47 #include "debug/HWPrefetch.hh" 50 #include "params/QueuedPrefetcher.hh" 57 RequestPtr req = std::make_shared<Request>(paddr, blk_size, 0, mid);
89 bool failed = (fault !=
NoFault);
96 p->max_prefetch_requests_with_pending_translation),
131 size_t max_pfs =
total;
134 size_t min_pfs = (total - throttle_pfs) == 0 ?
135 1 : (total - throttle_pfs);
136 max_pfs = min_pfs + (total - min_pfs) *
150 auto itr =
pfq.begin();
151 while (itr !=
pfq.end()) {
152 if (itr->pfInfo.getAddr() == blk_addr &&
153 itr->pfInfo.isSecure() == is_secure) {
155 itr =
pfq.erase(itr);
180 bool can_cross_page = (
tlb !=
nullptr);
184 DPRINTF(HWPrefetch,
"Found a pf candidate addr: %#x, " 185 "inserting into prefetch queue.\n", new_pfi.
getAddr());
187 insert(pkt, new_pfi, addr_prio.second);
189 if (num_pfs == max_pfs) {
193 DPRINTF(HWPrefetch,
"Ignoring page crossing prefetch.\n");
201 DPRINTF(HWPrefetch,
"Requesting a prefetch to issue.\n");
210 DPRINTF(HWPrefetch,
"No hardware prefetches available.\n");
219 assert(pkt !=
nullptr);
220 DPRINTF(HWPrefetch,
"Generating prefetch for %#x.\n", pkt->
getAddr());
233 .
desc(
"number of prefetch candidates identified");
237 .
desc(
"number of redundant prefetches already in prefetch queue");
241 .
desc(
"number of redundant prefetches already in cache/mshr dropped");
245 .
desc(
"number of prefetches dropped due to prefetch queue size");
249 .
desc(
"number of prefetches that crossed the page");
280 DPRINTF(HWPrefetch,
"%s Translation of vaddr %#x succeeded: " 282 it->translationRequest->getVaddr(),
283 it->translationRequest->getPaddr());
284 Addr target_paddr = it->translationRequest->getPaddr();
287 inMissQueue(target_paddr, it->pfInfo.isSecure()))) {
289 DPRINTF(HWPrefetch,
"Dropping redundant in " 290 "cache/MSHR prefetch addr:%#x\n", target_paddr);
293 it->createPkt(it->translationRequest->getPaddr(),
blkSize,
298 DPRINTF(HWPrefetch,
"%s Translation of vaddr %#x failed, dropping " 299 "prefetch request %#x \n",
tlb->
name(),
300 it->translationRequest->getVaddr());
311 for (it = queue.begin(); it != queue.end() && !found; it++) {
312 found = it->pfInfo.sameAddr(pfi);
316 if (it != queue.end()) {
318 if (it->priority < priority) {
320 it->priority = priority;
322 while (prev != queue.begin()) {
326 std::swap(*it, *prev);
330 DPRINTF(HWPrefetch,
"Prefetch addr already in " 331 "prefetch queue, priority updated\n");
333 DPRINTF(HWPrefetch,
"Prefetch addr already in " 344 RequestPtr translation_req = std::make_shared<Request>(pkt->
req->getAsid(),
346 pkt->
req->contextId());
348 return translation_req;
377 pkt->
req->getVaddr() : pkt->
req->getPaddr();
378 bool positive_stride = new_pfi.
getAddr() >= orig_addr;
380 (new_pfi.
getAddr() - orig_addr) : (orig_addr - new_pfi.
getAddr());
383 bool has_target_pa =
false;
390 target_paddr = positive_stride ? (pkt->
req->getPaddr() +
stride) :
393 target_paddr = new_pfi.
getAddr();
395 has_target_pa =
true;
400 if (!pkt->
req->hasContextId()) {
404 has_target_pa =
false;
407 }
else if (pkt->
req->hasVaddr()) {
408 has_target_pa =
false;
410 Addr target_vaddr = positive_stride ?
425 DPRINTF(HWPrefetch,
"Dropping redundant in " 426 "cache/MSHR prefetch addr:%#x\n", target_paddr);
435 DPRINTF(HWPrefetch,
"Prefetch queued. " 436 "addr:%#x priority: %3d tick:%lld.\n",
437 new_pfi.
getAddr(), priority, pf_time);
443 DPRINTF(HWPrefetch,
"Prefetch queued with no translation. " 444 "addr:%#x priority: %3d\n", new_pfi.
getAddr(), priority);
459 "Prefetch queue is both full and empty!");
463 "Prefetch queue is full with 1 element!");
467 while (cont && prev != queue.begin()) {
470 cont = prev->priority == it->priority;
475 DPRINTF(HWPrefetch,
"Prefetch queue full, removing lowest priority " 476 "oldest packet, addr: %#x\n",it->pfInfo.getAddr());
481 if (queue.size() == 0) {
482 queue.emplace_back(dpp);
487 }
while (it != queue.begin() && dpp > *it);
490 if (it == queue.begin() && dpp <= *it)
492 queue.insert(it, dpp);
RequestPtr translationRequest
Request used when a translation is needed.
Declares a basic cache interface BaseCache.
const Cycles latency
Cycles after generation when a prefetch can first be issued.
decltype(nullptr) constexpr NoFault
PrefetchInfo pfInfo
Prefetch info corresponding to this packet.
const unsigned queueSize
Maximum size of the prefetch queue.
void addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp)
Adds a DeferredPacket to the specified queue.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Bitfield< 21, 20 > stride
void translationComplete(DeferredPacket *dp, bool failed)
Indicates that the translation of the address of the provided deferred packet has been successfully c...
std::shared_ptr< Request > RequestPtr
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
BaseCache * cache
Pointr to the parent cache.
uint64_t usefulPrefetches
Total prefetches that has been useful.
System * system
System we are currently operating in.
void regStats() override
Register local statistics.
The request targets the secure memory space.
bool isSecure() const
Returns true if the address targets the secure memory space.
BaseTLB * tlb
Registered tlb for address translations.
const MasterID masterId
Request id for prefetches.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
std::list< DeferredPacket >::iterator iterator
ThreadContext * getThreadContext(ContextID tid) const
RequestPtr req
A pointer to the original request.
uint64_t issuedPrefetches
Total prefetches issued.
Addr getAddr() const
Obtains the address value of this Prefetcher address.
std::list< DeferredPacket > pfqMissingTranslation
Tick curTick()
The current simulated tick.
Class containing the information needed by the prefetch to train and generate new prefetch requests...
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) override
uint64_t Tick
Tick count type.
Addr getPC() const
Returns the program counter that generated this request.
Stats::Scalar pfRemovedFull
QueuedPrefetcher * owner
Owner of the packet.
void regStats() override
Register local statistics.
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)=0
The request is a prefetch.
void processMissingTranslations(unsigned max)
Starts the translations of the queued prefetches with a missing translation.
PacketPtr pkt
The memory packet generated by this prefetch.
void setTranslationRequest(const RequestPtr &req)
Sets the translation request needed to obtain the physical address of this request.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters...
virtual const std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
const bool cacheSnoop
Snoop the cache before generating prefetch (cheating basically)
const FlagsType total
Print the total.
QueuedPrefetcher(const QueuedPrefetcherParams *p)
const bool tagPrefetch
Tag prefetch with PC of generating access?
const bool queueFilter
Filter prefetches if already queued.
Derived & name(const std::string &name)
Set the name and marks this stat to print at the end of simulation.
bool alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority)
Checks whether the specified prefetch request is already in the specified queue.
const bool queueSquash
Squash queued prefetch if demand access observed.
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
PacketPtr getPacket() override
const unsigned int throttleControlPct
Percentage of requests that can be throttled.
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
size_t getMaxPermittedPrefetches(size_t total) const
Returns the maxmimum number of prefetch requests that are allowed to be created from the number of pr...
virtual void calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses)=0
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
virtual ~QueuedPrefetcher()
Derived & desc(const std::string &_desc)
Set the description and marks this stat to print at the end of simulation.
unsigned blkSize
The block size of the parent cache.
RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt)
void createPkt(Addr paddr, unsigned blk_size, MasterID mid, bool tag_prefetch, Tick t)
Create the associated memory packet.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
void startTranslation(BaseTLB *tlb)
Issues the translation request to the provided TLB.
std::shared_ptr< FaultBase > Fault
void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority)
void allocate()
Allocate memory for the packet.
Tick tick
Time when this prefetch becomes ready.
Stats::Scalar pfIdentified
Stats::Scalar pfBufferHit
ProbePointArg< PacketInfo > Packet
Packet probe point.
const unsigned missingTranslationQueueSize
Maximum size of the queue holding prefetch requests with missing address translations.
std::list< DeferredPacket > pfq
bool hasPC() const
Returns true if the associated program counter is valid.