Here is a list of all class members with links to the classes they belong to:

- n -

• n : ArmISA::PMU
• N : ArmISA::TlbEntry , QTIsaac< ALPHA > , testbench
• n_bits() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxtype_params , sc_dt::scfx_params
• n_cu : Shader
• n_master_ports : HMCController
• n_reg : GPUDynInst
• n_sign_bits : MultiperspectivePerceptron
• n_src : instr
• n_wf : Shader
• name() : A9GlobalTimer::Timer , ActivityRecorder , AddrOperandBase , AlphaISA::AlignmentFault , AlphaISA::ArithmeticFault , AlphaISA::DtbAcvFault , AlphaISA::DtbAlignmentFault , AlphaISA::DtbFault , AlphaISA::DtbPageFault , AlphaISA::FloatEnableFault , AlphaISA::IntegerOverflowFault , AlphaISA::InterruptFault , AlphaISA::ItbAcvFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::MachineCheckFault , AlphaISA::NDtbMissFault , AlphaISA::PalFault , AlphaISA::PDtbMissFault , AlphaISA::ProcessInfo , AlphaISA::RemoteGDB::AlphaGdbRegCache , AlphaISA::ResetFault , AlphaISA::UnimplementedOpcodeFault , AlphaISA::VectorEnableFault , ArchTimer , ArmISA::ArmFault::FaultVals , ArmISA::ArmFaultVals< T > , ArmISA::ProcessInfo , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , ArmSemihosting::SemiCall , ArmV8KvmCPU::IntRegInfo , ArmV8KvmCPU::MiscRegInfo , BaseGdbRegCache , BaseGen , BasePixelPump::PixelEvent , BaseRemoteGDB::GdbCommand , BaseRemoteGDB , BaseXBar::Layer< SrcType, DstType > , Brig::BrigDirectiveComment , Brig::BrigDirectiveExecutable , Brig::BrigDirectiveExtension , Brig::BrigDirectiveFbarrier , Brig::BrigDirectiveLabel , Brig::BrigDirectiveModule , Brig::BrigDirectiveVariable , Brig::BrigSectionHeader , CallbackQueue , ConditionRegisterState , CopyEngine::CopyEngineChannel , CpuLocalTimer::Timer , CxxConfigDirectoryEntry::ParamDesc , CxxConfigDirectoryEntry::PortDesc , CxxConfigManager::Exception , Debug::Flag , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DistEtherLink::Link , DmaCallback , DRAMCtrl::Rank , ElasticTrace , EmbeddedPyBind , EmulationPageTable , EtherInt , EtherLink::Link , EtherSwitch::Interface::PortFifo , Event , EventFunctionWrapper , EventQueue , EventWrapper< T, F > , ExecStage , FaultBase , FetchStage , FuncUnit , GenericAlignmentFault , GenericISA::M5FatalFault , GenericISA::M5HackFaultBase< Base > , GenericISA::M5InformFaultBase< Base > , GenericISA::M5PanicFault , GenericISA::M5WarnFaultBase< Base > , GenericPageTableFault , GlobalMemPipeline , HardBreakpoint , HsaCode , HsaObject , IGbE::DescCache< T > , InstructionQueue< Impl > , Intel8254Timer::Counter , Intel8254Timer , ItsCommand::DispatchEntry , ItsProcess , Kernel::Statistics , Label , LocalMemPipeline , LSQ< Impl > , LSQUnit< Impl > , MC146818 , MemDepUnit< MemDepPred, Impl >::MemDepEntry , MemDepUnit< MemDepPred, Impl > , MemoryImage::Segment , MipsISA::MipsFault< T > , MipsISA::MipsFaultBase::FaultVals , MipsISA::ProcessInfo , MipsISA::RemoteGDB::MipsGdbRegCache , Named , OutputStream , P9MsgInfo , PacketQueue , PAL , PCEvent , PciHost::DeviceInterface , PerfectSwitch , PhysicalMemory , Port , PowerISA::PowerFault , PowerISA::ProcessInfo , PowerISA::RemoteGDB::PowerGdbRegCache , ProbeListener , ProbePoint , ReExec , ReqPacketQueue , RespPacketQueue , RiscvISA::CSRMetadata , RiscvISA::ProcessInfo , RiscvISA::RemoteGDB::RiscvGdbRegCache , RiscvISA::Reset , RiscvISA::RiscvFault , ROB< Impl > , sc_core::sc_attr_base , sc_core::sc_event , sc_core::sc_object , sc_core::sc_process_handle , sc_core::sc_trace_params , sc_gem5::ClockTick , sc_gem5::Event , sc_gem5::Module , sc_gem5::Object , sc_gem5::Scheduler , ScheduleStage , Scoreboard , ScoreboardCheckStage , SimObject , SimpleThread , SimpleTrace , Sinic::Regs::Info , SMMUDeviceRetryEvent , SMMUProcess , SnoopRespPacketQueue , Sp804::Timer , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase::FaultVals , Stats::DataWrap< Derived, InfoProxyType > , Stats::DistPrint , Stats::Info , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::VectorPrint , StorageElement , StridePrefetcher::PCTable , SwitchingFiber , SyscallDesc , SyscallRetryFault , Throttle , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , UnifiedFreeList , UnimpFault , VecRegisterState , VirtIO9PBase::FSQueue , VirtIOBlock::RequestQueue , VirtIOConsole::TermRecvQueue , VirtIOConsole::TermTransQueue , VncServer::ServerInitMsg , X86ISA::ProcessInfo , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache , X86ISA::UnimpInstFault , X86ISA::Walker::WalkerState , X86ISA::X86FaultBase
• name_off : AlphaISA::ProcessInfo , ArmISA::ProcessInfo , MipsISA::ProcessInfo , X86ISA::ProcessInfo
• name_offs : HsaKernelInfo
• Named() : Named
• nameGen : sc_gem5::Module , sc_gem5::Process
• namelen : VncServer::ServerInitMsg
• nameLength : Brig::BrigSectionHeader
• nameOut() : Serializable::ScopedCheckpointSection
• nan() : sc_dt::scfx_ieee_double
• nand_reduce() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concatref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• native_listener : Trace::NativeTrace
• NativeTrace() : Trace::NativeTrace
• NativeTraceRecord() : Trace::NativeTraceRecord
• nb2b_thread() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• nb_bound() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_can_get() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_get_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_can_peek() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_peek_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_can_put() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_put_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_cb : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• nb_expand() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_func_type : tlm_utils::callback_binder_bw< TYPES > , tlm_utils::callback_binder_fw< TYPES >
• nb_get() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_get_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_peek() : tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T > , tlm::tlm_nonblocking_peek_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_poke() : tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T >
• nb_put() : tlm::tlm_fifo< T > , tlm::tlm_nonblocking_put_if< T > , tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• nb_read() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_nonblocking_in_if< T >
• nb_reduce() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_transport_bw() : sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , tlm::tlm_bw_nonblocking_transport_if< TRANS, PHASE > , tlm_utils::callback_binder_bw< TYPES > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process
• nb_transport_fw() : sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , tlm::tlm_fw_nonblocking_transport_if< TRANS, PHASE > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• nb_unbound() : tlm::tlm_fifo< T > , tlm::tlm_fifo_config_size_if
• nb_write() : sc_core::sc_fifo< T > , sc_core::sc_fifo_nonblocking_out_if< T > , sc_core::sc_fifo_out< T >
• nbest : MultiperspectivePerceptron
• nbits : sc_dt::sc_signed , sc_dt::sc_unsigned
• nbrOfBanksDRAM : DramGen
• nbrOfBanksUtil : DramGen
• nbrOfRanks : DramGen
• nbrOutstanding() : DRAMSim2
• nbrOutstandingReads : DRAMSim2
• nbrOutstandingWrites : DRAMSim2
• NBTransportPtr : tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• ndigits : sc_dt::sc_signed , sc_dt::sc_unsigned
• ndRange : GpuDispatcher
• ndRangeMap : GpuDispatcher
• nDS : Gicv3CPUInterface
• NDtbMissFault() : AlphaISA::NDtbMissFault
• need_stage() : InputUnit , VirtualChannel
• need_sync() : tlm_utils::tlm_quantumkeeper
• needCkpt : DistHeaderPkt::Header , DistIface::SyncNode
• needClose() : ArmSemihosting::File
• needExit : DistHeaderPkt::Header , DistIface::SyncNode
• needMoreBytes() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• needRetry : SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort
• NeedsResponse : MemCmd
• needsResponse() : MemCmd , Packet
• needsRetry() : SyscallReturn
• needsStart() : sc_gem5::Process
• needsToBeSentToStoreBuffer() : Minor::LSQ::LSQRequest
• needStopSync : DistHeaderPkt::Header , DistIface::SyncNode
• needsToTick() : Minor::LSQ
• needsTSO : LSQUnit< Impl >
• NeedsWritable : MemCmd
• needsWritable() : MemCmd , MSHR , MSHR::TargetList , Packet
• needToSendRequestRetry : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• needToSendRetry : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• needToSignalDrained : Minor::Pipeline
• needWB : LSQ< Impl >::LSQSenderState
• neg() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_pow10
• neg_scfx_rep : sc_dt::scfx_rep
• negative() : sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float
• negedge() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_gem5::ScSignalBaseBinary , sc_gem5::ScSignalBinary< T, WRITER_POLICY >
• negedge_event() : sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_gem5::ScSignalBinary< T, WRITER_POLICY >
• negedgeEvent() : sc_gem5::ScSignalBaseBinary
• neitherReadNorWriteReqs : DRAMCtrl::DRAMStats
• net_dest : RouteInfo
• NetDest() : NetDest
• netmask() : Net::IpNetmask
• Network() : Network
• NetworkInterface() : NetworkInterface
• NetworkLink() : NetworkLink
• Never : SETranslatingPortProxy
• neverSeen() : MultiperspectivePerceptron::FilterEntry
• new_address : tlm::tlm_endian_context
• new_bebuf : tlm::tlm_endian_context
• new_dbuf : tlm::tlm_endian_context
• new_eq : EventQueue::ScopedMigration
• newDynamicSensitivityEvent : sc_gem5::DynamicSensitivityEvent
• newDynamicSensitivityEventAndList : sc_gem5::DynamicSensitivityEventAndList
• newDynamicSensitivityEventOrList : sc_gem5::DynamicSensitivityEventOrList
• newest() : sc_gem5::Process
• newInfoSet : AlphaISA::Interrupts
• newIpl : AlphaISA::Interrupts
• newKernelEnds : GPUCoalescer
• newPCState : CheckerCPU
• newPhysReg : DefaultRename< Impl >::RenameHistory
• newPredictionSeqNum : Minor::BranchData
• newRequests : GPUCoalescer
• newState : Trace::ArmNativeTrace::ThreadState
• newStaticSensitivityEvent : sc_gem5::StaticSensitivityEvent
• newStaticSensitivityExport : sc_gem5::StaticSensitivityExport
• newStaticSensitivityFinder : sc_gem5::StaticSensitivityFinder
• newStaticSensitivityInterface : sc_gem5::StaticSensitivityInterface
• newStaticSensitivityPort : sc_gem5::StaticSensitivityPort
• newStreamSeqNum : Minor::BranchData
• newSummary : AlphaISA::Interrupts
• next() : ChunkGenerator , CopyEngineReg::DmaDesc , DependencyEntry< DynInstPtr > , ExtensionPool< T >::entry , FALRUBlk , mm::access , sc_dt::scfx_rep_node , sc_gem5::PythonInitFunc , sc_gem5::PythonReadyFunc , SwitchingFiber , tlm::tlm_endian_context , tlm_utils::instance_specific_extension_container , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , tlm_utils::time_ordered_list< PAYLOAD >::element , VirtDescriptor , vring_desc
• next_object() : sc_core::sc_simcontext
• next_time() : tlm_utils::time_ordered_list< PAYLOAD >
• next_trigger() : sc_core::sc_module , sc_core::sc_prim_channel
• nextAddr : ChunkGenerator , DmaReadFifo , LinearGen , WriteAllocator
• nextAddress() : TimerTable
• nextAt : DistIface::Sync
• nextBin : Event
• nextBurstAt : DRAMCtrl
• nextCycle() : Clocked
• nextDescAddr() : ArmISA::TableWalker::LongDescriptor
• nextElement : TraceGen
• nextExecute() : TraceCPU::FixedRetryGen
• nextGenerator() : BaseTrafficGen , PyTrafficGen , TrafficGen
• nextGlbMemBus : ComputeUnit
• nextGlbRdBus() : ComputeUnit
• NextGlobalsOffset : SparcISA::ISA
• nextIdxs() : ArmISA::VfpMacroOp
• nextInBin : Event
• nextIndex : StackDistCalc
• nextInsertCycle : Minor::FUPipeline
• nextInstAddr() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::PCStateBase , GPUStaticInst , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• nextIOState() : BaseKvmCPU::KVMCpuPort
• nextLevelPointer() : PageTableOps , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k
• nextLineAddr : HDLcd::DmaEngine
• nextListNode : sc_gem5::ListNode
• nextLocMemBus : ComputeUnit
• nextLocRdBus() : ComputeUnit
• nextMode : ArmISA::ArmFault::FaultVals , ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• nextModuleEntry : Brig::BrigDirectiveExecutable
• NextNameChars : sc_gem5::VcdTraceFile
• nextnlu() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• nextOffset : StorageSpace
• nextPacketTick() : BaseGen , BaseTrafficGen , ExitGen , IdleGen , LinearGen , RandomGen , TraceGen
• NextPage : SETranslatingPortProxy
• nextPC : TimeBufStruct< Impl >::decodeComm
• nextPixel() : BasePixelPump , HDLcd::PixelPump
• nextPrefetchReadyTime() : BasePrefetcher , MultiPrefetcher , QueuedPrefetcher
• nextPrivilegeLevel : SparcISA::SparcFaultBase::FaultVals
• nextProgressMessage : MemTest
• nextQueueReadyTime() : BaseCache
• nextRead : TraceCPU::ElasticDataGen
• nextReadyTime() : Queue< Entry >
• nextRepeat : DistIface::Sync
• nextReqEvent : DRAMCtrl , QoS::MemSinkCtrl
• nextReqTime : DRAMCtrl
• nextRequest : QoS::MemSinkCtrl
• nextSchedCu : Shader
• nextSeq() : X86ISA::TLB
• nextSeqCount : DramRotGen
• nextSerial : MemChecker
• nextSignalName() : sc_gem5::VcdTraceFile
• nextStageReserve : Minor::Decode , Minor::Fetch1 , Minor::Fetch2
• nextState : CopyEngine::CopyEngineChannel , TrafficGen , X86ISA::Walker::WalkerState
• nextTableAddr() : ArmISA::TableWalker::LongDescriptor
• nextTick() : EventQueue , LdsState::TickEvent
• nextToReplace : SMMUv3BaseCache
• nextTransitionTick : BaseTrafficGen
• nextVCPUID : KvmVM
• nextWalk() : ArmISA::TableWalker
• NextWindowOffset : SparcISA::ISA
• nHistoryTables : TAGEBase
• nIENBit : IdeDisk
• nill : tlm_utils::time_ordered_list< PAYLOAD >
• nInvalid : MathExpr
• nlink_t : RiscvLinux64 , Solaris
• nlu : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• nmiVector : X86ISA::Interrupts
• nmrr : ArmISA::TLB
• NN_CONFIG_MASK : GicV2
• nnpc() : GenericISA::DelaySlotPCState< MachInst >
• NO_ACCESS : Request
• no_retry_on_stall : RubyPort::MemSlavePort
• NO_ROW : DRAMCtrl::Bank
• NoAccess : MemBackdoor
• NoAddrRangeCoverage : Minor::LSQ
• noAllocateLimit : WriteAllocator
• NoBranch : Minor::BranchData
• NoCapableFU : FUPool
• NoCommand : X86ISA::I8042
• noCostFUIndex : Minor::Execute
• Node() : MathExpr::Node , StackDistCalc::Node
• node : Stats::Temp , ThermalDomain , ThermalReference
• Node() : Trie< Key, Value >::Node
• node1 : ThermalCapacitor , ThermalResistor
• node2 : ThermalCapacitor , ThermalResistor
• nodeIndex : StackDistCalc::Node
• NodeList() : sc_gem5::NodeList< T >
• nodename : Linux::utsname , OperatingSystem::utsname , Solaris::utsname
• NodeRobNum : TraceCPU::ElasticDataGen
• nodes : TCPIface , ThermalModel
• NodeSeqNum : TraceCPU::ElasticDataGen
• nodesRemoved : DependencyGraph< DynInstPtr >
• nodesTraversed : DependencyGraph< DynInstPtr >
• noExec : X86ISA::TlbEntry
• nofault() : SparcISA::PageTableEntry
• NoFreeFU : FUPool
• NoGoodAddr : DefaultFetch< Impl >
• nomali : NoMaliGpu
• NoMaliGpu() : NoMaliGpu
• nomaliInfo : NoMaliGpu
• nonCacheable : ArmISA::TlbEntry
• NonCachingSimpleCPU() : NonCachingSimpleCPU
• NoncoherentCache() : NoncoherentCache
• NoncoherentXBar() : NoncoherentXBar
• NoncoherentXBarMasterPort() : NoncoherentXBar::NoncoherentXBarMasterPort
• NoncoherentXBarSlavePort() : NoncoherentXBar::NoncoherentXBarSlavePort
• NonConstPolicy : sc_core::sc_direct_access< Element > , sc_core::sc_member_access< Element, Access > , sc_core::sc_vector_iter< Element, AccessPolicy >
• NonConstT : RefCountingPtr< T >
• none : cp::Format
• NONE : DefaultRename< Impl >
• noneActive() : VecPredRegT< VecElem, NumElems, Packed, Const >
• noneSet() : Flags< T >
• NonMaskableInterrupt() : X86ISA::NonMaskableInterrupt
• nonSecure() : ArmISA::ISA::MiscRegLUTEntryInitializer
• nonSpecInstReady() : MemDepUnit< MemDepPred, Impl >
• nonSpecInsts : InstructionQueue< Impl >
• NonSpecMapIt : InstructionQueue< Impl >
• nonSpecSeqNum : TimeBufStruct< Impl >::commitComm
• noOutput() : Stats::Text
• Nop() : SparcISA::Nop
• noProgress() : BaseTrafficGen
• noProgressEvent : BaseTrafficGen
• nopStaticInstPtr : StaticInst
• nor_reduce() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concatref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• noRequest() : MemTest
• noRequestEvent : MemTest
• noResponse() : MemTest
• noResponseCycles : GarnetSyntheticTraffic
• noResponseEvent : MemTest
• normal : sc_dt::scfx_rep
• normalize() : sc_dt::scfx_rep
• NormalPhase : VncServer
• NormalTran : ArmISA::TLB
• noSkip : TAGEBase
• noSquashFromTC : O3ThreadState< Impl >
• not_a_number : sc_dt::scfx_rep
• not_table : sc_dt::sc_logic
• notAnInst() : BaseDynInst< Impl >
• NotAnInst : BaseDynInst< Impl >
• noTargetMSHR : BaseCache
• NotDraining : Minor::Execute
• noThrow() : Iris::ThreadContext
• notIdleFraction : SimpleExecContext
• notify() : ArmISA::PMU::RegularEvent::RegularProbe , BaseMemProbe::PacketListener , BasePrefetcher , BasePrefetcher::PrefetchListener , MultiPrefetcher , PIFPrefetcher::PrefetchListenerPC , PowerModel::ThermalProbeListener , ProbeListenerArg< T, Arg > , ProbeListenerArgBase< Arg > , ProbePointArg< Arg > , QueuedPrefetcher , sc_core::sc_event , sc_core::sc_event_queue , sc_core::sc_event_queue_if , sc_gem5::Event , sc_gem5::Sensitivity , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES > , tlm_utils::peq_with_get< PAYLOAD >
• notify_delayed() : sc_core::sc_event
• notifyDelayed() : sc_gem5::Event
• notifyFill() : BasePrefetcher , BOPPrefetcher , MultiPrefetcher , SBOOEPrefetcher
• notifyFork() : BaseKvmCPU , CowDiskImage , Drainable , KvmVM , RawDiskImage
• notifyInterface() : SerialDevice
• notifyRetiredInst() : PIFPrefetcher
• notifyWgCompl() : GpuDispatcher
• notifyWork() : sc_gem5::DynamicSensitivityEventAndList , sc_gem5::DynamicSensitivityEventOrList , sc_gem5::Sensitivity
• NotIssued : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• notTakenCounters : BiModeBP
• notTakenPred : BiModeBP::BPHistory
• notTakenThreshold : BiModeBP
• NP : Gicv3CPUInterface
• npc() : GenericISA::SimplePCState< MachInst > , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache
• nphalt : PAL
• NPIE : Gicv3CPUInterface , VGic
• nres_error_head : SparcISA::ISA
• nres_error_tail : SparcISA::ISA
• ns : ArmISA::TlbEntry
• nsAccessToSecInt() : Gicv3Distributor
• nscfg : StreamTableEntry
• nsec() : Time
• NSEC_PER_MSEC : Time
• NSEC_PER_SEC : Time
• NSEC_PER_USEC : Time
• NSGigE() : NSGigE
• NSGigEInt() : NSGigEInt
• nsh : ArmISA::PMU
• nsk : ArmISA::PMU
• nState : Trace::ArmNativeTrace , Trace::X86NativeTrace
• nstid : ArmISA::TlbEntry
• nsu : ArmISA::PMU
• Nucleus : SparcISA::TLB
• null() : AtagHeader , AtagNone
• nullCallback() : IGbE::TxDescCache
• nullEvent : IGbE::TxDescCache
• nullStaticInstPtr : StaticInst
• num() : ArmInterruptPin , FastModel::CortexA76 , Intel8254Timer::Counter , KvmVM::MemSlot , MachineID , vring
• num_args : HsaQueueEntry
• num_attributes() : sc_core::sc_object , sc_gem5::Object
• num_available() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_in_if< T >
• NUM_BASER_REGS : Gicv3Its
• num_bits() : sc_dt::sc_signed , sc_dt::sc_unsigned
• NUM_BITS : VecPredRegContainer< NumBits, Packed > , VecPredRegT< VecElem, NumElems, Packed, Const >
• NUM_BLOCKED_CAUSES : BaseCache
• NUM_COMMAND_ATTRIBUTES : MemCmd
• num_dest_operands : HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
• num_encodings : VncInput::PixelEncodingsMessage
• num_fds : PollQueue
• num_free() : sc_core::sc_fifo< T > , sc_core::sc_fifo_out< T > , sc_core::sc_fifo_out_if< T >
• num_kernelLaunched : GpuDispatcher
• num_kernels : HsaDriverSizes
• num_lanes : SerialLink
• NUM_LOG_LEVELS : Logger
• NUM_LR : VGic
• NUM_MEM_CMDS : MemCmd
• NUM_MMAP_FLAGS : AlphaLinux , ArmLinux32 , ArmLinux64 , MipsLinux , PowerLinux , RiscvLinux32 , RiscvLinux64 , SparcLinux , SparcSolaris , X86Linux32 , X86Linux64
• NUM_OF_PERF_LEVELS : EnergyCtrl
• NUM_OPEN_FLAGS : AlphaLinux , ArmFreebsd32 , ArmFreebsd64 , ArmLinux32 , ArmLinux64 , MipsLinux , PowerLinux , RiscvLinux32 , RiscvLinux64 , SparcLinux , SparcSolaris , X86Linux32 , X86Linux64
• NUM_PATTERNS : BaseDelta< BaseType, DeltaSizeBits > , CPack , FPCD , RepeatedQwordsCompressor , ZeroCompressor
• num_rects : VncServer::FrameBufferUpdate
• NUM_ROOT_PROCS : MipsLinux
• NUM_SKEWING_FUNCTIONS : SkewedAssociative
• num_src_operands : HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
• Num_StageId : Minor::Pipeline
• Num_Syscall32_Descs : SparcISA::SparcLinuxProcess
• Num_Syscall_Descs : AlphaISA::AlphaLinuxProcess , MipsLinuxProcess , PowerLinuxProcess , SparcISA::SparcLinuxProcess , SparcISA::SparcSolarisProcess
• numAccessesInDTLB : Minor::LSQ
• numAccessesInMemorySystem : Minor::LSQ
• numAccessesIssuedToMemory : Minor::LSQ
• numActiveThreads() : FullO3CPU< Impl >
• numAllocatedStreams : Prefetcher
• numALUInstsExecuted : ComputeUnit
• numBanksActive : DRAMCtrl::Rank
• number : Arguments , EtherLink::Link , FUDesc , IntSinkPinBase , PacketFifoEntry , Terminal , VncServer
• number_of_fault_types : FaultModel
• numberOfAllocations : Gem5SystemC::MemoryManager
• numberOfFrees : Gem5SystemC::MemoryManager
• numBlocks : BaseTags
• numBlocksPerSector : SectorTags
• numBranches : SimpleExecContext
• numBranchMispred : SimpleExecContext
• numBusyCycles : SimpleExecContext
• numBytes : ArmISA::Stage2MMU::Stage2Translation , DmaPort::DmaReqState
• numCallsReturns : SimpleExecContext
• numCASOps : ComputeUnit
• numCCDestRegs() : BaseDynInst< Impl > , StaticInst
• numCCPhysRegs() : PhysRegFile
• numCCRegReads : SimpleExecContext
• numCCRegWrites : SimpleExecContext
• numCkptReq : DistIface::SyncSwitch
• numCoalescedMMIO : BaseKvmCPU
• NumCodes : PAL
• numCommittedDist : DefaultCommit< Impl >
• numCondCtrlInsts : SimpleExecContext
• numContexts() : BaseCPU , System
• numCPUs : AlphaAccess , MipsAccess
• NumCSRs : RiscvISA::RemoteGDB
• numCycles : BaseCPU , sc_gem5::Scheduler , Ticked
• numCyclesLocal : Ticked
• numCyclesPerLoadTransfer : ComputeUnit
• numCyclesPerStoreTransfer : ComputeUnit
• numCyclesWithInstrIssued : ExecStage
• numCyclesWithInstrTypeIssued : ExecStage
• numCyclesWithNoInstrTypeIssued : ExecStage
• numCyclesWithNoIssue : ExecStage
• numDataArrayReads : CacheMemory
• numDataArrayStalls : CacheMemory
• numDataArrayWrites : CacheMemory
• numDepts : ElasticTrace::TraceInfo
• numDestinations : GarnetSyntheticTraffic
• numDestRegs() : BaseDynInst< Impl > , StaticInst
• NumDeviceIds : Iob
• numDiscardedOps : Minor::MinorStats
• numDispLeft : HsaQueueEntry , NDRange
• numDomains() : DVFSHandler
• numDroppedPrefetches : Prefetcher
• numDstRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numEntries : AssociativeSet< Entry > , BaseDictionaryCompressor , DefaultBTB , DependencyGraph< DynInstPtr > , InstructionQueue< Impl > , Queue< Entry > , ReturnAddrStack , ROB< Impl >
• numEntriesFirstLocalHistories : StatisticalCorrector
• numEntriesSecondLocalHistories : MPP_StatisticalCorrector_64KB , TAGE_SC_L_64KB_StatisticalCorrector
• numEntriesThirdLocalHistories : MPP_StatisticalCorrector_64KB , TAGE_SC_L_64KB_StatisticalCorrector
• numExitReq : DistIface::SyncSwitch
• numExitSignal : BaseKvmCPU
• numFailedCASOps : ComputeUnit
• NumFaultSources : ArmISA::ArmFault
• numFetchesInITLB : Minor::Fetch1
• numFetchesInMemorySystem : Minor::Fetch1
• numFetchingThreads : DefaultFetch< Impl >
• numFetchSuspends : Minor::MinorStats
• numFilteredNodes : ElasticTrace
• numFloatPhysRegs() : PhysRegFile
• numFpAluAccesses : SimpleExecContext
• numFPDestRegs() : BaseDynInst< Impl > , StaticInst
• numFpInsts : SimpleExecContext
• numFpRegReads : SimpleExecContext
• numFpRegWrites : SimpleExecContext
• numFragments : LSQ< Impl >::SplitDataRequest , Minor::LSQ::SplitDataRequest
• numFreeCCEntries() : UnifiedRenameMap
• numFreeCCRegs() : UnifiedFreeList
• numFreeEntries() : InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl > , SimpleRenameMap , UnifiedRenameMap
• numFreeFloatEntries() : UnifiedRenameMap
• numFreeFloatRegs() : UnifiedFreeList
• numFreeIntEntries() : UnifiedRenameMap
• numFreeIntRegs() : UnifiedFreeList
• numFreeLoadEntries() : LSQ< Impl > , LSQUnit< Impl >
• numFreePredEntries() : UnifiedRenameMap
• numFreeRegs() : SimpleFreeList
• numFreeStoreEntries() : LSQ< Impl > , LSQUnit< Impl >
• numFreeVecElems() : UnifiedFreeList
• numFreeVecEntries() : UnifiedRenameMap
• numFreeVecPredRegs() : UnifiedFreeList
• numFreeVecRegs() : UnifiedFreeList
• numFU : FUPool
• numFuncUnits : Minor::Execute
• NumGDBRegs : RiscvISA::RemoteGDB
• numGlbMemUnits : ComputeUnit
• NumGlobalRegs : SparcISA::ISA
• numGoodPrefetches : AccessMapPatternMatching
• numHalt : BaseKvmCPU
• numHashes : BloomFilter::MultiBitSel
• numHits : Prefetcher
• numHypercalls : BaseKvmCPU
• numIdleCycles : SimpleExecContext
• numIncomplete : MemChecker::WriteCluster
• numInflight() : X86ISA::Walker::WalkerState
• numInFlightFetches() : Minor::Fetch1
• numInFlightLoads : TraceCPU::ElasticDataGen::HardwareResource
• numInFlightStores : TraceCPU::ElasticDataGen::HardwareResource
• numInService() : Queue< Entry >
• numInst : CheckerCPU , DefaultFetch< Impl > , SimpleExecContext , ThreadState
• numInstrExecuted : ComputeUnit
• numInsts : BaseKvmCPU , HsaCode , Minor::ForwardInstData , Minor::MinorStats , SimpleExecContext , ThreadState
• numInstsInROB : ROB< Impl >
• numIntAluAccesses : SimpleExecContext
• numIntDestRegs() : BaseDynInst< Impl > , StaticInst
• numInterrupts : BaseKvmCPU
• numIntInsts : SimpleExecContext
• numIntPhysRegs() : PhysRegFile
• numInTranslationFragments : LSQ< Impl >::LSQRequest , Minor::LSQ::SplitDataRequest
• numIntRegReads : SimpleExecContext
• numIntRegWrites : SimpleExecContext
• numIO : BaseKvmCPU
• numIssuedDist : InstructionQueue< Impl >
• numIssuedFragments : Minor::LSQ::SplitDataRequest
• numIssueOrderDepLoads : ElasticTrace
• numIssueOrderDepOther : ElasticTrace
• numIssueOrderDepStores : ElasticTrace
• numItems() : X86ISA::MediaOpBase
• numIter : LoopPredictor::LoopEntry
• numKernels() : BrigObject , HsaObject
• numLeaves : TreePLRURP
• numLeft : Barrier
• NumLevels : SparcISA::SparcFaultBase
• numLines : HDLcd::DmaEngine
• NumLines : X86ISA::I8259
• numLoad : CheckerCPU , SimpleExecContext , ThreadState
• numLoadInsts : SimpleExecContext
• numLoads() : LSQ< Impl > , LSQUnit< Impl >
• numLocMemUnits : ComputeUnit
• numMemRefs : SimpleExecContext , ThreadState
• numMemUnits : ExecStage , ScheduleStage , ScoreboardCheckStage
• numMicroops : ArmISA::Memory64 , ArmISA::Memory , ArmISA::PredMacroOp , ArmISA::RfeOp , ArmISA::SrsOp , SparcISA::SparcMacroInst , X86ISA::MacroopBase , X86ISAInst::MicrocodeRom
• numMissedPrefetchedBlocks : Prefetcher
• numMisses : IndirectMemoryPrefetcher::IndirectPatternDetectorEntry
• numMissObserved : Prefetcher
• numMMIO : BaseKvmCPU
• numNodes : DistIface::SyncSwitch
• numOp : SimpleExecContext , ThreadState
• numOps : Minor::MinorStats , SimpleExecContext , ThreadState , TraceCPU
• numOrderDepStores : ElasticTrace
• numOrdinalHistories : StatisticalCorrector::SCThreadHistory
• numOther : AbstractMemory::MemStats
• numPackets : BaseTrafficGen::StatGroup
• numPacketsMax : GarnetSyntheticTraffic
• numPacketsSent : GarnetSyntheticTraffic
• numPagesCrossed : Prefetcher
• numPartialHits : Prefetcher
• numPerfLevels() : DVFSHandler , SrcClockDomain
• numPhysicalCCRegs : PhysRegFile
• numPhysicalFloatRegs : PhysRegFile
• numPhysicalIntRegs : PhysRegFile
• numPhysicalVecElemRegs : PhysRegFile
• numPhysicalVecPredRegs : PhysRegFile
• numPhysicalVecRegs : PhysRegFile
• numPhysRegs : InstructionQueue< Impl > , Scoreboard
• numPinnedWrites : RegId
• numPinnedWritesToComplete : PhysRegId
• numPlanes : FlashDevice
• numPredictedBranches : SimpleExecContext
• numPredPhysRegs() : PhysRegFile
• numPrefetchAccepted : Prefetcher
• numPrefetchRequested : Prefetcher
• numPriorities() : QoS::MemCtrl
• numPwrStateTransitions : ClockedObject::ClockedObjectStats
• numRawCacheHits : AccessMapPatternMatching
• numRawCacheMisses : AccessMapPatternMatching
• numRdRetry : DRAMCtrl::DRAMStats
• numReadRetries : QoS::MemSinkCtrl
• numReads : AbstractMemory::MemStats , MemTest
• numReadsStat : MemTest
• numReadWriteTurnArounds : QoS::MemCtrl::MemCtrlStats
• numReceivedPackets : LSQ< Impl >::SplitDataRequest
• numRegDep : ElasticTrace , TraceCPU::ElasticDataGen::GraphNode
• numRegs : ArmISA::MicroNeonMixOp64
• numregs : ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >
• numRegs : ArmISA::VldMultOp64 , ArmISA::VstMultOp64 , ConditionRegisterState , Minor::Scoreboard , VectorRegisterFile , X86ISA::Cmos
• numRegsPerSimd : VectorRegisterFile
• numReserve : Queue< Entry >
• numReservedSlots : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• numResults : Minor::Scoreboard
• numRetiredFragments : Minor::LSQ::SplitDataRequest
• numRetries : BaseTrafficGen::StatGroup
• numRetrySucceeded : TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen
• numRobDep : TraceCPU::ElasticDataGen::GraphNode
• numROBFreeEntries() : DefaultCommit< Impl >
• numRobs : DefaultCommit< Impl >
• numRRPVBits : BRRIPRP
• numRunningContexts() : System
• numSchedDcacheEvent : TraceCPU
• numSchedIcacheEvent : TraceCPU
• NumSectionIndices : BrigObject
• numSectors : SectorTags
• numSendAttempted : TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen
• numSendFailed : TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen
• numSendSucceeded : TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen
• numSeqPkts : DramGen
• numSets : BaseIndexingPolicy , SimpleIndirectPredictor , X86ISA::GpuTLB
• numShrMemPipes : ScoreboardCheckStage
• numSIMDs : ComputeUnit , ExecStage , FetchStage , ScheduleStage , ScoreboardCheckStage
• numSimulatedCPUs() : BaseCPU
• numSimulatedInsts() : BaseCPU
• numSimulatedOps() : BaseCPU
• numSlots : Minor::LSQ::StoreBuffer
• numSOLoads : TraceCPU::ElasticDataGen
• numSOStores : TraceCPU::ElasticDataGen
• numSplitReqs : TraceCPU::ElasticDataGen
• numSquashable : ArmISA::TableWalker , X86ISA::Walker
• numSrcRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numSrcRegs() : BaseDynInst< Impl > , StaticInst
• numStages : ActivityRecorder
• NumStages : FullO3CPU< Impl >
• numStages : WaitClass
• NumStatus : BaseDynInst< Impl >
• numStayReadState : QoS::MemCtrl::MemCtrlStats
• numStayWriteState : QoS::MemCtrl::MemCtrlStats
• numStopSyncReq : DistIface::SyncSwitch
• numStoreInsts : SimpleExecContext
• numStores() : LSQ< Impl > , LSQUnit< Impl >
• numStoresInTransfers : Minor::LSQ
• numStoresToWB() : LSQ< Impl > , LSQUnit< Impl >
• numStructElems : ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::VldMultOp64 , ArmISA::VldSingleOp64 , ArmISA::VstMultOp64 , ArmISA::VstSingleOp64
• numSuppressed : BaseTrafficGen::StatGroup
• numSwitches() : Topology
• numSyscallDescs : X86ISA::X86Process
• numSyscalls : Process
• numSystemsRunning : System
• numTagArrayReads : CacheMemory
• numTagArrayStalls : CacheMemory
• numTagArrayWrites : CacheMemory
• numTarget : BaseCache
• numThreads : BaseCPU , BPredUnit , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , InstructionQueue< Impl > , LSQ< Impl > , MipsISA::ISA , ROB< Impl >
• numTimesBlockedDueRAWDependencies : Wavefront
• numTimesBlockedDueVrfPortAvail : Wavefront
• numTimesBlockedDueWAXDependencies : Wavefront
• numTimesWgBlockedDueVgprAlloc : ComputeUnit
• numTotalPrefetches : AccessMapPatternMatching
• numTraceCPUs : TraceCPU
• numTrackedCaches : FALRU::CacheTracking
• numTransActiveIdle : ExecStage
• numTranslatedFragments : LSQ< Impl >::LSQRequest , Minor::LSQ::SplitDataRequest
• numUniquePages : X86ISA::GpuTLB
• numUnissuedAccesses : Minor::LSQ::StoreBuffer
• numUnissuedStores() : Minor::LSQ::StoreBuffer
• numUnmatchedBits : DictionaryCompressor< T >::Pattern
• numUnpredictableResults : Minor::Scoreboard
• numUseAltOnNa : TAGEBase
• numVecAluAccesses : SimpleExecContext
• numVecDestRegs() : BaseDynInst< Impl > , StaticInst
• numVecElemDestRegs() : BaseDynInst< Impl > , StaticInst
• NumVecElemPerVecReg : BaseO3DynInst< Impl > , PhysRegFile
• numVecElemPhysRegs() : PhysRegFile
• numVecInsts : SimpleExecContext
• numVecOpsExecuted : ComputeUnit
• numVecPhysRegs() : PhysRegFile
• numVecPredDestRegs() : BaseDynInst< Impl > , StaticInst
• numVecPredRegReads : SimpleExecContext
• numVecPredRegWrites : SimpleExecContext
• numVecRegReads : SimpleExecContext
• numVecRegsPerSimd : ComputeUnit
• numVecRegWrites : SimpleExecContext
• numVMExits : BaseKvmCPU
• numVMHalfEntries : BaseKvmCPU
• numVnicDistance : Sinic::Device
• numVoltages() : VoltageDomain
• numVpes : MipsISA::ISA
• numWaiting : Barrier
• numWays : SimpleIndirectPredictor
• numWg : NDRange
• numWgCompleted : NDRange
• numWgTotal : NDRange
• NumWindowedRegs : SparcISA::ISA
• numWorkIds : System
• numWorkItemsCompleted : BaseCPU
• numWorkItemsStarted : BaseCPU
• numWriteReadTurnArounds : QoS::MemCtrl::MemCtrlStats
• numWriteRetries : QoS::MemSinkCtrl
• numWrites : AbstractMemory::MemStats , MemTest
• numWritesStat : MemTest
• numWrRetry : DRAMCtrl::DRAMStats
• nupc() : GenericISA::DelaySlotUPCState< MachInst > , GenericISA::UPCState< MachInst >
• NVecElems : UnifiedRenameMap
• NvFlags : RealViewCtrl
• NvFlagsClr : RealViewCtrl
• nvram : SparcSystem
• nvramSymtab : SparcSystem
• nxt() : Net::Ip6Hdr , Net::Ip6Opt
• nxtAvail : WaitClass
• nxtBusy : VectorRegisterFile