core.hh File Reference

#include <string>
#include "base/types.hh"
#include "sim/eventq.hh"

Go to the source code of this file.

Namespaces
	SimClock
	These are variables that are set based on the simulator frequency.
	SimClock::Float
	SimClock::Int
	These variables equal the number of ticks in the unit of time they're named after in a 64 bit integer.

Functions
Tick	curTick ()
	The universal simulation clock. More...
void	fixClockFrequency ()
bool	clockFrequencyFixed ()
void	setClockFrequency (Tick ticksPerSecond)
Tick	getClockFrequency ()
void	setOutputDir (const std::string &dir)
void	registerExitCallback (Callback *callback)
	Register an exit callback. More...
void	doExitCleanup ()
	Do C++ simulator exit processing. More...

Variables
const Tick	retryTime = 1000

Function Documentation

clockFrequencyFixed()

bool clockFrequencyFixed

(

)

Definition at line 112 of file core.cc.

Referenced by pybind_init_core(), sc_core::sc_set_default_time_unit(), and sc_core::sc_set_time_resolution().

curTick()

Tick curTick ( )

inline

The universal simulation clock.

The current simulated tick.

Definition at line 47 of file core.hh.

References _curEventQueue, and EventQueue::getCurTick().

Referenced by SBOOEPrefetcher::access(), DRAMSim2::accessAndRespond(), DRAMCtrl::accessAndRespond(), FlashDevice::accessDevice(), SimpleCache::accessTiming(), FlashDevice::actionComplete(), O3ThreadContext< Impl >::activate(), SimpleThread::activate(), FullO3CPU< O3CPUImpl >::activateContext(), ElasticTrace::addDepTraceRecord(), DRAMCtrl::addToReadQueue(), DRAMCtrl::addToWriteQueue(), CacheMemory::allocate(), BaseTrafficGen::allocateWaitingRespSlot(), DefaultFetch< Impl >::buildInst(), BaseXBar::calcPacketTiming(), DistIface::RecvScheduler::calcReceiveTick(), BaseCache::calculateAccessLatency(), SBOOEPrefetcher::calculatePrefetch(), NetworkInterface::calculateVC(), VncInput::captureFrameBuffer(), Sinic::Device::changeConfig(), AlphaISA::Kernel::Statistics::changeMode(), TraceCPU::checkAndSchedExitEvent(), FlashDevice::checkDrain(), DRAMCtrl::Rank::checkDrainDone(), IGbE::chkInterrupt(), DRAMCtrl::chooseNextFRFCFS(), BaseCache::CacheSlavePort::clearBlocked(), UFSHostDevice::clearInterrupt(), Intel8254Timer::Counter::CounterEvent::clocksLeft(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), MemTest::completeRequest(), LSQUnit< Impl >::completeStore(), SMMUTranslationProcess::completeTransaction(), ClockedObject::computeStats(), DRAMCtrl::Rank::computeStats(), BaseTags::computeStatsVisitor(), Sinic::Base::cpuInterrupt(), NSGigE::cpuInterrupt(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), IGbE::cpuPostInt(), CPUProgressEvent::CPUProgressEvent(), X86ISA::GpuTLB::curCycle(), Shader::curCycle(), TLBCoalescer::curCycle(), TraceCPU::dcacheRetryRecvd(), DefaultDecode< Impl >::decodeInsts(), PacketQueue::deferredPacketReady(), MSHR::delay(), BOPPrefetcher::delayQueueEventWrapper(), MessageBuffer::dequeue(), SimpleMemory::dequeue(), Sinic::Device::devIntrChangeMask(), NSGigE::devIntrChangeMask(), Sinic::Device::devIntrPost(), NSGigE::devIntrPost(), Shader::dispatch_workgroups(), DefaultIEW< Impl >::dispatchInsts(), Pl111::dmaDone(), SMMUProcess::doBroadcastSignal(), IdeDisk::doDmaDataRead(), IdeDisk::doDmaDataWrite(), IdeDisk::doDmaRead(), IdeDisk::doDmaTransfer(), IdeDisk::doDmaWrite(), DRAMCtrl::doDRAMAccess(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptorWrapper(), SMMUProcess::doSemaphoreUp(), doSimLoop(), ThermalModel::doStep(), StoreTrace::downgrade(), DRAMCtrl::drain(), PCEventQueue::dump(), Trace::TarmacParserRecord::dump(), EventQueue::dump(), CheckerCPU::dumpAndExit(), EtherDump::dumpPacket(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), LdsState::earliestReturnTime(), EtherSwitch::Interface::enqueue(), TraceGen::enter(), Event::Event(), Shader::exec(), TraceCPU::ElasticDataGen::execute(), exitSimLoop(), DefaultFetch< Impl >::fetch(), IGbE::DescCache< iGbReg::RxDesc >::fetchDescriptors(), IGbE::DescCache< iGbReg::RxDesc >::fetchDescriptors1(), ElasticTrace::fetchReqTrace(), GoodbyeObject::fillBuffer(), UFSHostDevice::finalUTP(), Minor::LSQ::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), ArmISA::flattenIntRegModeIndex(), DRAMCtrl::Rank::flushCmdList(), getElapsedTimeMicro(), getElapsedTimeNano(), Queue< WriteQueueEntry >::getNext(), BaseCache::getNextQueueEntry(), MultiPrefetcher::getPacket(), MipsISA::haltThread(), MipsISA::handleLockedWrite(), RiscvISA::handleLockedWrite(), Checker< O3CPUImpl >::handlePendingInt(), MemTraceProbe::handleRequest(), DmaPort::handleResp(), SimpleCache::handleResponse(), MSHR::handleSnoop(), X86ISA::GpuTLB::handleTranslationReturn(), RubyPort::MemSlavePort::hitCallback(), RubyDirectedTester::hitCallback(), CPA::hwWe(), TraceCPU::icacheRetryRecvd(), Check::initiateAction(), Check::initiateCheck(), Check::initiateFlush(), Check::initiatePrefetch(), QueuedPrefetcher::insert(), CacheBlk::insert(), BaseTags::insertBlock(), BOPPrefetcher::insertIntoDelayQueue(), GPUCoalescer::insertRequest(), Minor::Execute::issue(), Sequencer::issueRequest(), GPUCoalescer::issueRequest(), X86ISA::GpuTLB::issueTLBLookup(), EtherSwitch::Interface::learnSenderAddr(), BaseRemoteGDB::listen(), QoS::MemCtrl::logRequest(), QoS::MemCtrl::logResponse(), EtherSwitch::Interface::lookupDestPort(), UFSHostDevice::LUNSignal(), PseudoInst::m5checkpoint(), PseudoInst::m5exit(), PseudoInst::m5fail(), SMMUTranslationProcess::main(), VIPERCoalescer::makeRequest(), GPUCoalescer::makeRequest(), MemTest::MemTest(), RubySystem::memWriteback(), DRAMCtrl::minBankPrep(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), TraceCPU::FixedRetryGen::nextExecute(), RandomGen::nextPacketTick(), LinearGen::nextPacketTick(), TraceGen::nextPacketTick(), SBOOEPrefetcher::notifyFill(), GpuDispatcher::notifyWgCompl(), BaseXBar::Layer< MasterPort, SlavePort >::occupyLayer(), Linux::openSpecialFile(), DistIface::packetOut(), ArmISA::TableWalker::pendingChange(), DVFSHandler::perfLevel(), Stats::periodicStatDump(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), Minor::Decode::popInput(), DistIface::RecvScheduler::popPacket(), IGbE::postInterrupt(), BaseSimpleCPU::preExecute(), Stats::AvgStor::prepare(), Stats::AvgSampleStor::prepare(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), Trace::TarmacTracerRecord::TraceInstEntry::print(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::print(), Trace::TarmacTracerRecord::TraceRegEntry::print(), Trace::TarmacTracerRecordV8::TraceMemEntryV8::print(), Trace::TarmacTracerRecord::TraceMemEntry::print(), Trace::TarmacParserRecord::printMismatchHeader(), MC146818::RTCEvent::process(), GlobalSimLoopExitEvent::process(), Stats::SimTicksReset::process(), MC146818::RTCTickEvent::process(), AnnotateDumpCallback::process(), CPUProgressEvent::process(), DumpStatsPCEvent::process(), GlobalSyncEvent::process(), Stats::StatEvent::process(), DistIface::SyncEvent::process(), DRAMCtrl::Rank::processActivateEvent(), HelloObject::processEvent(), Uart8250::processIntrEvent(), QoS::MemSinkCtrl::processNextReqEvent(), DRAMCtrl::processNextReqEvent(), DRAMCtrl::Rank::processPowerEvent(), DRAMCtrl::Rank::processPrechargeEvent(), TLBCoalescer::processProbeTLBEvent(), BaseCPU::processProfileEvent(), DRAMCtrl::Rank::processRefreshEvent(), DRAMCtrl::processRespondEvent(), Shader::processTick(), EtherLink::Link::processTxQueue(), DRAMCtrl::Rank::processWakeUpEvent(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkAArch64(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), MSHR::promoteDeferredTargets(), MemChecker::ByteTracker::pruneTransactions(), EtherSwitch::Interface::PortFifo::push(), ClockedObject::pwrState(), ClockedObject::pwrStateWeights(), pybind_init_core(), QoS::MemCtrl::qosSchedule(), PseudoInst::quiesceNs(), PL031::read(), Sp804::Timer::read(), A9GlobalTimer::Timer::read(), CpuLocalTimer::Timer::read(), RealViewCtrl::read(), LSQUnit< Impl >::read(), UFSHostDevice::readCallback(), DRAMSim2::readComplete(), Pl111::readFramebuffer(), CheckerCPU::readMem(), X86ISA::Interrupts::readReg(), ArmSemihosting::readString(), ElasticTrace::recordExecTick(), Sequencer::recordMissLatency(), GPUCoalescer::recordMissLatency(), ElasticTrace::recordToCommTick(), BaseCache::recvAtomic(), TLBCoalescer::MemSidePort::recvReqRetry(), StubSlavePort::recvTimingReq(), SimpleTimingPort::recvTimingReq(), RubyPort::MemSlavePort::recvTimingReq(), MemDelay::SlavePort::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), SimpleMemory::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CommMonitor::recvTimingReq(), DRAMCtrl::recvTimingReq(), RubyPort::MemMasterPort::recvTimingResp(), MemDelay::MasterPort::recvTimingResp(), BaseTrafficGen::recvTimingResp(), RubyPort::PioMasterPort::recvTimingResp(), NoncoherentXBar::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), CoherentXBar::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), BaseCache::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), MemDelay::SlavePort::recvTimingSnoopResp(), CoherentXBar::recvTimingSnoopResp(), ElasticTrace::regEtraceListeners(), ElasticTrace::regProbeListeners(), Request::Request(), UFSHostDevice::requestHandler(), BankedArray::reserve(), BIPRP::reset(), WeightedLRUPolicy::reset(), LRURP::reset(), FIFORP::reset(), MRURP::reset(), Stats::AvgStor::reset(), Clocked::resetClock(), PseudoInst::resetstats(), DRAMCtrl::Rank::resetStats(), DRAMCtrl::DRAMStats::resetStats(), Sp804::Timer::restartCounter(), Sp805::restartCounter(), A9GlobalTimer::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), MipsISA::restoreThread(), Stats::AvgStor::result(), BasePixelPump::PixelEvent::resume(), DistIface::RecvScheduler::resumeRecvTicks(), SMMUTranslationProcess::resumeTransaction(), PL031::resyncMatch(), EtherTapBase::retransmit(), BaseTrafficGen::retryReq(), PseudoInst::rpns(), StatTest::run(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), Sinic::Device::rxKick(), NSGigE::rxKick(), CommMonitor::samplePeriodic(), TraceCPU::schedIcacheNext(), schedRelBreak(), PacketQueue::schedSendEvent(), PacketQueue::schedSendTiming(), GpuDispatcher::scheduleDispatch(), MC146818::RTCEvent::scheduleIntr(), Uart8250::scheduleIntr(), DRAMCtrl::Rank::schedulePowerEvent(), InstructionQueue< Impl >::scheduleReadyInsts(), BaseTrafficGen::scheduleUpdate(), DRAMCtrl::Rank::scheduleWakeUpEvent(), ArmSemihosting::semiExit(), EtherBus::send(), X86ISA::IntMasterPort< X86ISA::I82094AA >::sendMessage(), ComputeUnit::sendRequest(), DRAMSim2::sendResponse(), EtherTapBase::sendSimulated(), ComputeUnit::sendSyncRequest(), Globals::serialize(), MC146818::serialize(), Intel8254Timer::Counter::serialize(), Sinic::Device::serialize(), NSGigE::serialize(), Stats::AvgStor::set(), Request::setAccessLatency(), CheckpointIn::setDir(), SystemCounter::setFreq(), Pl011::setInterrupts(), CacheMemory::setMRU(), X86ISA::Interrupts::setReg(), Intel8254Timer::Counter::CounterEvent::setTo(), Request::setTranslateLatency(), Request::setVirt(), Event::setWhen(), simulate(), SMMUTranslationProcess::smmuTranslation(), DefaultRename< Impl >::sortInsts(), DistIface::SyncEvent::start(), IdeDisk::startDma(), sc_gem5::Kernel::startup(), CommMonitor::startup(), BaseKvmCPU::startup(), RubySystem::startup(), MC146818::startup(), ThermalModel::startup(), Intel8254Timer::Counter::startup(), DRAMSim2::startup(), BaseCPU::startup(), DRAMCtrl::Rank::startup(), DRAMCtrl::startup(), Stats::statElapsedTicks(), Stats::statFinalTick(), StoreTrace::store(), O3ThreadContext< Impl >::suspend(), SimpleThread::suspend(), BasePixelPump::PixelEvent::suspend(), AlphaISA::Kernel::Statistics::swpipl(), takeCheckpoint(), BaseCPU::takeOverFrom(), CacheMemory::testCacheAccess(), GarnetSyntheticTraffic::tick(), AtomicSimpleCPU::tick(), IGbE::tick(), DRAMSim2::tick(), BaseKvmCPU::tick(), timesFunc(), Root::timeSync(), Root::timeSyncEnable(), WeightedLRUPolicy::touch(), LRURP::touch(), MRURP::touch(), BaseCPU::traceFunctionsInternal(), Trace::InstPBTrace::traceInst(), BaseTrafficGen::transition(), QueuedPrefetcher::translationComplete(), X86ISA::GpuTLB::translationReturn(), EtherLink::Link::transmit(), DistEtherLink::TxLink::transmit(), EtherSwitch::Interface::transmit(), NSGigE::transmit(), BankedArray::tryAccess(), CacheMemory::tryCacheAccess(), SerialLink::SerialLinkSlavePort::trySendTiming(), Bridge::BridgeSlavePort::trySendTiming(), SerialLink::SerialLinkMasterPort::trySendTiming(), Bridge::BridgeMasterPort::trySendTiming(), EtherLink::Link::txDone(), Sinic::Device::txKick(), NSGigE::txKick(), Sinic::Device::unserialize(), NSGigE::unserialize(), Clocked::update(), BaseTrafficGen::update(), ElasticTrace::updateCommitOrderDep(), ArchTimer::updateCounter(), Stats::updateEvents(), DefaultIEW< Impl >::updateExeInstStats(), VGic::updateIntState(), GicV2::updateIntState(), ElasticTrace::updateIssueOrderDep(), X86ISA::GpuTLB::updatePageFootprint(), TLBCoalescer::updatePhysAddresses(), DRAMCtrl::Rank::updatePowerStats(), CommMonitor::MonitorStats::updateReqStats(), Checker< O3CPUImpl >::validateExecution(), Checker< O3CPUImpl >::validateInst(), Checker< O3CPUImpl >::validateState(), SystemCounter::value(), Checker< O3CPUImpl >::verify(), HDLcd::virtRefresh(), RubyDirectedTester::wakeup(), GPUCoalescer::wakeup(), RubyTester::wakeup(), ArmISA::TableWalker::walk(), System::workItemBegin(), System::workItemEnd(), Uart8250::write(), AlphaBackdoor::write(), PL031::write(), EnergyCtrl::write(), GpuDispatcher::write(), UFSHostDevice::write(), IGbE::DescCache< iGbReg::RxDesc >::writeback(), IGbE::DescCache< iGbReg::RxDesc >::writeback1(), LSQUnit< Impl >::writebackStores(), DRAMSim2::writeComplete(), MC146818::writeData(), UFSHostDevice::writeDevice(), CheckerCPU::writeMem(), and MipsISA::yieldThread().

doExitCleanup()

void doExitCleanup

(

)

Do C++ simulator exit processing.

Exported to Python to be invoked when simulator terminates via Python's atexit mechanism.

Definition at line 153 of file core.cc.

References CallbackQueue::clear(), exitCallbacks(), and CallbackQueue::process().

Referenced by pybind_init_core().

fixClockFrequency()

void fixClockFrequency

(

)

Definition at line 84 of file core.cc.

References cprintf(), SimClock::Frequency, SimClock::Float::GHz, SimClock::Float::Hz, SimClock::Float::kHz, SimClock::Float::MHz, SimClock::Int::ms, SimClock::Int::ns, SimClock::Int::ps, SimClock::Int::s, and SimClock::Int::us.

Referenced by sc_core::sc_time::from_value(), and pybind_init_core().

getClockFrequency()

Tick getClockFrequency

(

)

Definition at line 121 of file core.cc.

Referenced by pybind_init_core().

registerExitCallback()

void registerExitCallback

(

Callback *

callback

)

Register an exit callback.

Definition at line 143 of file core.cc.

setClockFrequency()

void setClockFrequency

(

Tick

ticksPerSecond

)

Definition at line 115 of file core.cc.

References panic_if.

Referenced by pybind_init_core(), and sc_core::sc_set_time_resolution().

setOutputDir()

void setOutputDir

(

const std::string &

dir

)

Variable Documentation

retryTime

const Tick retryTime = 1000

Definition at line 49 of file core.hh.

Referenced by EtherTapBase::retransmit(), EtherTapBase::sendSimulated(), EtherSwitch::Interface::transmit(), and NSGigE::transmit().