133 #include <sys/signal.h> 149 #include "blobs/gdb_xml_aarch64_core.hh" 150 #include "blobs/gdb_xml_aarch64_fpu.hh" 151 #include "blobs/gdb_xml_aarch64_target.hh" 152 #include "blobs/gdb_xml_arm_core.hh" 153 #include "blobs/gdb_xml_arm_target.hh" 154 #include "blobs/gdb_xml_arm_vfpv3.hh" 158 #include "debug/GDBAcc.hh" 159 #include "debug/GDBMisc.hh" 174 auto req = std::make_shared<Request>(
addr, 64, 0x40, -1, 0, 0);
190 :
BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this)
203 DPRINTF(GDBAcc,
"acc: %#x mapping is invalid\n", va);
208 DPRINTF(GDBAcc,
"acc: %#x mapping is valid\n", va);
220 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
222 for (
int i = 0;
i < 31; ++
i)
243 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
245 for (
int i = 0;
i < 31; ++
i)
247 auto pc_state = context->
pcState();
272 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
289 r.gpr[15] = context->
pcState().pc();
293 for (
int i = 0;
i < 32;
i++)
302 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
319 auto pc_state = context->
pcState();
320 pc_state.set(
r.gpr[15]);
332 #define GDB_XML(x, s) \ 333 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \ 335 static const std::map<std::string, std::string> annexMap32{
336 GDB_XML(
"target.xml", gdb_xml_arm_target),
337 GDB_XML(
"arm-core.xml", gdb_xml_arm_core),
338 GDB_XML(
"arm-vfpv3.xml", gdb_xml_arm_vfpv3),
340 static const std::map<std::string, std::string> annexMap64{
341 GDB_XML(
"target.xml", gdb_xml_aarch64_target),
342 GDB_XML(
"aarch64-core.xml", gdb_xml_aarch64_core),
343 GDB_XML(
"aarch64-fpu.xml", gdb_xml_aarch64_fpu),
347 auto it = annexMap.find(annex);
348 if (it == annexMap.end())
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
decltype(nullptr) constexpr NoFault
static void output(const char *filename)
virtual BaseTLB * getDTBPtr()=0
AArch32GdbRegCache regCache32
virtual TheISA::PCState pcState() const =0
virtual RegVal readIntReg(RegIndex reg_idx) const =0
AArch64GdbRegCache regCache64
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
BaseGdbRegCache * gdbRegs()
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
virtual Process * getProcessPtr()=0
Overload hash function for BasicBlockRange type.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual const VecRegContainer & readVecReg(const RegId ®) const =0
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
virtual BaseTLB * getITBPtr()=0
const int NumVecV8ArchRegs
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
ThreadContext * context()
EmulationPageTable * pTable
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
Declarations of a non-full system Page Table.
virtual VecRegContainer & getWritableVecReg(const RegId ®)=0
static bool tryTranslate(ThreadContext *tc, Addr addr)
bool acc(Addr addr, size_t len)
const Entry * lookup(Addr vaddr)
Lookup function.
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
Register ID: describe an architectural register with its class and index.
bool inAArch64(ThreadContext *tc)
Declaration and inline definition of ChunkGenerator object.
constexpr unsigned NumVecElemPerNeonVecReg
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)