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thread_context.hh
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41 
42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
44 
45 #include <iostream>
46 #include <string>
47 
48 #include "arch/generic/isa.hh"
49 #include "arch/registers.hh"
50 #include "arch/types.hh"
51 #include "base/types.hh"
52 #include "config/the_isa.hh"
53 #include "cpu/pc_event.hh"
54 #include "cpu/reg_class.hh"
55 
56 // @todo: Figure out a more architecture independent way to obtain the ITB and
57 // DTB pointers.
58 namespace TheISA
59 {
60  class ISA;
61  class Decoder;
62 }
63 class BaseCPU;
64 class BaseTLB;
65 class CheckerCPU;
66 class Checkpoint;
67 class EndQuiesceEvent;
68 class PortProxy;
69 class Process;
70 class System;
71 namespace Kernel {
72  class Statistics;
73 }
74 
91 class ThreadContext : public PCEventScope
92 {
93  protected:
94  typedef TheISA::MachInst MachInst;
95  using VecRegContainer = TheISA::VecRegContainer;
96  using VecElem = TheISA::VecElem;
97  using VecPredRegContainer = TheISA::VecPredRegContainer;
98 
99  public:
100 
101  enum Status
102  {
105  Active,
106 
109  Suspended,
110 
113  Halting,
114 
118  Halted
119  };
120 
121  virtual ~ThreadContext() { };
122 
123  virtual BaseCPU *getCpuPtr() = 0;
124 
125  virtual int cpuId() const = 0;
126 
127  virtual uint32_t socketId() const = 0;
128 
129  virtual int threadId() const = 0;
130 
131  virtual void setThreadId(int id) = 0;
132 
133  virtual ContextID contextId() const = 0;
134 
135  virtual void setContextId(ContextID id) = 0;
136 
137  virtual BaseTLB *getITBPtr() = 0;
138 
139  virtual BaseTLB *getDTBPtr() = 0;
140 
141  virtual CheckerCPU *getCheckerCpuPtr() = 0;
142 
143  virtual BaseISA *getIsaPtr() = 0;
144 
145  virtual TheISA::Decoder *getDecoderPtr() = 0;
146 
147  virtual System *getSystemPtr() = 0;
148 
149  virtual ::Kernel::Statistics *getKernelStats() = 0;
150 
151  virtual PortProxy &getPhysProxy() = 0;
152 
153  virtual PortProxy &getVirtProxy() = 0;
154 
161  virtual void initMemProxies(ThreadContext *tc) = 0;
162 
163  virtual Process *getProcessPtr() = 0;
164 
165  virtual void setProcessPtr(Process *p) = 0;
166 
167  virtual Status status() const = 0;
168 
169  virtual void setStatus(Status new_status) = 0;
170 
172  virtual void activate() = 0;
173 
175  virtual void suspend() = 0;
176 
178  virtual void halt() = 0;
179 
181  void quiesce();
182 
184  void quiesceTick(Tick resume);
185 
186  virtual void dumpFuncProfile() = 0;
187 
188  virtual void takeOverFrom(ThreadContext *old_context) = 0;
189 
190  virtual void regStats(const std::string &name) = 0;
191 
192  virtual EndQuiesceEvent *getQuiesceEvent() = 0;
193 
194  virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
195  virtual void descheduleInstCountEvent(Event *event) = 0;
196  virtual Tick getCurrentInstCount() = 0;
197 
198  // Not necessarily the best location for these...
199  // Having an extra function just to read these is obnoxious
200  virtual Tick readLastActivate() = 0;
201  virtual Tick readLastSuspend() = 0;
202 
203  virtual void profileClear() = 0;
204  virtual void profileSample() = 0;
205 
206  virtual void copyArchRegs(ThreadContext *tc) = 0;
207 
208  virtual void clearArchRegs() = 0;
209 
210  //
211  // New accessors for new decoder.
212  //
213  virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
214 
215  virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
216 
217  virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
218  virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
219 
223  virtual ConstVecLane8
224  readVec8BitLaneReg(const RegId& reg) const = 0;
225 
227  virtual ConstVecLane16
228  readVec16BitLaneReg(const RegId& reg) const = 0;
229 
231  virtual ConstVecLane32
232  readVec32BitLaneReg(const RegId& reg) const = 0;
233 
235  virtual ConstVecLane64
236  readVec64BitLaneReg(const RegId& reg) const = 0;
237 
239  virtual void setVecLane(const RegId& reg,
240  const LaneData<LaneSize::Byte>& val) = 0;
241  virtual void setVecLane(const RegId& reg,
242  const LaneData<LaneSize::TwoByte>& val) = 0;
243  virtual void setVecLane(const RegId& reg,
244  const LaneData<LaneSize::FourByte>& val) = 0;
245  virtual void setVecLane(const RegId& reg,
246  const LaneData<LaneSize::EightByte>& val) = 0;
249  virtual const VecElem& readVecElem(const RegId& reg) const = 0;
250 
251  virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
252  const = 0;
253  virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
254 
255  virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
256 
257  virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
258 
259  virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
260 
261  virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
262 
263  virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
264 
265  virtual void setVecPredReg(const RegId& reg,
266  const VecPredRegContainer& val) = 0;
267 
268  virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
269 
270  virtual TheISA::PCState pcState() const = 0;
271 
272  virtual void pcState(const TheISA::PCState &val) = 0;
273 
274  void
275  setNPC(Addr val)
276  {
277  TheISA::PCState pc_state = pcState();
278  pc_state.setNPC(val);
279  pcState(pc_state);
280  }
281 
282  virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
283 
284  virtual Addr instAddr() const = 0;
285 
286  virtual Addr nextInstAddr() const = 0;
287 
288  virtual MicroPC microPC() const = 0;
289 
290  virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
291 
292  virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
293 
294  virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
295 
296  virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
297 
298  virtual RegId flattenRegId(const RegId& regId) const = 0;
299 
300  // Also not necessarily the best location for these two. Hopefully will go
301  // away once we decide upon where st cond failures goes.
302  virtual unsigned readStCondFailures() const = 0;
303 
304  virtual void setStCondFailures(unsigned sc_failures) = 0;
305 
306  // Same with st cond failures.
307  virtual Counter readFuncExeInst() const = 0;
308 
309  virtual void syscall(Fault *fault) = 0;
310 
311  // This function exits the thread context in the CPU and returns
312  // 1 if the CPU has no more active threads (meaning it's OK to exit);
313  // Used in syscall-emulation mode when a thread calls the exit syscall.
314  virtual int exit() { return 1; };
315 
317  static void compare(ThreadContext *one, ThreadContext *two);
318 
331  virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
332  virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
333 
334  virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
335  virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
336 
337  virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
338  virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
339  virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
340 
341  virtual const VecElem& readVecElemFlat(RegIndex idx,
342  const ElemIndex& elemIdx) const = 0;
343  virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
344  const VecElem& val) = 0;
345 
346  virtual const VecPredRegContainer &
347  readVecPredRegFlat(RegIndex idx) const = 0;
348  virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
349  virtual void setVecPredRegFlat(RegIndex idx,
350  const VecPredRegContainer& val) = 0;
351 
352  virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
353  virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
356 };
357 
368 void serialize(const ThreadContext &tc, CheckpointOut &cp);
369 void unserialize(ThreadContext &tc, CheckpointIn &cp);
370 
384 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
385 
386 #endif
X86ISA::count
count
Definition: misc.hh:703
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
GuestABI::readVecReg
struct IsAapcs64Hfa< E[N], typename std::enable_if< std::is_floating_point< E >::value &&N<=4 >::type > :public std::true_type{};template< typename T, typename Enabled=void >struct IsAapcs64Hva :public std::false_type {};template< typename E, size_t N >struct IsAapcs64Hva< E[N], typename std::enable_if< IsAapcs64ShortVector< E >::value &&N<=4 >::type > :public std::true_type{};template< typename T, typename Enabled=void >struct IsAapcs64Hxa :public std::false_type {};template< typename T >struct IsAapcs64Hxa< T, typename std::enable_if< IsAapcs64Hfa< T >::value||IsAapcs64Hva< T >::value >::type > :public std::true_type{};struct Aapcs64ArgumentBase{ template< typename T > static T loadFromStack(ThreadContext *tc, Aapcs64::State &state) { size_t align=std::max< size_t >(8, alignof(T));size_t size=roundUp(sizeof(T), 8);state.nsaa=roundUp(state.nsaa, align);TypedBufferArg< T > val(state.nsaa);val.copyIn(tc->getVirtProxy());state.nsaa+=size;return gtoh(*val, ArmISA::byteOrder(tc));}};template< typename Float >struct Argument< Aapcs64, Float, typename std::enable_if< std::is_floating_point< Float >::value||IsAapcs64ShortVector< Float >::value >::type > :public Aapcs64ArgumentBase{ static Float get(ThreadContext *tc, Aapcs64::State &state) { if(state.nsrn<=state.MAX_SRN) { RegId id(VecRegClass, state.nsrn++);return tc->readVecReg(id).laneView< Float, 0 >();} return loadFromStack< Float >(tc, state);}};template< typename Float >struct Result< Aapcs64, Float, typename std::enable_if< std::is_floating_point< Float >::value||IsAapcs64ShortVector< Float >::value >::type >{ static void store(ThreadContext *tc, const Float &f) { RegId id(VecRegClass, 0);auto reg=tc-> readVecReg(id)
Definition: aapcs64.hh:204
GuestABI::setVecReg
tc setVecReg(id, reg)
ThreadContext::VecElem
TheISA::VecElem VecElem
Definition: thread_context.hh:96
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
name
const std::string & name()
Definition: trace.cc:50
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
ThreadContext::Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:113
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC...
Definition: vec_reg.hh:156
serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:158
ArmISA::getDTBPtr
TLB * getDTBPtr(T *tc)
Definition: tlb.hh:473
RegVal
uint64_t RegVal
Definition: types.hh:166
System
Definition: system.hh:72
cp
Definition: cprintf.cc:40
ArmISA::VecElem
uint32_t VecElem
Definition: registers.hh:68
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition: thread_context.hh:91
EndQuiesceEvent
Event for timing out quiesce instruction.
Definition: quiesce_event.hh:37
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:199
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
BaseTLB
Definition: tlb.hh:50
LaneData
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
Definition: vec_reg.hh:458
PseudoInst::quiesce
void quiesce(ThreadContext *tc)
Definition: pseudo_inst.cc:124
RegIndex
uint16_t RegIndex
Definition: types.hh:40
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:61
ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: registers.hh:77
MicroPC
uint16_t MicroPC
Definition: types.hh:142
ThreadContext::setNPC
void setNPC(Addr val)
Definition: thread_context.hh:275
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:56
MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:297
takeOverFrom
void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:242
Ps2::one
Bitfield< 3 > one
Definition: types.hh:110
PortProxy
This object is a proxy for a port or other object which implements the functional response protocol...
Definition: port_proxy.hh:80
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
ArmISA::VecRegContainer
VecReg::Container VecRegContainer
Definition: registers.hh:71
ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:43
Event
Definition: eventq.hh:246
ArmISA::readVecElem
XReg readVecElem(VReg src, int index, int eSize)
Read a single NEON vector element.
Definition: neon64_mem.hh:91
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
reg_class.hh
HsailISA::compare
bool compare(T src0, T src1, Brig::BrigCompareOperation cmpOp)
Definition: decl.hh:592
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
ThreadContext::exit
virtual int exit()
Definition: thread_context.hh:314
ThreadContext::Suspended
Temporarily inactive.
Definition: thread_context.hh:109
BaseISA
Definition: isa.hh:47
VecLaneT
Vector Lane abstraction Another view of a container.
Definition: vec_reg.hh:262
ThreadContext::MachInst
TheISA::MachInst MachInst
Definition: thread_context.hh:94
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:238
ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.hh:121
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:229
ArmISA::getITBPtr
TLB * getITBPtr(T *tc)
Definition: tlb.hh:464
MipsISA::halt
Bitfield< 26 > halt
Definition: dt_constants.hh:44
pc_event.hh
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