55 using namespace Linux;
59 _haveSecurity(p->have_security),
60 _haveLPAE(p->have_lpae),
61 _haveVirtualization(p->have_virtualization),
62 _haveCrypto(p->have_crypto),
63 _genericTimer(nullptr),
66 _highestELIs64(p->highest_el_is_64),
67 _physAddrRange64(p->phys_addr_range_64),
68 _haveLargeAsid64(p->have_large_asid_64),
69 _haveSVE(p->have_sve),
71 _haveLSE(p->have_lse),
72 _havePAN(p->have_pan),
73 semihosting(p->semihosting),
74 multiProc(p->multi_proc)
76 if (p->auto_reset_addr) {
81 "Workload entry point %#x and reset address %#x are different",
87 warn(
"Highest ARM exception-level set to AArch%d but the workload " 88 "is for AArch%d. Assuming you wanted these to match.",
143 warn(
"Unimplemented Exception Level\n");
203 pwr_ctrl->setStandByWfi(tc);
210 pwr_ctrl->clearStandByWfi(tc);
217 return pwr_ctrl->setWakeRequest(tc);
226 pwr_ctrl->clearWakeRequest(tc);
230 ArmSystemParams::create()
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
#define fatal(...)
This implements a cprintf based fatal() function.
Addr physAddrMask() const
Returns the physical address mask.
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
bool call64(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch64 code.
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8) ...
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Overload hash function for BasicBlockRange type.
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
static bool haveEL(ThreadContext *tc, ExceptionLevel el)
Return true if the system implements a specific exception level.
bool call32(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch32 code.
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8) ...
virtual Loader::Arch getArch() const =0
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Workload * workload
OS kernel.
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system's power controller.
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
virtual Addr getEntry() const =0
This class implements the base power controller for FVP-based platforms.
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
ExceptionLevel highestEL() const
Returns the highest implemented exception level.
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Implementation of a GICv2.
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
bool inAArch64(ThreadContext *tc)
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Addr _resetAddr
Reset address (ARMv8)
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8) ...
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.