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cpu
intr_control.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2002-2005 The Regents of The University of Michigan
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
#include "
cpu/intr_control.hh
"
30
31
#include <string>
32
#include <vector>
33
34
#include "
base/trace.hh
"
35
#include "
cpu/base.hh
"
36
#include "
cpu/thread_context.hh
"
37
#include "debug/IntrControl.hh"
38
#include "
sim/sim_object.hh
"
39
40
using namespace
std
;
41
42
IntrControl::IntrControl
(
const
Params
*
p
)
43
:
SimObject
(p), sys(p->sys)
44
{}
45
46
void
47
IntrControl::post
(
int
cpu_id,
int
int_num,
int
index
)
48
{
49
DPRINTF
(
IntrControl
,
"post %d:%d (cpu %d)\n"
, int_num, index, cpu_id);
50
ThreadContext
*tc =
sys
->
getThreadContext
(cpu_id);
51
tc->
getCpuPtr
()->
postInterrupt
(tc->
threadId
(), int_num,
index
);
52
}
53
54
void
55
IntrControl::clear
(
int
cpu_id,
int
int_num,
int
index
)
56
{
57
DPRINTF
(
IntrControl
,
"clear %d:%d (cpu %d)\n"
, int_num, index, cpu_id);
58
ThreadContext
*tc =
sys
->
getThreadContext
(cpu_id);
59
tc->
getCpuPtr
()->
clearInterrupt
(tc->
threadId
(), int_num,
index
);
60
}
61
62
void
63
IntrControl::clearAll
(
int
cpu_id)
64
{
65
DPRINTF
(
IntrControl
,
"Clear all pending interrupts for CPU %d\n"
, cpu_id);
66
ThreadContext
*tc =
sys
->
getThreadContext
(cpu_id);
67
tc->
getCpuPtr
()->
clearInterrupts
(tc->
threadId
());
68
}
69
70
bool
71
IntrControl::havePosted
(
int
cpu_id)
const
72
{
73
DPRINTF
(
IntrControl
,
"Check pending interrupts for CPU %d\n"
, cpu_id);
74
ThreadContext
*tc =
sys
->
getThreadContext
(cpu_id);
75
return
tc->
getCpuPtr
()->
checkInterrupts
(tc);
76
}
77
78
IntrControl
*
79
IntrControlParams::create()
80
{
81
return
new
IntrControl
(
this
);
82
}
DPRINTF
#define DPRINTF(x,...)
Definition:
trace.hh:222
IntrControl::havePosted
bool havePosted(int cpu_id) const
Definition:
intr_control.cc:71
MipsISA::index
Bitfield< 30, 0 > index
Definition:
pra_constants.hh:44
IntrControl::Params
IntrControlParams Params
Definition:
intr_control.hh:43
IntrControl::post
void post(int cpu_id, int int_num, int index)
Definition:
intr_control.cc:47
base.hh
BaseCPU::clearInterrupt
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition:
base.hh:242
std
Overload hash function for BasicBlockRange type.
Definition:
vec_reg.hh:587
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
BaseCPU::clearInterrupts
void clearInterrupts(ThreadID tid)
Definition:
base.hh:248
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:91
trace.hh
IntrControl::clearAll
void clearAll(int cpu_id)
Definition:
intr_control.cc:63
System::getThreadContext
ThreadContext * getThreadContext(ContextID tid) const
Definition:
system.hh:186
IntrControl::IntrControl
IntrControl(const Params *p)
Definition:
intr_control.cc:42
BaseCPU::checkInterrupts
bool checkInterrupts(ThreadContext *tc) const
Definition:
base.hh:254
thread_context.hh
ThreadContext::threadId
virtual int threadId() const =0
sim_object.hh
IntrControl::sys
System * sys
Definition:
intr_control.hh:42
intr_control.hh
IntrControl::clear
void clear(int cpu_id, int int_num, int index)
Definition:
intr_control.cc:55
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition:
base.hh:234
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:92
IntrControl
Definition:
intr_control.hh:39
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