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arch
power
interrupts.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2011 Google
3
* All rights reserved.
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*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
#ifndef __ARCH_POWER_INTERRUPT_HH__
30
#define __ARCH_POWER_INTERRUPT_HH__
31
32
#include "
arch/generic/interrupts.hh
"
33
#include "
base/logging.hh
"
34
#include "params/PowerInterrupts.hh"
35
36
class
BaseCPU
;
37
class
ThreadContext
;
38
39
namespace
PowerISA
{
40
41
class
Interrupts
:
public
BaseInterrupts
42
{
43
private
:
44
BaseCPU
*
cpu
;
45
46
public
:
47
typedef
PowerInterruptsParams
Params
;
48
49
const
Params *
50
params
()
const
51
{
52
return
dynamic_cast<
const
Params *
>
(
_params
);
53
}
54
55
Interrupts
(Params *
p
) :
BaseInterrupts
(p), cpu(NULL)
56
{}
57
58
void
59
setCPU
(
BaseCPU
* _cpu)
60
{
61
cpu = _cpu;
62
}
63
64
void
65
post
(
int
int_num,
int
index
)
66
{
67
panic
(
"Interrupts::post not implemented.\n"
);
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}
69
70
void
71
clear
(
int
int_num,
int
index
)
72
{
73
panic
(
"Interrupts::clear not implemented.\n"
);
74
}
75
76
void
77
clearAll
()
78
{
79
panic
(
"Interrupts::clearAll not implemented.\n"
);
80
}
81
82
bool
83
checkInterrupts
(
ThreadContext
*tc)
const
84
{
85
panic
(
"Interrupts::checkInterrupts not implemented.\n"
);
86
}
87
88
Fault
89
getInterrupt
(
ThreadContext
*tc)
90
{
91
assert(
checkInterrupts
(tc));
92
panic
(
"Interrupts::getInterrupt not implemented.\n"
);
93
}
94
95
void
96
updateIntrInfo
(
ThreadContext
*tc)
97
{
98
panic
(
"Interrupts::updateIntrInfo not implemented.\n"
);
99
}
100
};
101
102
}
// namespace PowerISA
103
104
#endif // __ARCH_POWER_INTERRUPT_HH__
105
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition:
logging.hh:163
logging.hh
interrupts.hh
MipsISA::index
Bitfield< 30, 0 > index
Definition:
pra_constants.hh:44
PowerISA::Interrupts::clear
void clear(int int_num, int index)
Definition:
interrupts.hh:71
PowerISA::Interrupts::clearAll
void clearAll()
Definition:
interrupts.hh:77
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:91
PowerISA::Interrupts
Definition:
interrupts.hh:41
BaseInterrupts
Definition:
interrupts.hh:37
PowerISA::Interrupts::getInterrupt
Fault getInterrupt(ThreadContext *tc)
Definition:
interrupts.hh:89
PowerISA::Interrupts::checkInterrupts
bool checkInterrupts(ThreadContext *tc) const
Definition:
interrupts.hh:83
PowerISA::Interrupts::Params
PowerInterruptsParams Params
Definition:
interrupts.hh:47
PowerISA
Definition:
decoder.cc:31
PowerISA::Interrupts::updateIntrInfo
void updateIntrInfo(ThreadContext *tc)
Definition:
interrupts.hh:96
PowerISA::Interrupts::setCPU
void setCPU(BaseCPU *_cpu)
Definition:
interrupts.hh:59
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition:
sim_object.hh:110
PowerISA::Interrupts::cpu
BaseCPU * cpu
Definition:
interrupts.hh:44
PowerISA::Interrupts::post
void post(int int_num, int index)
Definition:
interrupts.hh:65
BaseCPU
Definition:
cpu_dummy.hh:43
PowerISA::Interrupts::Interrupts
Interrupts(Params *p)
Definition:
interrupts.hh:55
PowerISA::Interrupts::params
const Params * params() const
Definition:
interrupts.hh:50
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:238
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