29 #ifndef __ARCH_X86_DECODER_HH__ 30 #define __ARCH_X86_DECODER_HH__ 33 #include <unordered_map> 44 #include "debug/Decoder.hh" 106 return ((uint8_t *)&fetchChunk)[
offset];
113 int toGet = size - collected;
115 int remaining =
sizeof(
MachInst) - offset;
117 toGet = toGet > remaining ? remaining : toGet;
120 uint64_t partialImm = fetchChunk >> (offset * 8);
122 partialImm &=
mask(toGet * 8);
126 current |= partialImm;
136 DPRINTF(
Decoder,
"At the end of a chunk, idx = %d, chunks = %d.\n",
137 chunkIdx, instBytes->
chunks.size());
139 if (chunkIdx == instBytes->
chunks.size()) {
216 bool addrSizedImm =
false);
231 typedef std::unordered_map<
236 Decoder(
ISA* isa =
nullptr) : basePC(0), origPC(0), offset(0),
237 outOfBytes(true), instDone(false),
257 mode = (X86Mode)(uint64_t)m5Reg.mode;
258 submode = (
X86SubMode)(uint64_t)m5Reg.submode;
263 altAddr = m5Reg.altAddr;
264 defAddr = m5Reg.defAddr;
267 AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg);
268 if (amIter != addrCacheMap.end()) {
269 decodePages = amIter->second;
275 InstCacheMap::iterator imIter = instCacheMap.find(m5Reg);
276 if (imIter != instCacheMap.end()) {
277 instMap = imIter->second;
311 fetchChunk =
letoh(data);
329 if (!nextPC.
size()) {
330 int size = basePC + offset -
origPC;
332 "Calculating the instruction size: " 333 "basePC: %#x offset: %#x origPC: %#x size: %d\n",
334 basePC, offset, origPC, size);
336 nextPC.
npc(nextPC.
pc() + size);
352 #endif // __ARCH_X86_DECODER_HH__
static ByteTable UsesModRMThreeByte0F38
RegVal CacheKey
Caching for decoded instruction objects.
State doVex3Of3State(uint8_t)
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
State doVex2Of3State(uint8_t)
static ByteTable Prefixes
void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
State doTwoByteOpcodeState(uint8_t)
static ByteTable ImmediateTypeVex[10]
static const uint8_t SizeTypeToSize[3][10]
std::unordered_map< CacheKey, DecodePages * > AddrCacheMap
State doPrefixState(uint8_t)
StaticInstPtr decodeInst(ExtMachInst mach_inst)
State doSIBState(uint8_t)
static ByteTable ImmediateTypeThreeByte0F3A
static ByteTable UsesModRMOneByte
DecodePages * decodePages
static ByteTable UsesModRMTwoByte
static InstCacheMap instCacheMap
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
void consumeBytes(int numBytes)
State doVexOpcodeState(uint8_t)
void setM5Reg(HandyM5Reg m5Reg)
static ByteTable ImmediateTypeTwoByte
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
AddrCacheMap addrCacheMap
static ByteTable ImmediateTypeOneByte
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
A sparse map from an Addr to a Value, stored in page chunks.
DecodeCache::AddrMap< Decoder::InstBytes > DecodePages
State doVex2Of2State(uint8_t)
State doModRMState(uint8_t)
Decoder(ISA *isa=nullptr)
std::vector< MachInst > masks
This is exposed globally, independent of the ISA.
DecodeCache::InstMap< ExtMachInst > * instMap
State doDisplacementState()
State doOneByteOpcodeState(uint8_t)
State doThreeByte0F38OpcodeState(uint8_t)
const uint8_t ByteTable[256]
static ByteTable ImmediateTypeThreeByte0F38
void takeOverFrom(Decoder *old)
std::unordered_map< EMI, StaticInstPtr > InstMap
Hash for decoded instructions.
void updateNPC(X86ISA::PCState &nextPC)
std::vector< MachInst > chunks
State doThreeByte0F3AOpcodeState(uint8_t)
State processExtendedOpcode(ByteTable &immTable)
std::unordered_map< CacheKey, DecodeCache::InstMap< ExtMachInst > * > InstCacheMap
static ByteTable UsesModRMThreeByte0F3A
void getImmediate(int &collected, uint64_t ¤t, int size)