#include "arch/arm/ccregs.hh"
#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"

Namespaces
	ArmISA

Typedefs
using	ArmISA::VecElem = uint32_t

using	ArmISA::VecReg = ::VecRegT< VecElem, NumVecElemPerVecReg, false >

using	ArmISA::ConstVecReg = ::VecRegT< VecElem, NumVecElemPerVecReg, true >

using	ArmISA::VecRegContainer = VecReg::Container

using	ArmISA::VecPredReg = ::VecPredRegT< VecElem, NumVecElemPerVecReg, VecPredRegHasPackedRepr, false >

using	ArmISA::ConstVecPredReg = ::VecPredRegT< VecElem, NumVecElemPerVecReg, VecPredRegHasPackedRepr, true >

using	ArmISA::VecPredRegContainer = VecPredReg::Container

Variables
const int	ArmISA::MaxInstSrcRegs

constexpr unsigned	ArmISA::NumVecElemPerNeonVecReg = 4

constexpr unsigned	ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords

const int	ArmISA::NumIntArchRegs = NUM_ARCH_INTREGS

const int	ArmISA::NumIntRegs = NUM_INTREGS

const int	ArmISA::NumFloatRegs = 0

const int	ArmISA::NumCCRegs = NUM_CCREGS

const int	ArmISA::NumMiscRegs = NUM_MISCREGS

const int	ArmISA::NumFloatV7ArchRegs = 64

const int	ArmISA::NumVecV7ArchRegs = 16

const int	ArmISA::NumVecV8ArchRegs = 32

const int	ArmISA::NumVecSpecialRegs = 8

const int	ArmISA::NumVecIntrlvRegs = 4

const int	ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs

const int	ArmISA::NumVecPredRegs = 18

const int	ArmISA::TotalNumRegs

const int	ArmISA::ReturnValueReg = 0

const int	ArmISA::ReturnValueReg1 = 1

const int	ArmISA::ReturnValueReg2 = 2

const int	ArmISA::NumArgumentRegs = 4

const int	ArmISA::NumArgumentRegs64 = 8

const int	ArmISA::ArgumentReg0 = 0

const int	ArmISA::ArgumentReg1 = 1

const int	ArmISA::ArgumentReg2 = 2

const int	ArmISA::ArgumentReg3 = 3

const int	ArmISA::FramePointerReg = 11

const int	ArmISA::StackPointerReg = INTREG_SP

const int	ArmISA::ReturnAddressReg = INTREG_LR

const int	ArmISA::PCReg = INTREG_PC

const int	ArmISA::ZeroReg = INTREG_ZERO

const int	ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg

const int	ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs

const int	ArmISA::INTRLVREG1 = INTRLVREG0 + 1

const int	ArmISA::INTRLVREG2 = INTRLVREG0 + 2

const int	ArmISA::INTRLVREG3 = INTRLVREG0 + 3

const int	ArmISA::VECREG_UREG0 = 32

const int	ArmISA::PREDREG_FFR = 16

const int	ArmISA::PREDREG_UREG0 = 17

const int	ArmISA::SyscallNumReg = ReturnValueReg

const int	ArmISA::SyscallPseudoReturnReg = ReturnValueReg

const int	ArmISA::SyscallSuccessReg = ReturnValueReg

Namespaces

Typedefs

Variables