- b -

• b2nb_thread() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• b_not() : sc_dt::sc_bit , sc_dt::sc_bitref< X > , sc_dt::sc_logic , sc_dt::sc_proxy< X >
• b_transport() : MultiSocketSimpleSwitchAT , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , tlm::tlm_blocking_transport_if< TRANS > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• back() : CircularQueue< T >
• back_cast() : sc_dt::sc_proxy< X >
• backdoor() : MemBackdoor::Callback
• BackingStoreEntry() : BackingStoreEntry
• backward_nb_transport() : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• BadDevice() : BadDevice
• Bank() : DRAMCtrl::Bank
• banked() : ArmISA::ISA::MiscRegLUTEntryInitializer
• banked64() : ArmISA::ISA::MiscRegLUTEntryInitializer
• BankedArray() : BankedArray
• bankedChild() : ArmISA::ISA::MiscRegLUTEntryInitializer
• BankedRegs() : GicV2::BankedRegs
• BareMetal() : RiscvISA::BareMetal
• Barrier() : Barrier , HsailISA::Barrier
• BarrierDataRequest() : Minor::LSQ::BarrierDataRequest
• BarrierEvent() : BaseGlobalEvent::BarrierEvent , GlobalEvent::BarrierEvent , GlobalSyncEvent::BarrierEvent
• Base() : BloomFilter::Base
• base() : MipsISA::MipsFaultBase
• Base() : Prefetcher::Base , Sinic::Base
• Base16Delta8() : Base16Delta8
• Base32Delta16() : Base32Delta16
• Base32Delta8() : Base32Delta8
• Base64Delta16() : Base64Delta16
• Base64Delta32() : Base64Delta32
• Base64Delta8() : Base64Delta8
• base_event() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_read() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_value_changed_event() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_write() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• BaseArmKvmCPU() : BaseArmKvmCPU
• BaseBufferArg() : BaseBufferArg
• BaseCache() : BaseCache
• BaseCacheCompressor() : BaseCacheCompressor
• BaseCacheCompressorStats() : BaseCacheCompressor::BaseCacheCompressorStats
• baseCheck() : Stats::Info
• BaseConfigEntry() : X86ISA::IntelMP::BaseConfigEntry
• BaseCPU() : BaseCPU , Iris::BaseCPU
• BaseDelta() : BaseDelta< BaseType, DeltaSizeBits >
• BaseDictionaryCompressor() : BaseDictionaryCompressor
• BaseDynInst() : BaseDynInst< Impl >
• BaseGdbRegCache() : BaseGdbRegCache
• BaseGen() : BaseGen
• BaseGic() : BaseGic
• BaseGlobalEvent() : BaseGlobalEvent
• BaseGlobalEventTemplate() : BaseGlobalEventTemplate< Derived >
• BaseIndexingPolicy() : BaseIndexingPolicy
• BaseInterrupts() : BaseInterrupts
• BaseISADevice() : ArmISA::BaseISADevice
• BaseKvmCPU() : BaseKvmCPU
• BaseKvmTimer() : BaseKvmTimer
• BaseMemProbe() : BaseMemProbe
• basename() : sc_core::sc_event , sc_core::sc_object , sc_gem5::Event , sc_gem5::Object
• BaseO3CPU() : BaseO3CPU
• BaseO3DynInst() : BaseO3DynInst< Impl >
• BaseOperand() : BaseOperand
• BasePixelPump() : BasePixelPump
• basePtr() : MultiLevelPageTable< EntryTypes >
• BaseRemoteGDB() : BaseRemoteGDB
• BaseReplacementPolicy() : BaseReplacementPolicy
• BaseSetAssoc() : BaseSetAssoc
• BaseSimpleCPU() : BaseSimpleCPU
• BaseTags() : BaseTags
• BaseTagsCallback() : BaseTagsCallback
• BaseTagStats() : BaseTags::BaseTagStats
• BaseTLB() : BaseTLB
• BaseTrafficGen() : BaseTrafficGen
• baseUpdate() : TAGEBase
• BaseXBar() : BaseXBar
• BasicBlock() : BasicBlock
• basicBlock() : ControlFlowInfo
• BasicExtLink() : BasicExtLink
• BasicIntLink() : BasicIntLink
• BasicLink() : BasicLink
• BasicPioDevice() : BasicPioDevice
• BasicRouter() : BasicRouter
• BasicSignal() : BasicSignal
• before_end_of_elaboration() : FastModel::SCGIC , FastModel::ScxEvsCortexA76< Types > , sc_core::sc_clock , sc_core::sc_export< IF > , sc_core::sc_export_base , sc_core::sc_module , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_prim_channel , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , sc_gem5::TlmToGem5Bridge< BITWIDTH > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• beforeEndOfElaboration() : sc_gem5::Module
• begin() : AddrRangeMap< V, max_cache_size > , AssociativeSet< Entry > , CircularQueue< T > , PacketFifo , sc_core::sc_attr_cltn , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , sc_dt::sc_context< T > , SimpleRenameMap , SparcISA::TlbMap , Stats::Hdf5 , Stats::Output , Stats::Text
• beginGroup() : Stats::Hdf5 , Stats::Output , Stats::Text
• beginLine() : BasePixelPump
• beginResponse() : ExplicitATTarget , SimpleATTarget1 , SimpleATTarget2
• beginTransaction() : SMMUTranslationProcess
• bestOffsetLearning() : Prefetcher::BOP
• bi() : sc_dt::scfx_index
• bias() : Loader::ElfObject , Loader::ObjectFile
• BIAS() : MultiperspectivePerceptron::BIAS
• BigFpMemImmOp() : ArmISA::BigFpMemImmOp
• BigFpMemLitOp() : ArmISA::BigFpMemLitOp
• BigFpMemPostOp() : ArmISA::BigFpMemPostOp
• BigFpMemPreOp() : ArmISA::BigFpMemPreOp
• BigFpMemRegOp() : ArmISA::BigFpMemRegOp
• BiModeBP() : BiModeBP
• BinaryNode() : Stats::BinaryNode< Op >
• binaryOp() : ArmISA::FpOp
• bind() : EtherInt , IntSinkPinBase , IntSourcePinBase , MasterPort , Port , RubyDummyPort , sc_core::sc_export< IF > , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , sc_gem5::Port , sc_gem5::ScExportWrapper< IF > , sc_gem5::ScInterfaceWrapper< IF > , sc_gem5::ScPortWrapper< IF > , sc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL > , sc_gem5::TlmTargetBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL > , SlavePort , tlm::tlm_analysis_port< T > , tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , TokenMasterPort , TokenSlavePort
• bind_exports() : tlm::tlm_req_rsp_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• bindAllPorts() : CxxConfigManager
• bindex() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• Binding() : sc_gem5::Port::Binding
• bindList() : Scheduler
• bindMasterPort() : CxxConfigManager
• bindObjectPorts() : CxxConfigManager
• bindPort() : CxxConfigManager
• bindPorts() : sc_gem5::Module
• bindTargetSocket() : MultiSocketSimpleSwitchAT
• bindWaveList() : FetchUnit
• BiosInformation() : X86ISA::SMBios::BiosInformation
• BIPRP() : BIPRP
• bit() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_int_base , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• BitfieldROType() : BitfieldROType< Base >
• BitfieldType() : BitfieldType< Base >
• BitfieldTypeImpl() : BitfieldTypeImpl< Base >
• BitfieldWOType() : BitfieldWOType< Base >
• bitIndex() : NetDest
• BitUnion16() : GenericTimerFrame
• BitUnion32() : A9GlobalTimer::Timer , ArchTimer , ArmISA::PMU , CpuLocalTimer::Timer , FVPBasePwrCtrl , GenericTimerMem , GicV2 , Gicv3CPUInterface , Gicv3Its , HDLcd , RealViewCtrl , Sp804::Timer , VGic , X86ISA::Interrupts , X86ISA::PageFault
• BitUnion64() : ContextDescriptor , Gicv3CPUInterface , Gicv3Distributor , Gicv3Its , SMMUCommand , StreamTableEntry , X86ISA::I82094AA
• BitUnion8() : GenericTimerFrame , Gicv3Redistributor , IdeController , Intel8254Timer , MC146818 , Pl050 , Pl111 , PS2Mouse , VirtIODeviceBase , X86ISA::I8042 , X86ISA::Speaker
• BitUnionOperators() : BitfieldBackend::BitUnionOperators< Base >
• blkAlign() : BaseTags
• Block() : Block , BloomFilter::Block
• block() : DefaultDecode< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• blockAddress() : Prefetcher::Base
• blockAlign() : MemTest
• blockIndex() : Prefetcher::Base
• BlockMem() : SparcISA::BlockMem
• BlockMemImmMicro() : SparcISA::BlockMemImmMicro
• blockMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• BlockMemMicro() : SparcISA::BlockMemMicro
• blockOnQueue() : AbstractController
• BLURRYPATH() : MultiperspectivePerceptron::BLURRYPATH
• BmpWriter() : BmpWriter
• BOP() : Prefetcher::BOP
• BoundRange() : X86ISA::BoundRange
• BpInfo() : Iris::ThreadContext::BpInfo
• bpr1() : Gicv3CPUInterface
• BPredUnit() : BPredUnit
• BranchCond() : PowerISA::BranchCond
• branchCount() : DefaultFetch< Impl >
• BranchData() : Minor::BranchData
• BranchDisp() : SparcISA::BranchDisp
• BranchEret64() : ArmISA::BranchEret64
• BranchEretA64() : ArmISA::BranchEretA64
• BranchImm() : ArmISA::BranchImm
• BranchImm13() : SparcISA::BranchImm13
• BranchImm64() : ArmISA::BranchImm64
• BranchImmCond() : ArmISA::BranchImmCond
• BranchImmCond64() : ArmISA::BranchImmCond64
• BranchImmImmReg64() : ArmISA::BranchImmImmReg64
• BranchImmReg() : ArmISA::BranchImmReg
• BranchImmReg64() : ArmISA::BranchImmReg64
• BranchInfo() : LoopPredictor::BranchInfo , MPP_TAGE::BranchInfo , StatisticalCorrector::BranchInfo , TAGE_SC_L_TAGE::BranchInfo , TAGEBase::BranchInfo
• branching() : GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , RiscvISA::PCState , X86ISA::PCState
• BranchNBits() : SparcISA::BranchNBits< bits >
• BranchNonPCRel() : PowerISA::BranchNonPCRel
• BranchNonPCRelCond() : PowerISA::BranchNonPCRelCond
• BranchPCRel() : PowerISA::BranchPCRel
• BranchPCRelCond() : PowerISA::BranchPCRelCond
• BranchReg() : ArmISA::BranchReg
• BranchReg64() : ArmISA::BranchReg64
• BranchRegCond() : ArmISA::BranchRegCond , PowerISA::BranchRegCond
• BranchRegReg() : ArmISA::BranchRegReg
• BranchRegReg64() : ArmISA::BranchRegReg64
• BranchRet64() : ArmISA::BranchRet64
• BranchRetA64() : ArmISA::BranchRetA64
• BranchSplit() : SparcISA::BranchSplit
• branchTarget() : ArmISA::BranchImm64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , BaseDynInst< Impl > , PowerISA::BranchNonPCRel , PowerISA::BranchNonPCRelCond , PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::BranchRegCond , StaticInst
• BrDirectInst() : HsailISA::BrDirectInst
• BreakPCEvent() : BreakPCEvent
• breakpoint() : BaseRemoteGDB , System
• Breakpoint() : X86ISA::Breakpoint
• BreakpointFault() : RiscvISA::BreakpointFault
• breakpointHit() : Iris::ThreadContext
• Bridge() : Bridge
• BridgeMasterPort() : Bridge::BridgeMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort
• BridgeSlavePort() : Bridge::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort
• BrigObject() : BrigObject
• BrigRegOperandInfo() : BrigRegOperandInfo
• BrIndirectInst() : HsailISA::BrIndirectInst
• BrInstBase() : HsailISA::BrInstBase< TargetType >
• BrnDirectInst() : HsailISA::BrnDirectInst
• BrnIndirectInst() : HsailISA::BrnIndirectInst
• BrnInstBase() : HsailISA::BrnInstBase< TargetType >
• broadcast() : ArmISA::DTLBIALL , ArmISA::DTLBIASID , ArmISA::DTLBIMVA , ArmISA::ITLBIALL , ArmISA::ITLBIASID , ArmISA::ITLBIMVA , ArmISA::TLBIOp , Net::EthAddr , NetDest , Set
• BRRIPReplData() : BRRIPRP::BRRIPReplData
• BRRIPRP() : BRRIPRP
• BTBEntry() : DefaultBTB::BTBEntry
• BTBLookup() : BPredUnit
• btbUpdate() : BiModeBP , BPredUnit
• BTBUpdate() : BPredUnit
• btbUpdate() : LocalBP , MultiperspectivePerceptron , TAGE , TAGEBase , TournamentBP
• BTBValid() : BPredUnit
• bubble() : Minor::BranchData , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• bubbleFill() : Minor::ForwardInstData
• buf_alloc() : tlm::circular_buffer< T >
• buf_clear() : tlm::circular_buffer< T >
• buf_free() : tlm::circular_buffer< T >
• buf_read() : tlm::circular_buffer< T >
• buf_write() : tlm::circular_buffer< T >
• BufferArg() : BufferArg
• bufferPtr() : BufferArg
• bufLen() : iGbReg::Regs::SRRCTL
• buildDispatcher() : ArmSemihosting::SemiCall
• buildDumper() : ArmSemihosting::SemiCall , SyscallDescABI< ABI >
• buildExecutor() : SyscallDescABI< ABI >
• buildImage() : Loader::DtbFile , Loader::ElfObject , Loader::ImageFile , Loader::RawImage
• buildInst() : DefaultFetch< Impl >
• buildPacket() : TimingSimpleCPU
• buildPackets() : LSQ< Impl >::LSQRequest , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest
• buildSplitPacket() : TimingSimpleCPU
• buildTageTables() : TAGE_SC_L_TAGE , TAGEBase
• Bulk() : BloomFilter::Bulk
• burstAlign() : DRAMCtrl
• BurstHelper() : DRAMCtrl::BurstHelper
• burstSize() : DRAMSim2Wrapper
• Bus() : X86ISA::IntelMP::Bus
• busAddr() : PciDevice
• BusHierarchy() : X86ISA::IntelMP::BusHierarchy
• busy() : DistEtherLink::Link , DMASequencer , EtherBus , EtherLink::Link , Shader
• bw_invalidate_direct_mem_ptr() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• bw_nb_transport() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• bw_process() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process
• bwPEQcb() : MultiSocketSimpleSwitchAT
• bypass() : SMMUTranslationProcess
• bypassCaches() : System
• bytes() : Net::EthAddr , Net::EthHdr , Net::Ip6Hdr , Net::IpHdr , Net::TcpHdr , Net::TcpOpt , Net::UdpHdr
• ByteTracker() : MemChecker::ByteTracker