- t -

• t0Handler() : sc_gem5::Kernel
• T1000() : T1000
• tableSize() : X86ISA::LongModePTE
• TableWalker() : ArmISA::TableWalker
• tadvProcess() : IGbE
• tag() : AtagCmdline , AtagCore , AtagHeader , AtagMem , AtagNone , AtagRev , AtagSerial , Prefetcher::BOP
• TAGE() : TAGE
• TAGE_SC_L() : TAGE_SC_L
• TAGE_SC_L_64KB() : TAGE_SC_L_64KB
• TAGE_SC_L_64KB_StatisticalCorrector() : TAGE_SC_L_64KB_StatisticalCorrector
• TAGE_SC_L_8KB() : TAGE_SC_L_8KB
• TAGE_SC_L_8KB_StatisticalCorrector() : TAGE_SC_L_8KB_StatisticalCorrector
• TAGE_SC_L_LoopPredictor() : TAGE_SC_L_LoopPredictor
• TAGE_SC_L_TAGE() : TAGE_SC_L_TAGE
• TAGE_SC_L_TAGE_64KB() : TAGE_SC_L_TAGE_64KB
• TAGE_SC_L_TAGE_8KB() : TAGE_SC_L_TAGE_8KB
• TAGEBase() : TAGEBase
• TageBranchInfo() : TAGE::TageBranchInfo
• TageEntry() : TAGEBase::TageEntry
• tagePredict() : TAGEBase
• TageSCLBranchInfo() : TAGE_SC_L::TageSCLBranchInfo
• Tagged() : Prefetcher::Tagged
• TaggedEntry() : TaggedEntry
• TagRead() : SparcISA::TLB
• tagsInit() : BaseSetAssoc , BaseTags , CompressedTags , FALRU , SectorTags
• tail() : CircularQueue< T >
• takeInt() : ArmISA::Interrupts
• takeInterrupt() : Minor::Execute
• takeOverFrom() : ArmISA::Decoder , ArmISA::ISA , ArmISA::TLB , AtomicSimpleCPU , BaseCPU , BaseISA , BaseKvmCPU , BaseTLB , Checker< Impl > , CheckerThreadContext< TC > , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , FUPool , InstructionQueue< Impl > , Iris::ThreadContext , Iris::TLB , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , MinorCPU , MipsISA::Decoder , MipsISA::TLB , O3ThreadContext< Impl > , Port , PowerISA::Decoder , PowerISA::TLB , RiscvISA::Decoder , RiscvISA::TLB , ROB< Impl > , SimpleThread , SparcISA::Decoder , SparcISA::TLB , ThreadContext , TimingSimpleCPU , TraceCPU , X86ISA::Decoder , X86ISA::TLB
• TapEvent() : TapEvent
• TapListener() : TapListener
• Target() : MSHR::Target , QueueEntry::Target
• target() : sc_gem5::TlmTargetBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
• targetContext() : ArmInterruptPin
• TargetList() : MSHR::TargetList , WriteQueueEntry::TargetList
• targetNBTransport() : MultiSocketSimpleSwitchAT , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• TarmacBaseRecord() : Trace::TarmacBaseRecord
• TarmacContext() : Trace::TarmacContext
• tarmacCpuName() : Trace::TarmacContext
• TarmacParser() : Trace::TarmacParser
• TarmacParserRecord() : Trace::TarmacParserRecord
• TarmacParserRecordEvent() : Trace::TarmacParserRecord::TarmacParserRecordEvent
• TarmacTracer() : Trace::TarmacTracer
• TarmacTracerRecord() : Trace::TarmacTracerRecord
• TarmacTracerRecordV8() : Trace::TarmacTracerRecordV8
• task() : ArmISA::ProcessInfo , MipsISA::ProcessInfo , PowerISA::ProcessInfo , RiscvISA::ProcessInfo , X86ISA::ProcessInfo
• taskHandler() : UFSHostDevice
• taskId() : BaseCPU , LSQ< Impl >::LSQRequest , Request
• taskStart() : UFSHostDevice
• TBETable() : TBETable< ENTRY >
• tcBase() : BaseDynInst< Impl > , CheckerCPU , ExecContext , FullO3CPU< Impl > , Minor::ExecContext , SimpleExecContext
• TCPIface() : TCPIface
• TcpPtr() : Net::TcpPtr
• Temp() : Stats::Temp
• TempCacheBlk() : TempCacheBlk
• templatedFunction() : BitUnionData
• Terminal() : Terminal
• terminalDump() : Terminal
• terminate() : ItsProcess , sc_gem5::Process
• terminated() : sc_core::sc_process_handle , sc_gem5::Process
• terminated_event() : sc_core::sc_process_handle
• terminatedEvent() : sc_gem5::Process
• terminateDiod() : VirtIO9PDiod
• Terminator() : FastModel::SCGIC::Terminator
• TermRecvQueue() : VirtIOConsole::TermRecvQueue
• TermTransQueue() : VirtIOConsole::TermTransQueue
• ternaryOp() : ArmISA::FpOp
• test() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned , test , WriteMask
• testbench() : testbench
• testCacheAccess() : CacheMemory
• testCmdAttrib() : MemCmd
• testDrainComplete() : RubyPort
• testRR() : Prefetcher::BOP
• testTranslation() : ArmISA::TLB
• testWalk() : ArmISA::TableWalker , ArmISA::TLB
• texcb() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor
• Text() : Stats::Text
• tgid() : Process
• ThermalCapacitor() : ThermalCapacitor
• ThermalDomain() : ThermalDomain
• ThermalModel() : ThermalModel
• ThermalNode() : ThermalNode
• ThermalProbeListener() : PowerModel::ThermalProbeListener
• ThermalReference() : ThermalReference
• ThermalResistor() : ThermalResistor
• thermalUpdateCallback() : PowerModel
• Thread() : sc_gem5::Thread
• threadBase() : CheckerCPU
• ThreadContext() : Iris::ThreadContext
• ThreadData() : MultiperspectivePerceptron::ThreadData
• threadId() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• ThreadInfo() : FreeBSD::ThreadInfo , Linux::ThreadInfo , SimpleIndirectPredictor::ThreadInfo
• threadSnoop() : AtomicSimpleCPU , Minor::LSQ , TimingSimpleCPU
• ThreadState() : ThreadState , Trace::ArmNativeTrace::ThreadState
• ThreeNonUniformSourceInst() : HsailISA::ThreeNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType, Src2DataType >
• ThreeNonUniformSourceInstBase() : HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
• Throttle() : Throttle
• throw_it() : sc_core::sc_process_handle , sc_gem5::BuiltinExceptionWrapper< T > , sc_gem5::ExceptionWrapper< T > , sc_gem5::ExceptionWrapperBase , sc_gem5::Process
• throwUp() : sc_gem5::Scheduler
• thumbPcElrOffset() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• thumbPcOffset() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• tick() : AtomicSimpleCPU , BaseKvmCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DRAMSim2 , DRAMSim2Wrapper , FullO3CPU< Impl > , GarnetSyntheticTraffic , IGbE , LSQ< Impl > , MemTest , sc_gem5::ClockTick
• tickClock() : MC146818
• tickDelta() : TraceCPU::FixedRetryGen
• tickDown() : sc_core::sc_clock
• Ticked() : Ticked
• TickedObject() : TickedObject
• TickEvent() : LdsState::TickEvent , TimingSimpleCPU::TimingCPUPort::TickEvent
• ticks() : Shader , TLBCoalescer , X86ISA::GpuTLB
• ticksFromHostCycles() : BaseKvmTimer
• ticksFromHostNs() : BaseKvmTimer
• ticksToCycles() : Clocked
• ticksTokHz() : EnergyCtrl
• tickToCycles() : Shader , TLBCoalescer , X86ISA::GpuTLB
• tickUp() : sc_core::sc_clock
• tidvProcess() : IGbE
• time() : Request
• Time() : Time
• time() : Time
• time_ordered_list() : tlm_utils::time_ordered_list< PAYLOAD >
• time_stamp() : sc_core::sc_clock
• timeAdvances() : sc_gem5::Scheduler
• TimeBuffer() : TimeBuffer< T >
• timed_out() : sc_core::sc_module , sc_core::sc_prim_channel
• timedOut() : sc_gem5::Process
• timeout() : sc_gem5::Process
• timeoutExpired() : Sp805
• Timer() : A9GlobalTimer::Timer , CpuLocalTimer::Timer , Sp804::Timer
• timerAtZero() : CpuLocalTimer::Timer
• timerCtrlRead() : GenericTimerMem
• timerCtrlWrite() : GenericTimerMem
• timerRead() : GenericTimerFrame
• TimerTable() : TimerTable
• timerValue() : ArchTimer
• timerWrite() : GenericTimerFrame
• TimeSlot() : sc_gem5::Scheduler::TimeSlot
• timeSync() : Root
• timeSyncEnable() : Root
• timeSyncEnabled() : Root
• timeSyncPeriod() : Root
• timeSyncSpinThreshold() : Root
• timeToPending() : sc_gem5::Scheduler
• TimingCPUPort() : TimingSimpleCPU::TimingCPUPort
• TimingExpr() : TimingExpr
• TimingExprBin() : TimingExprBin
• TimingExprEvalContext() : TimingExprEvalContext
• TimingExprIf() : TimingExprIf
• TimingExprLet() : TimingExprLet
• TimingExprLiteral() : TimingExprLiteral
• TimingExprReadIntReg() : TimingExprReadIntReg
• TimingExprRef() : TimingExprRef
• TimingExprSrcReg() : TimingExprSrcReg
• TimingExprUn() : TimingExprUn
• timings() : BasePixelPump
• TimingSimpleCPU() : TimingSimpleCPU
• TLB() : ArmISA::TLB , Iris::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::TLB
• TLBCoalescer() : TLBCoalescer
• TlbEntry() : ArmISA::TlbEntry , MipsISA::TlbEntry , PowerISA::TlbEntry , RiscvISA::TlbEntry , SparcISA::TlbEntry , X86ISA::TlbEntry
• TLBEvent() : X86ISA::GpuTLB::TLBEvent
• TlbFault() : MipsISA::TlbFault< T >
• TLBIALL() : ArmISA::TLBIALL
• TLBIALLN() : ArmISA::TLBIALLN
• TLBIASID() : ArmISA::TLBIASID
• TLBIIPA() : ArmISA::TLBIIPA
• TLBIMVA() : ArmISA::TLBIMVA
• TLBIMVAA() : ArmISA::TLBIMVAA
• TlbInvalidFault() : MipsISA::TlbInvalidFault
• TLBIOp() : ArmISA::TLBIOp
• tlbLookup() : X86ISA::GpuTLB
• TlbModifiedFault() : MipsISA::TlbModifiedFault
• TLBPort() : GpuDispatcher::TLBPort
• TlbRefillFault() : MipsISA::TlbRefillFault
• TlbTestInterface() : ArmISA::TlbTestInterface
• tlm_analysis_fifo() : tlm::tlm_analysis_fifo< T >
• tlm_analysis_port() : tlm::tlm_analysis_port< T >
• tlm_analysis_triple() : tlm::tlm_analysis_triple< T >
• tlm_array() : tlm::tlm_array< T >
• tlm_base_initiator_socket() : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
• tlm_base_target_socket() : tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL >
• tlm_bool() : tlm::tlm_bool< D >
• tlm_dmi() : tlm::tlm_dmi
• tlm_endian_context() : tlm::tlm_endian_context
• tlm_endian_context_pool() : tlm::tlm_endian_context_pool
• tlm_event_finder_t() : tlm::tlm_event_finder_t< IF, T >
• tlm_fifo() : tlm::tlm_fifo< T >
• tlm_generic_payload() : tlm::tlm_generic_payload
• tlm_global_quantum() : tlm::tlm_global_quantum
• tlm_initiator_socket() : tlm::tlm_initiator_socket< BUSWIDTH, TYPES, N, POL >
• tlm_master_imp() : tlm::tlm_master_imp< REQ, RSP >
• tlm_nonblocking_get_port() : tlm::tlm_nonblocking_get_port< T >
• tlm_nonblocking_peek_port() : tlm::tlm_nonblocking_peek_port< T >
• tlm_nonblocking_put_port() : tlm::tlm_nonblocking_put_port< T >
• tlm_phase() : tlm::tlm_phase
• tlm_put_get_imp() : tlm::tlm_put_get_imp< PUT_DATA, GET_DATA >
• tlm_quantumkeeper() : tlm_utils::tlm_quantumkeeper
• tlm_req_rsp_channel() : tlm::tlm_req_rsp_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• tlm_slave_imp() : tlm::tlm_slave_imp< REQ, RSP >
• tlm_slave_to_transport() : tlm::tlm_slave_to_transport< REQ, RSP >
• tlm_target_socket() : tlm::tlm_target_socket< BUSWIDTH, TYPES, N, POL >
• tlm_transport_channel() : tlm::tlm_transport_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• tlm_transport_to_master() : tlm::tlm_transport_to_master< REQ, RSP >
• TlmInitiatorBaseWrapper() : sc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
• TlmSenderState() : sc_gem5::TlmToGem5Bridge< BITWIDTH >::TlmSenderState
• TlmTargetBaseWrapper() : sc_gem5::TlmTargetBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
• TlmToGem5Bridge() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• to_anything_signed() : sc_dt::sc_proxy< X >
• to_anything_unsigned() : sc_dt::sc_proxy< X >
• to_bin() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_bool() : sc_dt::sc_bit , sc_dt::sc_bitref_r< T > , sc_dt::sc_int_bitref_r , sc_dt::sc_logic , sc_dt::sc_signed_bitref_r , sc_dt::sc_uint_bitref_r , sc_dt::sc_unsigned_bitref_r
• to_char() : sc_dt::sc_bit , sc_dt::sc_bitref_r< T > , sc_dt::sc_logic
• to_dec() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_double() : sc_core::sc_time , sc_core::sc_time_tuple , sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r , sc_dt::scfx_rep
• to_float() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_hex() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_int() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• to_int64() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• to_long() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• to_oct() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_sc_signed() : sc_dt::sc_concatref
• to_sc_unsigned() : sc_dt::sc_concatref
• to_seconds() : sc_core::sc_time
• to_short() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_string() : AddrRange , sc_core::sc_time , sc_core::sc_time_tuple , sc_dt::sc_concatref , sc_dt::sc_fxcast_switch , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxtype_params , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_length_param , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r , sc_dt::scfx_rep
• to_uint() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• to_uint64() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r , sc_dt::scfx_rep
• to_ulong() : sc_dt::sc_concatref , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_int_base , sc_dt::sc_int_subref_r , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_subref_r
• to_ushort() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast
• to_value() : sc_dt::sc_bit , sc_dt::sc_logic
• toDictionaryEntry() : DictionaryCompressor< T >
• toggle_tc() : sc_dt::scfx_rep
• toggleSync() : DistIface
• toHostAddr() : AbstractMemory
• toInt() : MemCmd
• TokenManager() : TokenManager
• TokenMasterPort() : TokenMasterPort
• TokenSlavePort() : TokenSlavePort
• toLookupLevel() : ArmISA::TableWalker
• toMicroVolt() : EnergyCtrl
• top() : ReturnAddrStack , tlm_utils::time_ordered_list< PAYLOAD > , top< T >
• top_delta() : tlm_utils::time_ordered_list< PAYLOAD >
• top_time() : tlm_utils::time_ordered_list< PAYLOAD >
• topIdx() : ReturnAddrStack
• toPixel() : PixelConverter::Channel , PixelConverter
• Topology() : Topology
• tos() : Net::IpHdr
• toStr() : LinearEquation , LinearSystem , MathExpr::Node , MathExpr
• toString() : MemCmd
• total() : Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::Vector2dBase< Derived, Stor > , Stats::Vector2dInfo , Stats::Vector2dInfoProxy< Stat > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• totalInsts() : BaseCPU , BaseKvmCPU , BaseSimpleCPU , CheckerCPU , FullO3CPU< Impl > , Iris::BaseCPU , MinorCPU , TraceCPU
• totalNumPhysRegs() : PhysRegFile
• totalOps() : BaseCPU , BaseKvmCPU , BaseSimpleCPU , CheckerCPU , FullO3CPU< Impl > , Iris::BaseCPU , MinorCPU , TraceCPU
• totalSize() : PhysicalMemory
• totalSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• touch() : BaseReplacementPolicy , BRRIPRP , FIFORP , LFURP , LRURP , MRURP , RandomRP , SecondChanceRP , TreePLRURP , WeightedLRUPolicy
• TournamentBP() : TournamentBP
• tr() : Net::IpOpt
• trace() : ArmISA::StackTrace , Event , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , sc_gem5::Scheduler , sc_gem5::TraceFile , sc_gem5::VcdTraceFile , SparcISA::StackTrace , X86ISA::StackTrace
• traceCommit() : SimpleTrace
• TraceCPU() : TraceCPU
• traceDeltas() : sc_gem5::TraceFile
• TraceEntryV8() : Trace::TarmacTracerRecordV8::TraceEntryV8
• traceFetch() : SimpleTrace
• TraceFile() : sc_gem5::TraceFile
• traceFunctions() : BaseCPU
• traceFunctionsInternal() : BaseCPU
• TraceGen() : TraceGen
• TraceInfo() : ElasticTrace::TraceInfo
• traceInst() : Trace::ExeTracerRecord , Trace::InstPBTrace
• TraceInstEntry() : Trace::TarmacTracerRecord::TraceInstEntry
• TraceInstEntryV8() : Trace::TarmacTracerRecordV8::TraceInstEntryV8
• traceMem() : Trace::InstPBTrace
• TraceMemEntry() : Trace::TarmacTracerRecord::TraceMemEntry
• TraceMemEntryV8() : Trace::TarmacTracerRecordV8::TraceMemEntryV8
• TraceRegEntry() : Trace::TarmacTracerRecord::TraceRegEntry
• TraceRegEntryV8() : Trace::TarmacTracerRecordV8::TraceRegEntryV8
• TraceVal() : sc_gem5::TraceVal< T, Base > , sc_gem5::TraceVal<::sc_core::sc_event, Base > , sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base >
• TraceValBase() : sc_gem5::TraceValBase
• TraceValFxnumBase() : sc_gem5::TraceValFxnumBase< T, Base >
• trackLoadLocked() : AbstractMemory , CacheBlk
• trackMissIndex1() : Prefetcher::IndirectMemory
• trackMissIndex2() : Prefetcher::IndirectMemory
• TrafficGen() : TrafficGen
• TrafficGenPort() : BaseTrafficGen::TrafficGenPort
• train() : MultiperspectivePerceptron
• Transaction() : MemChecker::Transaction
• transferDone() : NSGigE , Sinic::Device , UFSHostDevice
• transferHandler() : UFSHostDevice
• transferStart() : UFSHostDevice
• transition() : BaseTrafficGen
• translate() : EmulationPageTable , Gicv3Its , RiscvISA::TLB , SparcISA::PageTableEntry , X86ISA::GpuTLB , X86ISA::TLB
• translateAddress() : FastModel::CortexA76TC , Iris::ThreadContext
• translateAtomic() : ArmISA::TLB , BaseTLB , Iris::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• translateComplete() : ArmISA::TLB
• translateData() : PowerISA::TLB , SparcISA::TLB
• translateFs() : ArmISA::TLB
• translateFunctional() : ArmISA::TLB , BaseTLB , Iris::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::TLB
• translateInst() : PowerISA::TLB , SparcISA::TLB
• translateInt() : X86ISA::GpuTLB , X86ISA::TLB
• translateLPI() : ItsTranslation
• translateMmuOff() : ArmISA::TLB
• translateMmuOn() : ArmISA::TLB
• transLatency() : DVFSHandler
• translateOrDie() : HSADevice , HSAPacketProcessor
• translateSe() : ArmISA::TLB
• translateStage1And2() : SMMUTranslationProcess
• translateStage2() : SMMUTranslationProcess
• translateTiming() : ArmISA::Stage2MMU::Stage2Translation , ArmISA::TLB , BaseTLB , Iris::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• translateWithTLB() : RiscvISA::TLB
• TranslatingPortProxy() : TranslatingPortProxy
• translationCheck() : ArmISA::TlbTestInterface
• translationComplete() : Prefetcher::Queued
• translationCompleted() : BaseDynInst< Impl >
• translationFault() : TimingSimpleCPU
• translationReturn() : X86ISA::GpuTLB
• translationStarted() : BaseDynInst< Impl >
• TranslationState() : X86ISA::GpuTLB::TranslationState
• transmit() : DistEtherLink::TxLink , EtherLink::Link , EtherSwitch::Interface , NSGigE , Sinic::Device
• transport() : tlm::tlm_transport_if< REQ, RSP > , tlm::tlm_transport_to_master< REQ, RSP >
• transport_dbg() : ExplicitATTarget , ExplicitLTTarget , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , SimpleLTTarget2 , SimpleLTTarget_ext , tlm::tlm_transport_dbg_if< TRANS > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• transport_debug() : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• transportDebug() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• tranTypeEL() : ArmISA::TLB
• trap() : BaseO3DynInst< Impl > , BaseRemoteGDB , FullO3CPU< Impl > , MiscRegOp64
• Trap() : SparcISA::Trap
• trap_value() : RiscvISA::AddressFault , RiscvISA::BreakpointFault , RiscvISA::InstFault , RiscvISA::RiscvFault
• TrapEvent() : BaseRemoteGDB::TrapEvent
• TrapInstruction() : SparcISA::TrapInstruction
• trapType() : SparcISA::EnumeratedFault< T > , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• trapWFx() : ArmISA::ArmStaticInst
• TreePLRUReplData() : TreePLRURP::TreePLRUReplData
• TreePLRURP() : TreePLRURP
• trickBoxCheck() : ArmISA::TLB
• Trie() : Trie< Key, Value >
• triggered() : sc_core::sc_event , sc_gem5::Event
• triggeredStamp() : sc_gem5::Event
• triggerTimerInterrupt() : X86ISA::Interrupts
• tryAccess() : BankedArray
• tryCacheAccess() : CacheMemory , GPUCoalescer
• tryCompleteDrain() : AtomicSimpleCPU , TimingSimpleCPU
• tryDrain() : BaseKvmCPU , DrainManager , FullO3CPU< Impl >
• tryFile() : BrigObject
• tryGet() : DmaReadFifo
• tryGetRegList() : BaseArmKvmCPU
• tryLoaders() : Process
• trylock() : sc_core::sc_mutex , sc_core::sc_mutex_if
• tryMemsetBlob() : PortProxy , TranslatingPortProxy
• tryNext() : TraceCPU::FixedRetryGen
• tryPCEvents() : Minor::Execute
• tryReadBlob() : PortProxy , TranslatingPortProxy
• tryReadString() : PortProxy
• trySatisfyFunctional() : Bridge::BridgeMasterPort , MemDelay , MSHR::TargetList , MSHR , Packet , PacketQueue , Queue< Entry > , QueuedMasterPort , QueuedSlavePort , SerialLink::SerialLinkMasterPort , TokenSlavePort , WriteQueueEntry::TargetList , WriteQueueEntry
• trySend() : TimingRequestProtocol , VirtIOConsole::TermRecvQueue
• trySendPacket() : LSQUnit< Impl >
• trySendRetries() : RubyPort
• trySendRetry() : SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort
• trySendTiming() : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort , SerialLink::SerialLinkMasterPort , SerialLink::SerialLinkSlavePort
• trySendTimingReq() : DmaPort
• tryTiming() : BaseCache::CpuSidePort , BaseXBar::Layer< SrcType, DstType > , CommMonitor::MonitorSlavePort , CommMonitor , MasterPort , MemDelay::SlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SlavePort , TimingResponseProtocol
• tryTLBs() : TranslatingPortProxy
• tryTLBsOnce() : TranslatingPortProxy
• tryToBranch() : Minor::Execute
• tryToSend() : Minor::Fetch1 , Minor::LSQ
• tryToSendToTransfers() : Minor::Fetch1 , Minor::LSQ
• tryToSuppressFault() : Minor::LSQ::LSQRequest
• trywait() : sc_core::sc_semaphore , sc_core::sc_semaphore_if
• tryWriteBlob() : PortProxy , TranslatingPortProxy
• tryWriteString() : PortProxy
• ts() : Net::IpOpt
• tsecr() : Net::TcpOpt
• tsval() : Net::TcpOpt
• TteRead() : SparcISA::TLB
• TteTag() : SparcISA::TteTag
• ttl() : Net::IpHdr
• TurnaroundPolicy() : QoS::TurnaroundPolicy
• TurnaroundPolicyIdeal() : QoS::TurnaroundPolicyIdeal
• TwoNonUniformSourceInst() : HsailISA::TwoNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType >
• TwoNonUniformSourceInstBase() : HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
• txComplete() : EtherLink::Link
• TxDescCache() : IGbE::TxDescCache
• txDmaDone() : Sinic::Device
• txDmaReadDone() : NSGigE
• txDmaWriteDone() : NSGigE
• txDone() : DistEtherLink::TxLink , EtherBus , EtherLink::Link
• txDump() : NSGigE , Sinic::Device
• txEventTransmit() : NSGigE , Sinic::Device
• txKick() : NSGigE , Sinic::Device
• TxLink() : DistEtherLink::TxLink
• txReset() : NSGigE
• txStateMachine() : IGbE
• txWire() : IGbE
• type() : ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::LongDescriptor , BaseRemoteGDB::TrapEvent , Net::EthHdr , Net::IpOpt , Net::TcpOpt
• type_params() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_params
• typeClass() : Net::IpOpt
• typeCopied() : Net::IpOpt
• TypedBufferArg() : TypedBufferArg< T >
• typeNumber() : Net::IpOpt
• typeOfSmallest() : PersistentTable
• typeToStr() : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode