Base, ISA-independent static instruction class. More...

#include <static_inst.hh>

Inheritance diagram for StaticInst:

Public Types
enum	{ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }

typedef TheISA::ExtMachInst	ExtMachInst
	Binary extended machine instruction type. More...

Public Member Functions
void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue. More...

const RegId &	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg. More...

const RegId &	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg. More...

virtual	~StaticInst ()

virtual Fault	execute (ExecContext xc, Trace::InstRecord traceData) const =0

virtual Fault	initiateAcc (ExecContext xc, Trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, Trace::InstRecord *traceData) const

virtual void	advancePC (TheISA::PCState &pcState) const =0

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc. More...

virtual TheISA::PCState	branchTarget (const TheISA::PCState &pc) const
	Return the target address for a PC-relative branch. More...

virtual TheISA::PCState	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump). More...

bool	hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
	Return true if the instruction is a control transfer, and if so, return the target address as well. More...

virtual const std::string &	disassemble (Addr pc, const Loader::SymbolTable *symtab=nullptr) const
	Return string representation of disassembled instruction. More...

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream. More...

std::string	getName ()
	Return name of machine instruction. More...

virtual size_t	asBytes (void *buf, size_t max_size)
	Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...

Register information.
The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(), numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs(). The former two functions are used to track physical register usage for machines with separate int & FP reg files, the next three are for machines with vector and predicate register files.
int8_t	numSrcRegs () const
	Number of source registers. More...

int8_t	numDestRegs () const
	Number of destination registers. More...

int8_t	numFPDestRegs () const
	Number of floating-point destination regs. More...

int8_t	numIntDestRegs () const
	Number of integer destination regs. More...

int8_t	numVecDestRegs () const
	Number of vector destination regs. More...

int8_t	numVecElemDestRegs () const
	Number of vector element destination regs. More...

int8_t	numVecPredDestRegs () const
	Number of predicate destination regs. More...

int8_t	numCCDestRegs () const
	Number of coprocesor destination regs. More...

Flag accessors.
These functions are used to access the values of the various instruction property flags. See StaticInst::Flags for descriptions of the individual flags.
bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isCC () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isCondDelaySlot () const

bool	isThreadSync () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isMemBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isIprAccess () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isMicroBranch () const

Public Member Functions inherited from RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref () const
	Increment the reference count. More...

void	decref () const
	Decrement the reference count and destroy the object if all references are gone. More...

Public Attributes
const ExtMachInst	machInst
	The binary machine instruction. More...

Static Public Attributes
static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object. More...

static StaticInstPtr	nopStaticInstPtr = new NopStaticInst
	Pointer to a statically allocated generic "nop" instruction object. More...

Protected Member Functions
virtual std::string	generateDisassembly (Addr pc, const Loader::SymbolTable *symtab) const =0
	Internal function to generate disassembly string. More...

	StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
	Constructor. More...

template<typename T >
size_t	simpleAsBytes (void *buf, size_t max_size, const T &t)

Protected Attributes
std::bitset< Num_Flags >	flags
	Flag values for this instruction. More...

OpClass	_opClass
	See opClass(). More...

int8_t	_numSrcRegs
	See numSrcRegs(). More...

int8_t	_numDestRegs
	See numDestRegs(). More...

RegId	_destRegIdx [MaxInstDestRegs]
	See destRegIdx(). More...

RegId	_srcRegIdx [MaxInstSrcRegs]
	See srcRegIdx(). More...

const char *	mnemonic
	Base mnemonic (e.g., "add"). More...

std::string *	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()). More...


int8_t	_numFPDestRegs
	The following are used to track physical register usage for machines with separate int & FP reg files. More...

int8_t	_numIntDestRegs

int8_t	_numCCDestRegs


int8_t	_numVecDestRegs
	To use in architectures with vector register file. More...

int8_t	_numVecElemDestRegs

int8_t	_numVecPredDestRegs

Detailed Description

Base, ISA-independent static instruction class.

The main component of this class is the vector of flags and the associated methods for reading them. Any object that can rely solely on these flags can process instructions without being recompiled for multiple ISAs.

Definition at line 85 of file static_inst.hh.

Member Typedef Documentation

◆ ExtMachInst

typedef TheISA::ExtMachInst StaticInst::ExtMachInst

Binary extended machine instruction type.

Definition at line 89 of file static_inst.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum

Enumerator
MaxInstSrcRegs
MaxInstDestRegs

Definition at line 91 of file static_inst.hh.

Constructor & Destructor Documentation

◆ StaticInst()

StaticInst::StaticInst	(	const char *	_mnemonic,
		ExtMachInst	_machInst,
		OpClass	__opClass
	)

inlineprotected

Constructor.

It's important to initialize everything here to a sane default, since the decoder generally only overrides the fields that are meaningful for the particular instruction.

Definition at line 265 of file static_inst.hh.

◆ ~StaticInst()

StaticInst::~StaticInst ( )

virtual

Definition at line 74 of file static_inst.cc.

Member Function Documentation

◆ advancePC()

virtual void StaticInst::advancePC ( TheISA::PCState & pcState ) const

pure virtual

Referenced by GenericISA::M5DebugFault::advancePC(), SparcISA::advancePC(), X86ISA::advancePC(), RiscvISA::advancePC(), ArmISA::advancePC(), Minor::Decode::evaluate(), and ArmISA::SupervisorCall::invoke().

◆ asBytes()

virtual size_t StaticInst::asBytes	(	void *	buf,
		size_t	max_size
	)

inlinevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented in ArmISA::ArmStaticInst, SparcISA::SparcStaticInst, PowerISA::PowerStaticInst, and RiscvISA::RiscvStaticInst.

Definition at line 363 of file static_inst.hh.

Referenced by Trace::InstPBTrace::traceInst().

◆ branchTarget() [1/2]

TheISA::PCState StaticInst::branchTarget ( const TheISA::PCState & pc ) const

virtual

Return the target address for a PC-relative branch.

Invalid if not a PC-relative branch (i.e. isDirectCtrl() should be true).

Definition at line 105 of file static_inst.cc.

References panic.

Referenced by ArmISA::BranchImm64::BranchImm64(), ArmISA::BranchImmImmReg64::BranchImmImmReg64(), ArmISA::BranchImmReg64::BranchImmReg64(), PowerISA::BranchNonPCRel::BranchNonPCRel(), PowerISA::BranchNonPCRelCond::BranchNonPCRelCond(), PowerISA::BranchPCRel::BranchPCRel(), PowerISA::BranchPCRelCond::BranchPCRelCond(), PowerISA::BranchRegCond::BranchRegCond(), and BaseDynInst< Impl >::branchTarget().

◆ branchTarget() [2/2]

TheISA::PCState StaticInst::branchTarget ( ThreadContext * tc ) const

virtual

Return the target address for an indirect branch (jump).

The register value is read from the supplied thread context, so the result is valid only if the thread context is about to execute the branch in question. Invalid if not an indirect branch (i.e. isIndirectCtrl() should be true).

Reimplemented in PowerISA::BranchRegCond.

Definition at line 113 of file static_inst.cc.

References panic.

◆ completeAcc()

virtual Fault StaticInst::completeAcc	(	Packet *	pkt,
		ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

inlinevirtual

Definition at line 284 of file static_inst.hh.

References ArmISA::advancePC(), panic, and MipsISA::pc.

Referenced by BaseO3DynInst< Impl >::completeAcc(), and TimingSimpleCPU::completeDataAccess().

◆ destRegIdx()

const RegId& StaticInst::destRegIdx ( int i ) const

inline

Return logical index (architectural reg num) of i'th destination reg.

Only the entries from 0 through numDestRegs()-1 are valid.

Definition at line 218 of file static_inst.hh.

References ArmISA::i.

◆ disassemble()

const string & StaticInst::disassemble	(	Addr	pc,
		const Loader::SymbolTable *	symtab = `nullptr`
	)		const

virtual

Return string representation of disassembled instruction.

The default version of this function will call the internal virtual generateDisassembly() function to get the string, then cache it in cachedDisassembly. If the disassembly should not be cached, this function should be overridden directly.

Reimplemented in PowerISA::PCDependentDisassembly.

Definition at line 121 of file static_inst.cc.

Referenced by Minor::Scoreboard::canInstIssue(), BaseDynInst< Impl >::dump(), Minor::FUPipeline::findTiming(), X86ISA::PageFault::invoke(), Minor::MinorDynInst::minorTraceInst(), Trace::TarmacParserRecord::printMismatchHeader(), Trace::TarmacBaseRecord::TarmacBaseRecord(), Trace::ExeTracerRecord::traceInst(), and BaseO3DynInst< Impl >::~BaseO3DynInst().

◆ execute()

virtual Fault StaticInst::execute	(	ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

pure virtual

Implemented in ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, McrMrcImplDefined, McrMrcMiscInst, ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::PredMacroOp, ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >, MiscRegImplDefined64, ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >, IllegalExecInst, WarnUnimplemented, SparcISA::WarnUnimplemented, RiscvISA::RiscvMacroInst, ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >, FailUnimplemented, SparcISA::SparcMacroInst, SparcISA::FailUnimplemented, RiscvISA::Unknown, DecoderFaultInst, SparcISA::Nop, RiscvISA::MemFenceMicro, and SparcISA::Unknown.

Referenced by TimingSimpleCPU::completeIfetch(), BaseO3DynInst< Impl >::execute(), MiscRegImplDefined64::MiscRegImplDefined64(), and AtomicSimpleCPU::tick().

◆ fetchMicroop()

StaticInstPtr StaticInst::fetchMicroop ( MicroPC upc ) const

virtual

Return the microop that goes with a particular micropc.

This should only be defined/used in macroops which will contain microops

Reimplemented in ArmISA::PredMacroOp, ArmISA::Memory, ArmISA::SrsOp, ArmISA::Memory64, ArmISA::RfeOp, RiscvISA::RiscvMacroInst, X86ISA::MacroopBase, and SparcISA::SparcMacroInst.

Definition at line 98 of file static_inst.cc.

References panic.

Referenced by Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseSimpleCPU::preExecute(), and Checker< O3CPUImpl >::verify().

◆ generateDisassembly()

virtual std::string StaticInst::generateDisassembly	(	Addr	pc,
		const Loader::SymbolTable *	symtab
	)		const

protectedpure virtual

Internal function to generate disassembly string.

Implemented in ArmISA::FpRegRegRegImmOp, ArmISA::FpRegRegRegRegOp, ArmISA::FpRegRegRegCondOp, ArmISA::FpRegRegRegOp, ArmISA::FpRegRegImmOp, ArmISA::FpRegImmOp, ArmISA::FpRegRegOp, ArmISA::FpCondSelOp, ArmISA::SveComplexIdxOp, ArmISA::FpCondCompRegOp, ArmISA::SveComplexOp, ArmISA::SveDotProdOp, ArmISA::SveDotProdIdxOp, ArmISA::SveUnarySca2VecUnpredOp, ArmISA::SveBinImmIdxUnpredOp, ArmISA::SveBinImmUnpredDestrOp, ArmISA::SveWImplicitSrcDstOp, ArmISA::SvePredUnaryWImplicitDstOp, ArmISA::SvePredUnaryWImplicitSrcPredOp, ArmISA::SvePredUnaryWImplicitSrcOp, ArmISA::SvePredTestOp, ArmISA::SveUnpackOp, ArmISA::SveTblOp, ArmISA::SveUnaryPredPredOp, ArmISA::SveSelectOp, ArmISA::SvePartBrkPropOp, ArmISA::SvePartBrkOp, ArmISA::SveElemCountOp, ArmISA::SveAdrOp, ArmISA::SveIntCmpImmOp, ArmISA::SveIntCmpOp, ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::SvePtrueOp, ArmISA::SveOrdReducOp, ArmISA::SveReducOp, ArmISA::SveTerImmUnpredOp, ArmISA::SveTerPredOp, ArmISA::SveCmpImmOp, McrMrcImplDefined, ArmISA::MicroMemPairOp, ArmISA::SveCmpOp, ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, McrMrcMiscInst, ArmISA::MicroMemOp, ArmISA::SvePredBinPermOp, UnknownOp, ArmISA::SvePredLogicalOp, RegImmRegShiftOp, ArmISA::PredMacroOp, ArmISA::SveBinIdxUnpredOp, ArmISA::MicroIntRegXOp, RegRegImmImmOp, ArmISA::SveBinUnpredOp, ArmISA::MicroIntOp, RegImmImmOp, ArmISA::SveBinConstrPredOp, ArmISA::DataRegRegOp, ArmISA::MicroIntImmXOp, RegMiscRegImmOp, ArmISA::SveBinDestrPredOp, ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::DataRegOp, ArmISA::MicroIntImmOp, ArmISA::SveBinWideImmUnpredOp, MiscRegRegImmOp, ArmISA::DataImmOp, ArmISA::MicroIntMov, ArmISA::SveBinImmPredOp, RegRegImmOp, ArmISA::PredIntOp, ArmISA::SveBinImmUnpredConstrOp, ArmISA::MicroSetPCCPSR, ArmISA::DataXCondSelOp, ArmISA::MemoryLiteral64, RegRegRegOp, PowerISA::BranchRegCond, ArmISA::PredImmOp, ArmISA::SveUnaryWideImmPredOp, ArmISA::MemoryEx64, ArmISA::DataXCondCompRegOp, RegRegRegRegOp, ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::MemoryRaw64, PowerISA::BranchNonPCRelCond, MiscRegImplDefined64, ArmISA::SveUnaryWideImmUnpredOp, ArmISA::DataXCondCompImmOp, RegRegRegImmOp, ArmISA::MemoryReg64, ArmISA::BranchImmImmReg64, ArmISA::SveUnaryUnpredOp, ArmISA::DataX3RegOp, RegImmRegOp, ArmISA::MemoryPostIndex64, RegMiscRegImmOp64, PowerISA::BranchPCRelCond, ArmISA::ArmStaticInst, ArmISA::SveUnaryPredOp, ArmISA::DataX2RegImmOp, RegOp, ArmISA::MemoryPreIndex64, ArmISA::BranchImmReg64, MiscRegRegImmOp64, ArmISA::SveCompTermOp, ArmISA::MemoryDImmEx64, RegRegOp, ArmISA::DataX2RegOp, PowerISA::IntRotateOp, ArmISA::SveWhileOp, ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >, MiscRegImmOp64, ArmISA::BranchEretA64, RegImmOp, ArmISA::DataX1Reg2ImmOp, ArmISA::MemoryDImm64, ArmISA::SvePredCountPredOp, ArmISA::SrsOp, ArmISA::BranchEret64, ArmISA::SveContigMemSI, X86ISA::LdStSplitOp, ImmOp, PowerISA::FloatOp, ArmISA::MemoryImm64, ArmISA::DataX1RegImmOp, ArmISA::BranchRetA64, PowerISA::IntShiftOp, ArmISA::SvePredCountOp, McrrOp, ArmISA::DataX1RegOp, X86ISA::MediaOpImm, ArmISA::BranchRet64, SparcISA::SetHi, ArmISA::SveContigMemSS, PowerISA::BranchNonPCRel, ArmISA::BranchRegReg, X86ISA::RegOpImm, ArmISA::SveIndexRROp, WarnUnimplemented, PowerISA::IntImmOp, X86ISA::LdStOp, ArmISA::DataXERegOp, MrrcOp, RiscvISA::AtomicMemOpMicro, X86ISA::X86MicroopBase, ArmISA::BranchReg64, SparcISA::BranchImm13, ArmISA::RfeOp, SparcISA::WarnUnimplemented, X86ISA::MediaOpReg, SparcISA::WrPrivImm, UnknownOp64, RiscvISA::AtomicMemOp, ArmISA::SveIndexRIOp, RiscvISA::CSROp, ArmISA::BranchRegReg64, ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::SveMemPredFillSpill, X86ISA::RegOp, ArmISA::DataXSRegOp, MsrRegOp, RiscvISA::StoreCondMicro, PowerISA::BranchPCRel, PowerISA::IntOp, SparcISA::SparcStaticInst, RegRegRegImmOp64, ArmISA::BranchReg, X86ISA::X86StaticInst, FailUnimplemented, X86ISA::MacroopBase, ArmISA::SveIndexIROp, RiscvISA::StoreCond, SparcISA::BlockMemImmMicro, MsrImmOp, PowerISA::CondMoveOp, ArmISA::BranchImmCond64, RiscvISA::SystemOp, X86ISA::FpOp, SparcISA::WrPriv, ArmISA::DataXImmOnlyOp, PowerISA::MemDispOp, RiscvISA::LoadReservedMicro, RegRegImmImmOp64, SparcISA::IntOpImm, SparcISA::FailUnimplemented, ArmISA::SveMemVecFillSpill, ArmISA::SveIndexIIOp, SparcISA::FpUnimpl, RiscvISA::Store, SparcISA::BlockMemMicro, SparcISA::MemImm, SparcISA::RdPriv, SparcISA::BranchDisp, RiscvISA::Unknown, ArmISA::BranchImm64, ArmISA::SysDC64, RiscvISA::LoadReserved, PowerISA::PowerStaticInst, SparcISA::Nop, ArmISA::BranchImm, ArmISA::DataXImmOp, DecoderFaultInst, PowerISA::CondLogicOp, RiscvISA::Load, SparcISA::SparcMacroInst, SparcISA::Trap, SparcISA::Unknown, PowerISA::MemOp, MrsOp, ImmOp64, RiscvISA::MemFenceMicro, RiscvISA::RegOp, SparcISA::Branch, SparcISA::IntOp, SparcISA::Mem, RiscvISA::CompRegOp, PowerISA::MiscOp, SparcISA::Priv, and RiscvISA::PseudoOp.

◆ getName()

std::string StaticInst::getName ( )

inline

Return name of machine instruction.

Definition at line 338 of file static_inst.hh.

Referenced by Minor::operator<<(), and BaseSimpleCPU::preExecute().

◆ hasBranchTarget()

bool StaticInst::hasBranchTarget	(	const TheISA::PCState &	pc,
		ThreadContext *	tc,
		TheISA::PCState &	tgt
	)		const

Return true if the instruction is a control transfer, and if so, return the target address as well.

Definition at line 81 of file static_inst.cc.

◆ initiateAcc()

virtual Fault StaticInst::initiateAcc	(	ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

inlinevirtual

Reimplemented in RiscvISA::RiscvMacroInst, and SparcISA::SparcMacroInst.

Definition at line 278 of file static_inst.hh.

References panic.

Referenced by TimingSimpleCPU::completeIfetch(), and BaseO3DynInst< Impl >::initiateAcc().

◆ isAtomic()

bool StaticInst::isAtomic ( ) const

inline

Definition at line 163 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), BaseDynInst< Impl >::isAtomic(), BaseSimpleCPU::postExecute(), and BaseCPU::probeInstCommit().

◆ isCall()

bool StaticInst::isCall ( ) const

inline

Definition at line 176 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isCall(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), MPP_StatisticalCorrector_8KB::scHistoryUpdate(), MPP_StatisticalCorrector_64KB::scHistoryUpdate(), MipsISA::StackTrace::trace(), RiscvISA::StackTrace::trace(), X86ISA::StackTrace::trace(), PowerISA::StackTrace::trace(), ArmISA::StackTrace::trace(), and MultiperspectivePerceptronTAGE::update().

◆ isCC()

bool StaticInst::isCC ( ) const

inline

Definition at line 173 of file static_inst.hh.

◆ isCondCtrl()

bool StaticInst::isCondCtrl ( ) const

inline

Definition at line 180 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isCondCtrl(), BaseSimpleCPU::postExecute(), and MultiperspectivePerceptronTAGE::update().

◆ isCondDelaySlot()

bool StaticInst::isCondDelaySlot ( ) const

inline

Definition at line 182 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isCondDelaySlot().

◆ isControl()

bool StaticInst::isControl ( ) const

inline

Definition at line 175 of file static_inst.hh.

Referenced by BaseSimpleCPU::advancePC(), BaseDynInst< Impl >::isControl(), BaseSimpleCPU::postExecute(), BaseSimpleCPU::preExecute(), BaseCPU::probeInstCommit(), and SimPoint::profile().

◆ isDataPrefetch()

bool StaticInst::isDataPrefetch ( ) const

inline

Definition at line 166 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isDataPrefetch().

◆ isDelayedCommit()

bool StaticInst::isDelayedCommit ( ) const

inline

Definition at line 200 of file static_inst.hh.

Referenced by TimingSimpleCPU::fetch(), BaseDynInst< Impl >::isDelayedCommit(), BaseSimpleCPU::swapActiveThread(), and AtomicSimpleCPU::tick().

◆ isDirectCtrl()

bool StaticInst::isDirectCtrl ( ) const

inline

Definition at line 178 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isDirectCtrl(), BPredUnit::predict(), MPP_StatisticalCorrector_8KB::scHistoryUpdate(), MPP_StatisticalCorrector_64KB::scHistoryUpdate(), TAGE_SC_L_8KB_StatisticalCorrector::scHistoryUpdate(), TAGE_SC_L_64KB_StatisticalCorrector::scHistoryUpdate(), StatisticalCorrector::scHistoryUpdate(), MultiperspectivePerceptronTAGE::update(), MPP_TAGE::updateHistories(), and TAGE_SC_L_TAGE::updateHistories().

◆ isFirstMicroop()

bool StaticInst::isFirstMicroop ( ) const

inline

Definition at line 202 of file static_inst.hh.

Referenced by TimingSimpleCPU::completeIfetch(), Trace::InstPBTraceRecord::dump(), Trace::TarmacTracerRecord::dump(), BaseDynInst< Impl >::isFirstMicroop(), and AtomicSimpleCPU::tick().

◆ isFloating()

bool StaticInst::isFloating ( ) const

inline

Definition at line 171 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), ArmISA::MicroMemOp::generateDisassembly(), BaseDynInst< Impl >::isFloating(), and BaseSimpleCPU::postExecute().

◆ isIndirectCtrl()

bool StaticInst::isIndirectCtrl ( ) const

inline

Definition at line 179 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isIndirectCtrl().

◆ isInstPrefetch()

bool StaticInst::isInstPrefetch ( ) const

inline

Definition at line 165 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isInstPrefetch().

◆ isInteger()

bool StaticInst::isInteger ( ) const

inline

Definition at line 170 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), BaseDynInst< Impl >::isInteger(), and BaseSimpleCPU::postExecute().

◆ isIprAccess()

bool StaticInst::isIprAccess ( ) const

inline

Definition at line 195 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isIprAccess().

◆ isLastMicroop()

bool StaticInst::isLastMicroop ( ) const

inline

Definition at line 201 of file static_inst.hh.

Referenced by BaseSimpleCPU::advancePC(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), BaseSimpleCPU::countInst(), Trace::TarmacParserRecord::dump(), Trace::TarmacTracerRecord::dump(), Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseDynInst< Impl >::isLastMicroop(), Minor::MinorDynInst::isLastOpInInst(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::PairMemOp::PairMemOp(), BaseCPU::probeInstCommit(), SimPoint::profile(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), and ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS().

◆ isLoad()

bool StaticInst::isLoad ( ) const

inline

Definition at line 161 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), BaseDynInst< Impl >::isLoad(), BaseSimpleCPU::postExecute(), BaseCPU::probeInstCommit(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), and ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI().

◆ isMacroop()

bool StaticInst::isMacroop ( ) const

inline

Definition at line 198 of file static_inst.hh.

Referenced by Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseDynInst< Impl >::isMacroop(), Minor::MinorDynInst::minorTraceInst(), BaseSimpleCPU::preExecute(), and Checker< O3CPUImpl >::verify().

◆ isMemBarrier()

bool StaticInst::isMemBarrier ( ) const

inline

Definition at line 191 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isMemBarrier().

◆ isMemRef()

bool StaticInst::isMemRef ( ) const

inline

Definition at line 160 of file static_inst.hh.

Referenced by TimingSimpleCPU::completeIfetch(), Minor::MinorDynInst::isMemRef(), BaseDynInst< Impl >::isMemRef(), and BaseSimpleCPU::postExecute().

◆ isMicroBranch()

bool StaticInst::isMicroBranch ( ) const

inline

Definition at line 204 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isMicroBranch().

◆ isMicroop()

bool StaticInst::isMicroop ( ) const

inline

Definition at line 199 of file static_inst.hh.

Referenced by Trace::ArmNativeTrace::check(), TimingSimpleCPU::completeIfetch(), BaseSimpleCPU::countInst(), Trace::InstPBTraceRecord::dump(), Trace::TarmacParserRecord::dump(), Trace::TarmacTracerRecord::dump(), Minor::MinorDynInst::isLastOpInInst(), BaseDynInst< Impl >::isMicroop(), BaseCPU::probeInstCommit(), SimPoint::profile(), AtomicSimpleCPU::tick(), and Trace::ExeTracerRecord::traceInst().

◆ isNonSpeculative()

bool StaticInst::isNonSpeculative ( ) const

inline

Definition at line 193 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isNonSpeculative().

◆ isNop()

bool StaticInst::isNop ( ) const

inline

Definition at line 158 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isNop().

◆ isPrefetch()

bool StaticInst::isPrefetch ( ) const

inline

Definition at line 167 of file static_inst.hh.

◆ isQuiesce()

bool StaticInst::isQuiesce ( ) const

inline

Definition at line 194 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isQuiesce().

◆ isReturn()

bool StaticInst::isReturn ( ) const

inline

Definition at line 177 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isReturn(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), MPP_StatisticalCorrector_8KB::scHistoryUpdate(), MPP_StatisticalCorrector_64KB::scHistoryUpdate(), MipsISA::StackTrace::trace(), RiscvISA::StackTrace::trace(), X86ISA::StackTrace::trace(), PowerISA::StackTrace::trace(), ArmISA::StackTrace::trace(), and MultiperspectivePerceptronTAGE::update().

◆ isSerializeAfter()

bool StaticInst::isSerializeAfter ( ) const

inline

Definition at line 189 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isSerializeAfter().

◆ isSerializeBefore()

bool StaticInst::isSerializeBefore ( ) const

inline

Definition at line 188 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isSerializeBefore().

◆ isSerializing()

bool StaticInst::isSerializing ( ) const

inline

Definition at line 185 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isSerializing().

◆ isSquashAfter()

bool StaticInst::isSquashAfter ( ) const

inline

Definition at line 190 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isSquashAfter().

◆ isStore()

bool StaticInst::isStore ( ) const

inline

Definition at line 162 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), BaseDynInst< Impl >::isStore(), BaseSimpleCPU::postExecute(), and BaseCPU::probeInstCommit().

◆ isStoreConditional()

bool StaticInst::isStoreConditional ( ) const

inline

Definition at line 164 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isStoreConditional().

◆ isSyscall()

bool StaticInst::isSyscall ( ) const

inline

Definition at line 197 of file static_inst.hh.

Referenced by Trace::X86NativeTrace::check(), and BaseDynInst< Impl >::isSyscall().

◆ isThreadSync()

bool StaticInst::isThreadSync ( ) const

inline

Definition at line 184 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isThreadSync().

◆ isUncondCtrl()

bool StaticInst::isUncondCtrl ( ) const

inline

Definition at line 181 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isUncondCtrl(), BPredUnit::predict(), MPP_StatisticalCorrector_8KB::scHistoryUpdate(), MPP_StatisticalCorrector_64KB::scHistoryUpdate(), TAGE_SC_L_8KB_StatisticalCorrector::scHistoryUpdate(), TAGE_SC_L_64KB_StatisticalCorrector::scHistoryUpdate(), StatisticalCorrector::scHistoryUpdate(), MPP_TAGE::updateHistories(), and TAGE_SC_L_TAGE::updateHistories().

◆ isUnverifiable()

bool StaticInst::isUnverifiable ( ) const

inline

Definition at line 196 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isUnverifiable().

◆ isVector()

bool StaticInst::isVector ( ) const

inline

Definition at line 172 of file static_inst.hh.

Referenced by Minor::Fetch2::evaluate(), BaseDynInst< Impl >::isVector(), and BaseSimpleCPU::postExecute().

◆ isWriteBarrier()

bool StaticInst::isWriteBarrier ( ) const

inline

Definition at line 192 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::isWriteBarrier().

◆ numCCDestRegs()

int8_t StaticInst::numCCDestRegs ( ) const

inline

Number of coprocesor destination regs.

Definition at line 149 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numCCDestRegs().

◆ numDestRegs()

int8_t StaticInst::numDestRegs ( ) const

inline

Number of destination registers.

Definition at line 137 of file static_inst.hh.

Referenced by Trace::TarmacTracerRecordV8::addRegEntry(), Trace::TarmacTracerRecord::addRegEntry(), Minor::Scoreboard::clearInstDests(), Minor::Scoreboard::markupInstDests(), Minor::MinorDynInst::minorTraceInst(), BaseDynInst< Impl >::numDestRegs(), and MsrBase::printMsrBase().

◆ numFPDestRegs()

int8_t StaticInst::numFPDestRegs ( ) const

inline

Number of floating-point destination regs.

Definition at line 139 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numFPDestRegs().

◆ numIntDestRegs()

int8_t StaticInst::numIntDestRegs ( ) const

inline

Number of integer destination regs.

Definition at line 141 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numIntDestRegs().

◆ numSrcRegs()

int8_t StaticInst::numSrcRegs ( ) const

inline

Number of source registers.

Definition at line 135 of file static_inst.hh.

Referenced by Minor::Scoreboard::canInstIssue(), Minor::Scoreboard::execSeqNumToWaitFor(), MrsOp::generateDisassembly(), Minor::MinorDynInst::minorTraceInst(), and BaseDynInst< Impl >::numSrcRegs().

◆ numVecDestRegs()

int8_t StaticInst::numVecDestRegs ( ) const

inline

Number of vector destination regs.

Definition at line 143 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numVecDestRegs().

◆ numVecElemDestRegs()

int8_t StaticInst::numVecElemDestRegs ( ) const

inline

Number of vector element destination regs.

Definition at line 145 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numVecElemDestRegs().

◆ numVecPredDestRegs()

int8_t StaticInst::numVecPredDestRegs ( ) const

inline

Number of predicate destination regs.

Definition at line 147 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numVecPredDestRegs().

◆ opClass()

OpClass StaticInst::opClass ( ) const

inline

Operation class. Used to select appropriate function unit in issue.

Definition at line 213 of file static_inst.hh.

Referenced by Minor::FUPipeline::findTiming(), Minor::MinorDynInst::isNoCostInst(), Minor::MinorDynInst::minorTraceInst(), BaseDynInst< Impl >::opClass(), BaseSimpleCPU::postExecute(), Trace::ExeTracerRecord::traceInst(), Trace::InstPBTrace::traceInst(), and Trace::InstPBTrace::traceMem().

◆ printFlags()

void StaticInst::printFlags	(	std::ostream &	outs,
		const std::string &	separator
	)		const

Print a separator separated list of this instruction's set flag names on the given stream.

Definition at line 130 of file static_inst.cc.

Referenced by Minor::MinorDynInst::minorTraceInst(), and Trace::ExeTracerRecord::traceInst().

◆ setDelayedCommit()

void StaticInst::setDelayedCommit ( )

inline

Definition at line 209 of file static_inst.hh.

Referenced by ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

◆ setFirstMicroop()

void StaticInst::setFirstMicroop ( )

inline

Definition at line 207 of file static_inst.hh.

Referenced by ArmISA::BigFpMemImmOp::BigFpMemImmOp(), ArmISA::BigFpMemLitOp::BigFpMemLitOp(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), ArmISA::BigFpMemRegOp::BigFpMemRegOp(), ArmISA::PairMemOp::PairMemOp(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstMultOp::VstMultOp(), and ArmISA::VstSingleOp::VstSingleOp().

◆ setFlag()

void StaticInst::setFlag ( Flags f )

inline

Definition at line 210 of file static_inst.hh.

References ArmISA::f.

Referenced by ArmISA::MacroMemOp::MacroMemOp().

◆ setLastMicroop()

void StaticInst::setLastMicroop ( )

inline

Definition at line 208 of file static_inst.hh.

Referenced by ArmISA::BigFpMemLitOp::BigFpMemLitOp(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::PairMemOp::PairMemOp(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

◆ simpleAsBytes()

template<typename T >

size_t StaticInst::simpleAsBytes	(	void *	buf,
		size_t	max_size,
		const T &	t
	)

inlineprotected

Definition at line 343 of file static_inst.hh.

Referenced by RiscvISA::RiscvStaticInst::asBytes(), PowerISA::PowerStaticInst::asBytes(), SparcISA::SparcStaticInst::asBytes(), and ArmISA::ArmStaticInst::asBytes().

◆ srcRegIdx()

const RegId& StaticInst::srcRegIdx ( int i ) const

inline

Return logical index (architectural reg num) of i'th source reg.

Only the entries from 0 through numSrcRegs()-1 are valid.

Definition at line 222 of file static_inst.hh.

References ArmISA::i.

Member Data Documentation

◆ _destRegIdx

RegId StaticInst::_destRegIdx[MaxInstDestRegs]

protected

See destRegIdx().

Definition at line 236 of file static_inst.hh.

Referenced by PowerISA::MiscOp::generateDisassembly(), RiscvISA::CompRegOp::generateDisassembly(), SparcISA::Mem::generateDisassembly(), SparcISA::BlockMemMicro::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), SparcISA::BlockMemImmMicro::generateDisassembly(), SparcISA::SparcStaticInst::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), SparcISA::SparcStaticInst::printDestReg(), and X86ISA::X86StaticInst::printDestReg().

◆ _numCCDestRegs

int8_t StaticInst::_numCCDestRegs

protected

Definition at line 115 of file static_inst.hh.

◆ _numDestRegs

int8_t StaticInst::_numDestRegs

protected

See numDestRegs().

Definition at line 108 of file static_inst.hh.

Referenced by PowerISA::MiscOp::generateDisassembly(), SparcISA::Branch::generateDisassembly(), SparcISA::IntOp::generateDisassembly(), SparcISA::IntOpImm::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), SparcISA::SparcStaticInst::generateDisassembly(), SparcISA::BranchImm13::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), SparcISA::SparcStaticInst::printDestReg(), and X86ISA::X86StaticInst::printDestReg().

◆ _numFPDestRegs

int8_t StaticInst::_numFPDestRegs

protected

The following are used to track physical register usage for machines with separate int & FP reg files.

Definition at line 113 of file static_inst.hh.

◆ _numIntDestRegs

int8_t StaticInst::_numIntDestRegs

protected

Definition at line 114 of file static_inst.hh.

◆ _numSrcRegs

int8_t StaticInst::_numSrcRegs

protected

See numSrcRegs().

Definition at line 105 of file static_inst.hh.

Referenced by PowerISA::BranchRegCond::branchTarget(), PowerISA::MiscOp::generateDisassembly(), SparcISA::Branch::generateDisassembly(), SparcISA::IntOp::generateDisassembly(), SparcISA::IntOpImm::generateDisassembly(), SparcISA::SparcStaticInst::generateDisassembly(), SparcISA::BranchImm13::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), SparcISA::IntOpImm::printPseudoOps(), SparcISA::SparcStaticInst::printSrcReg(), and X86ISA::X86StaticInst::printSrcReg().

◆ _numVecDestRegs

int8_t StaticInst::_numVecDestRegs

protected

To use in architectures with vector register file.

Definition at line 120 of file static_inst.hh.

◆ _numVecElemDestRegs

int8_t StaticInst::_numVecElemDestRegs

protected

Definition at line 121 of file static_inst.hh.

◆ _numVecPredDestRegs

int8_t StaticInst::_numVecPredDestRegs

protected

Definition at line 122 of file static_inst.hh.

◆ _opClass

OpClass StaticInst::_opClass

protected

See opClass().

Definition at line 102 of file static_inst.hh.

◆ _srcRegIdx

RegId StaticInst::_srcRegIdx[MaxInstSrcRegs]

protected

See srcRegIdx().

Definition at line 238 of file static_inst.hh.

◆ cachedDisassembly

std::string* StaticInst::cachedDisassembly

mutableprotected

String representation of disassembly (lazily evaluated via disassemble()).

Definition at line 252 of file static_inst.hh.

Referenced by PowerISA::PCDependentDisassembly::disassemble().

◆ flags

std::bitset<Num_Flags> StaticInst::flags

protected

Flag values for this instruction.

Definition at line 99 of file static_inst.hh.

Referenced by ArmISA::MightBeMicro::advancePC(), ArmISA::MicroOp::advancePC(), ArmISA::MightBeMicro64::advancePC(), ArmISA::MicroOpX::advancePC(), SparcISA::SparcMicroInst::advancePC(), RiscvISA::RiscvMicroInst::advancePC(), ArmISA::FpOp::advancePC(), X86ISA::X86MicroopBase::checkCondition(), DecoderFaultInst::DecoderFaultInst(), FailUnimplemented::FailUnimplemented(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), SparcISA::Mem::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), SparcISA::BlockMemMicro::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), SparcISA::BlockMemImmMicro::generateDisassembly(), X86ISA::LdStOp::generateDisassembly(), X86ISA::LdStSplitOp::generateDisassembly(), X86ISA::RegOpBase::genFlags(), X86ISA::MacroopBase::MacroopBase(), McrMrcMiscInst::McrMrcMiscInst(), SparcISA::Nop::Nop(), RiscvISA::RiscvMacroInst::RiscvMacroInst(), RiscvISA::RiscvMicroInst::RiscvMicroInst(), SparcISA::SparcDelayedMicroInst::SparcDelayedMicroInst(), SparcISA::SparcMacroInst::SparcMacroInst(), SparcISA::SparcMicroInst::SparcMicroInst(), and WarnUnimplemented::WarnUnimplemented().

◆ machInst

const ExtMachInst StaticInst::machInst

The binary machine instruction.

Definition at line 231 of file static_inst.hh.

◆ mnemonic

const char* StaticInst::mnemonic

protected

Base mnemonic (e.g., "add").

Used by generateDisassembly() methods. Also useful to readily identify instructions from within the debugger when cachedDisassembly has not been initialized.

Definition at line 246 of file static_inst.hh.

◆ nopStaticInstPtr

StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst

static

Pointer to a statically allocated generic "nop" instruction object.

Definition at line 228 of file static_inst.hh.

Referenced by DefaultFetch< Impl >::finishTranslation().

◆ nullStaticInstPtr

StaticInstPtr StaticInst::nullStaticInstPtr

static

Pointer to a statically allocated "null" instruction object.

Definition at line 225 of file static_inst.hh.

Referenced by ArmISA::AbortFault< DataAbort >::AbortFault(), BaseSimpleCPU::advancePC(), Checker< O3CPUImpl >::advancePC(), ArmISA::ArmFault::ArmFault(), ArmISA::ArmSev::ArmSev(), BPredUnit::BTBLookup(), DefaultCommit< Impl >::commitHead(), SparcISA::FastDataAccessMMUMiss::FastDataAccessMMUMiss(), SparcISA::FastInstructionAccessMMUMiss::FastInstructionAccessMMUMiss(), SparcISA::SparcFaultBase::FaultVals::FaultVals(), SparcISA::FillNNormal::FillNNormal(), GenericAlignmentFault::GenericAlignmentFault(), GenericPageTableFault::GenericPageTableFault(), Checker< O3CPUImpl >::handlePendingInt(), X86ISA::InitInterrupt::InitInterrupt(), X86ISA::InvalidOpcode::InvalidOpcode(), X86ISA::X86FaultBase::isSoft(), UnimpFault::name(), RiscvISA::Reset::name(), X86ISA::PageFault::PageFault(), ArmISA::PCAlignmentFault::PCAlignmentFault(), ReExec::ReExec(), ArmISA::SecureMonitorCall::SecureMonitorCall(), SparcISA::SpillNNormal::SpillNNormal(), X86ISA::StartupInterrupt::StartupInterrupt(), ArmISA::SupervisorCall::SupervisorCall(), SyscallRetryFault::SyscallRetryFault(), SparcISA::TrapInstruction::TrapInstruction(), ArmISA::UndefinedInstruction::UndefinedInstruction(), MipsISA::MipsFaultBase::vect(), Checker< O3CPUImpl >::verify(), X86ISA::X86Abort::X86Abort(), X86ISA::X86Trap::X86Trap(), and TAGEBase::BranchInfo::~BranchInfo().

The documentation for this class was generated from the following files:

cpu/static_inst.hh
cpu/static_inst.cc

Public Types

Public Member Functions

Public Attributes

Static Public Attributes

Protected Member Functions

Protected Attributes

Detailed Description

Member Typedef Documentation

◆ ExtMachInst

Member Enumeration Documentation

◆ anonymous enum

Constructor & Destructor Documentation

◆ StaticInst()

◆ ~StaticInst()

Member Function Documentation

◆ advancePC()

◆ asBytes()

◆ branchTarget() [1/2]

◆ branchTarget() [2/2]

◆ completeAcc()

◆ destRegIdx()

◆ disassemble()

◆ execute()

◆ fetchMicroop()

◆ generateDisassembly()

◆ getName()

◆ hasBranchTarget()

◆ initiateAcc()

◆ isAtomic()

◆ isCall()

◆ isCC()

◆ isCondCtrl()

◆ isCondDelaySlot()

◆ isControl()

◆ isDataPrefetch()

◆ isDelayedCommit()

◆ isDirectCtrl()

◆ isFirstMicroop()

◆ isFloating()

◆ isIndirectCtrl()

◆ isInstPrefetch()

◆ isInteger()

◆ isIprAccess()

◆ isLastMicroop()

◆ isLoad()

◆ isMacroop()

◆ isMemBarrier()

◆ isMemRef()

◆ isMicroBranch()

◆ isMicroop()

◆ isNonSpeculative()

◆ isNop()

◆ isPrefetch()

◆ isQuiesce()

◆ isReturn()

◆ isSerializeAfter()

◆ isSerializeBefore()

◆ isSerializing()

◆ isSquashAfter()

◆ isStore()

◆ isStoreConditional()

◆ isSyscall()

◆ isThreadSync()

◆ isUncondCtrl()

◆ isUnverifiable()

◆ isVector()

◆ isWriteBarrier()

◆ numCCDestRegs()

◆ numDestRegs()

◆ numFPDestRegs()

◆ numIntDestRegs()

◆ numSrcRegs()

◆ numVecDestRegs()

◆ numVecElemDestRegs()

◆ numVecPredDestRegs()

◆ opClass()

◆ printFlags()

◆ setDelayedCommit()

◆ setFirstMicroop()

◆ setFlag()