#include <system.hh>

Inheritance diagram for System:

Classes
class	SystemPort
	Private class for the system port which is only used as a master for debug access and for non-structural entities that do not have a port of their own. More...

Public Types
typedef SystemParams	Params

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

MasterPort &	getSystemPort ()
	Get a reference to the system port that can be used by non-structural simulation objects like processes or threads, or external entities like loaders and debuggers, etc, to access the memory system. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Additional function to return the Port of a memory object. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

ThreadContext *	findFreeContext ()

ThreadContext *	getThreadContext (ContextID tid) const

bool	schedule (PCEvent *event) override

bool	remove (PCEvent *event) override

unsigned	numContexts () const

int	numRunningContexts ()
	Return number of running (non-halted) thread contexts in system. More...

KvmVM *	getKvmVM ()
	Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present. More...

bool	validKvmEnvironment () const
	Verify gem5 configuration will support KVM emulation. More...

PhysicalMemory &	getPhysMem ()
	Get a pointer to access the physical memory of the system. More...

Addr	freeMemSize () const
	Amount of physical memory that is still free. More...

Addr	memSize () const
	Amount of physical memory that exists. More...

bool	isMemAddr (Addr addr) const
	Check if a physical address is within a range of a memory that is part of the global address map. More...

Arch	getArch () const
	Get the architecture. More...

ByteOrder	getGuestByteOrder () const
	Get the guest byte order. More...

Addr	getPageBytes () const
	Get the page bytes for the ISA. More...

Addr	getPageShift () const
	Get the number of bits worth of in-page address for the ISA. More...

ThermalModel *	getThermalModel () const
	The thermal model used for this system (if any). More...

MasterID	getMasterId (const SimObject *master, std::string submaster=std::string())
	Request an id used to create a request object in the system. More...

MasterID	getGlobalMasterId (const std::string &master_name)
	Registers a GLOBAL MasterID, which is a MasterID not related to any particular SimObject; since no SimObject is passed, the master gets registered by providing the full master name. More...

std::string	getMasterName (MasterID master_id)
	Get the name of an object for a given request id. More...

MasterID	lookupMasterId (const SimObject *obj) const
	Looks up the MasterID for a given SimObject returns an invalid MasterID (invldMasterId) if not found. More...

MasterID	lookupMasterId (const std::string &name) const
	Looks up the MasterID for a given object name string returns an invalid MasterID (invldMasterId) if not found. More...

MasterID	maxMasters ()
	Get the number of masters registered in the system. More...

void	regStats () override
	Callback to set stat parameters. More...

uint64_t	incWorkItemsBegin ()
	Called by pseudo_inst to track the number of work items started by this system. More...

uint64_t	incWorkItemsEnd ()
	Called by pseudo_inst to track the number of work items completed by this system. More...

int	markWorkItem (int index)
	Called by pseudo_inst to mark the cpus actively executing work items. More...

void	workItemBegin (uint32_t tid, uint32_t workid)

void	workItemEnd (uint32_t tid, uint32_t workid)

bool	breakpoint ()

	System (Params *p)

	~System ()

const Params *	params () const

const AddrRange &	m5opRange () const
	Range used by memory-mapped m5 pseudo-ops if enabled. More...

Addr	allocPhysPages (int npages)
	Allocate npages contiguous unused physical pages. More...

ContextID	registerThreadContext (ThreadContext *tc, ContextID assigned=InvalidContextID)

void	replaceThreadContext (ThreadContext *tc, ContextID context_id)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

void	drainResume () override
	Resume execution after a successful drain. More...


bool	isAtomicMode () const
	Is the system in atomic mode? More...

bool	isTimingMode () const
	Is the system in timing mode? More...

bool	bypassCaches () const
	Should caches be bypassed? More...


Enums::MemoryMode	getMemoryMode () const
	Get the memory mode of the system. More...

void	setMemoryMode (Enums::MemoryMode mode)
	Change the memory mode of the system. More...

Public Member Functions inherited from SimObject
virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

const Params *	params () const

	SimObject (const Params *_params)

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Static Public Member Functions
static void	printSystems ()

Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Public Attributes
std::vector< ThreadContext * >	threadContexts

const bool	multiThread

Addr	pagePtr

uint64_t	init_param

PortProxy	physProxy
	Port to physical memory used for writing object files into ram at boot. More...

Workload *	workload = nullptr
	OS kernel. More...

std::vector< BaseRemoteGDB * >	remoteGDB

Counter	totalNumInsts

std::map< std::pair< uint32_t, uint32_t >, Tick >	lastWorkItemStarted

std::map< uint32_t, Stats::Histogram * >	workItemStats

FutexMap	futexMap

std::set< int >	PIDs
	Process set to track which PIDs have already been allocated. More...

std::list< BasicSignal >	signalList

std::vector< RedirectPath * >	redirectPaths

Static Public Attributes
static std::vector< System * >	systemList

static int	numSystemsRunning = 0

static const int	maxPID = 32768

Protected Member Functions
std::string	stripSystemName (const std::string &master_name) const
	Strips off the system name from a master name. More...

MasterID	_getMasterId (const SimObject *master, const std::string &master_name)
	helper function for getMasterId More...

std::string	leafMasterName (const SimObject *master, const std::string &submaster)
	Helper function for constructing the full (sub)master name by providing the root master and the relative submaster name. More...

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
KvmVM *const	kvmVM

PhysicalMemory	physmem

Enums::MemoryMode	memoryMode

const unsigned int	_cacheLineSize

uint64_t	workItemsBegin

uint64_t	workItemsEnd

uint32_t	numWorkIds

std::vector< bool >	activeCpus

std::vector< MasterInfo >	masters
	This array is a per-system list of all devices capable of issuing a memory system request and an associated string for each master id. More...

ThermalModel *	thermalModel

Params *	_params

const AddrRange	_m5opRange
	Range for memory-mapped m5 pseudo ops. More...

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Attributes
std::list< PCEvent * >	liveEvents

SystemPort	_systemPort

Detailed Description

Definition at line 72 of file system.hh.

Member Typedef Documentation

◆ Params

typedef SystemParams System::Params

Definition at line 441 of file system.hh.

Constructor & Destructor Documentation

◆ System()

System::System ( Params * p )

Definition at line 85 of file system.cc.

References _cacheLineSize, Request::funcMasterId, getMasterId(), Request::intMasterId, kvmVM, numSystemsRunning, params(), KvmVM::setSystem(), Workload::system, systemList, warn_once, Request::wbMasterId, workload, and RiscvISA::x.

Referenced by getMasterName().

◆ ~System()

System::~System ( )

Definition at line 145 of file system.cc.

References ArmISA::j, numWorkIds, and workItemStats.

Member Function Documentation

◆ _getMasterId()

MasterID System::_getMasterId	(	const SimObject *	master,
		const std::string &	master_name
	)

protected

helper function for getMasterId

Definition at line 499 of file system.cc.

References Stats::enabled(), fatal, ArmISA::i, masters, SimObject::name(), and stripSystemName().

Referenced by getGlobalMasterId(), getMasterId(), and maxMasters().

◆ allocPhysPages()

Addr System::allocPhysPages ( int npages )

Allocate npages contiguous unused physical pages.

Returns: Starting address of first page

Definition at line 323 of file system.cc.

References _m5opRange, AddrRange::contains(), fatal, pagePtr, ArmISA::PageShift, physmem, PhysicalMemory::totalSize(), and warn.

Referenced by Process::allocateMem(), X86ISA::X86_64Process::initState(), m5opRange(), and Process::replicatePage().

◆ breakpoint()

bool System::breakpoint ( )

Definition at line 198 of file system.cc.

References remoteGDB.

◆ bypassCaches()

bool System::bypassCaches ( ) const

inline

Should caches be bypassed?

Some CPUs need to bypass caches to allow direct memory accesses, which is required for hardware virtualization.

Definition at line 152 of file system.hh.

References memoryMode.

Referenced by HDLcd::cmdDisable(), HDLcd::cmdEnable(), HDLcd::drainResume(), CoherentXBar::forwardAtomic(), CoherentXBar::forwardFunctional(), CoherentXBar::forwardTiming(), RubyPort::MemSlavePort::recvAtomic(), RubyPort::PioSlavePort::recvAtomic(), BaseCache::CpuSidePort::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), BaseCache::MemSidePort::recvAtomicSnoop(), BaseCache::CpuSidePort::recvFunctional(), CoherentXBar::recvFunctional(), BaseCache::MemSidePort::recvFunctionalSnoop(), BaseCache::CpuSidePort::recvTimingReq(), CoherentXBar::recvTimingReq(), CoherentXBar::recvTimingResp(), BaseCache::MemSidePort::recvTimingSnoopReq(), BaseCache::CpuSidePort::recvTimingSnoopResp(), DmaReadFifo::resumeFill(), BaseCache::CpuSidePort::tryTiming(), NonCachingSimpleCPU::verifyMemoryMode(), and BaseKvmCPU::verifyMemoryMode().

◆ cacheLineSize()

unsigned int System::cacheLineSize ( ) const

inline

Get the cache line size of the system.

Definition at line 180 of file system.hh.

References _cacheLineSize.

Referenced by DmaDevice::cacheBlockSize(), BaseTrafficGen::createDram(), BaseTrafficGen::createDramRot(), BaseTrafficGen::createLinear(), BaseTrafficGen::createRandom(), DmaPort::dmaAction(), DRAMSim2::init(), MemFootprintProbe::MemFootprintProbe(), ArmISA::ISA::readMiscReg(), and DmaReadFifo::resumeFillFunctional().

◆ drainResume()

void System::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from Drainable.

Definition at line 360 of file system.cc.

References totalNumInsts.

Referenced by m5opRange().

◆ findFreeContext()

ThreadContext * System::findFreeContext ( )

Definition at line 245 of file system.cc.

References ThreadContext::Halted, and threadContexts.

Referenced by cloneFunc().

◆ freeMemSize()

Addr System::freeMemSize ( ) const

Amount of physical memory that is still free.

Definition at line 348 of file system.cc.

References pagePtr, ArmISA::PageShift, physmem, and PhysicalMemory::totalSize().

Referenced by getPhysMem(), and Linux::procMeminfo().

◆ getArch()

Arch System::getArch ( ) const

inline

Get the architecture.

Definition at line 248 of file system.hh.

Referenced by Sequencer::makeRequest().

◆ getGlobalMasterId()

MasterID System::getGlobalMasterId ( const std::string & master_name )

Registers a GLOBAL MasterID, which is a MasterID not related to any particular SimObject; since no SimObject is passed, the master gets registered by providing the full master name.

Parameters

masterName full name of the master

Returns: the master's ID.

Definition at line 486 of file system.cc.

References _getMasterId().

◆ getGuestByteOrder()

ByteOrder System::getGuestByteOrder ( ) const

inline

Get the guest byte order.

Definition at line 254 of file system.hh.

References ArmISA::GuestByteOrder, and panic.

Referenced by _llseekFunc(), dumpDmesgEntry(), and rmdirFunc().

◆ getKvmVM()

KvmVM* System::getKvmVM ( )

inline

Get a pointer to the Kernel Virtual Machine (KVM) SimObject, if present.

Definition at line 220 of file system.hh.

References kvmVM, and validKvmEnvironment().

Referenced by MuxingKvmGic::MuxingKvmGic().

◆ getMasterId()

MasterID System::getMasterId	(	const SimObject *	master,
		std::string	submaster = `std::string()`
	)

Request an id used to create a request object in the system.

All objects that intend to issues requests into the memory system must request an id in the init() phase of startup. All master ids must be fixed by the regStats() phase that immediately precedes it. This allows objects in the memory system to understand how many masters may exist and appropriately name the bins of their per-master stats before the stats are finalized.

Registers a MasterID: This method takes two parameters, one of which is optional. The first one is the master object, and it is compulsory; in case a object has multiple (sub)masters, a second parameter must be provided and it contains the name of the submaster. The method will create a master's name by concatenating the SimObject name with the eventual submaster string, separated by a dot.

As an example: For a cpu having two masters: a data master and an instruction master, the method must be called twice:

instMasterId = getMasterId(cpu, "inst"); dataMasterId = getMasterId(cpu, "data");

and the masters' names will be:

"cpu.inst"
"cpu.data"

Parameters

master	SimObject related to the master
submaster	String containing the submaster's name

Returns: the master's ID.

Definition at line 492 of file system.cc.

References _getMasterId(), and leafMasterName().

Referenced by BaseTrafficGen::BaseTrafficGen(), and System().

◆ getMasterName()

std::string System::getMasterName ( MasterID master_id )

Get the name of an object for a given request id.

Definition at line 541 of file system.cc.

References fatal, masters, and System().

Referenced by QoS::MemCtrl::addMaster(), AbstractMemory::checkLockedAddrList(), QoS::MemSinkCtrl::processNextReqEvent(), QoS::MemCtrl::qosSchedule(), QoS::MemSinkCtrl::recvTimingReq(), BaseTags::BaseTagStats::regStats(), QoS::MemCtrl::MemCtrlStats::regStats(), AbstractMemory::MemStats::regStats(), BaseCache::CacheStats::regStats(), DRAMCtrl::DRAMStats::regStats(), BaseCache::CacheCmdStats::regStatsFromParent(), QoS::FixedPriorityPolicy::schedule(), and MemTraceProbe::startup().

◆ getMemoryMode()

Enums::MemoryMode System::getMemoryMode ( ) const

inline

Get the memory mode of the system.

This should only be used by the Python world. The C++ world should use one of the query functions above (isAtomicMode(), isTimingMode(), bypassCaches()).

Definition at line 165 of file system.hh.

References memoryMode, ArmISA::mode, and setMemoryMode().

Referenced by MinorCPU::init().

◆ getPageBytes()

Addr System::getPageBytes ( ) const

inline

Get the page bytes for the ISA.

Definition at line 266 of file system.hh.

References ArmISA::PageBytes.

Referenced by GenericTimerFrame::GenericTimerFrame(), IdeController::IdeController(), mmapFunc(), mremapFunc(), and munmapFunc().

◆ getPageShift()

Addr System::getPageShift ( ) const

inline

Get the number of bits worth of in-page address for the ISA.

Definition at line 271 of file system.hh.

References ArmISA::PageShift.

◆ getPhysMem()

PhysicalMemory& System::getPhysMem ( )

inline

Get a pointer to access the physical memory of the system.

Definition at line 228 of file system.hh.

References addr, freeMemSize(), isMemAddr(), memSize(), and physmem.

Referenced by KvmVM::delayedStartup(), ArmSemihosting::gatherHeapInfo(), ArmISA::FsLinux::initState(), and NonCachingSimpleCPU::sendPacket().

◆ getPort()

Port & System::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Additional function to return the Port of a memory object.

Reimplemented from SimObject.

Definition at line 185 of file system.cc.

References _systemPort.

Referenced by getSystemPort().

◆ getSystemPort()

MasterPort& System::getSystemPort ( )

inline

Get a reference to the system port that can be used by non-structural simulation objects like processes or threads, or external entities like loaders and debuggers, etc, to access the memory system.

Returns: a reference to the system port we own

Definition at line 113 of file system.hh.

References _systemPort, getPort(), and InvalidPortID.

◆ getThermalModel()

ThermalModel* System::getThermalModel ( ) const

inline

The thermal model used for this system (if any).

Definition at line 276 of file system.hh.

References thermalModel.

◆ getThreadContext()

ThreadContext* System::getThreadContext ( ContextID tid ) const

inline

Definition at line 186 of file system.hh.

Referenced by MipsProcess::argsInit(), RiscvProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), ArmProcess64::armHwcapImpl(), Gicv3CPUInterface::assertWakeRequest(), ArmISA::TLBIOp::broadcast(), AbstractMemory::checkLockedAddrList(), IntrControl::clear(), IntrControl::clearAll(), KvmVM::contextIdToVCpuId(), GenericTimer::createTimers(), Gicv3CPUInterface::deassertWakeRequest(), ArmISA::FsLinux::dumpDmesg(), MemState::fixupFault(), Gicv3Redistributor::getAffinity(), IntrControl::havePosted(), CpuLocalTimer::init(), SparcProcess::initState(), Process::initState(), ArmProcess32::initState(), ArmLinuxProcess32::initState(), RiscvProcess64::initState(), RiscvProcess32::initState(), ArmProcess64::initState(), X86ISA::X86_64Process::initState(), Sparc32Process::initState(), X86ISA::I386Process::initState(), Sparc64Process::initState(), Prefetcher::Queued::insert(), IntrControl::post(), Gicv3::postInt(), DistIface::SyncEvent::process(), HSAPacketProcessor::processPkt(), GenericTimer::setMiscReg(), X86ISA::I82094AA::signalInterrupt(), DistIface::toggleSync(), HSADevice::translateOrDie(), and HSAPacketProcessor::translateOrDie().

◆ incWorkItemsBegin()

uint64_t System::incWorkItemsBegin ( )

inline

Called by pseudo_inst to track the number of work items started by this system.

Definition at line 395 of file system.hh.

References workItemsBegin.

Referenced by PseudoInst::workbegin().

◆ incWorkItemsEnd()

uint64_t System::incWorkItemsEnd ( )

inline

Called by pseudo_inst to track the number of work items completed by this system.

Definition at line 405 of file system.hh.

References workItemsEnd.

Referenced by PseudoInst::workend().

◆ init()

void System::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from SimObject.

Definition at line 152 of file system.cc.

References _systemPort, Port::isConnected(), SimObject::name(), and panic.

◆ isAtomicMode()

bool System::isAtomicMode ( ) const

inline

Is the system in atomic mode?

There are currently two different atomic memory modes: 'atomic', which supports caches; and 'atomic_noncaching', which bypasses caches. The latter is used by hardware virtualized CPUs. SimObjects are expected to use Port::sendAtomic() and Port::recvAtomic() when accessing memory in this mode.

Definition at line 131 of file system.hh.

References ArmISA::atomic, and memoryMode.

Referenced by sc_gem5::TlmToGem5Bridge< BITWIDTH >::before_end_of_elaboration(), SMMUTranslationProcess::completeTransaction(), SMMUv3::processCommands(), SMMUv3::runProcess(), Gicv3Its::runProcess(), DmaPort::sendDma(), NonCachingSimpleCPU::verifyMemoryMode(), and AtomicSimpleCPU::verifyMemoryMode().

◆ isMemAddr()

bool System::isMemAddr ( Addr addr ) const

Check if a physical address is within a range of a memory that is part of the global address map.

Parameters

addr	A physical address

Returns: Whether the address corresponds to a memory

Definition at line 354 of file system.cc.

References PhysicalMemory::isMemAddr(), and physmem.

Referenced by getPhysMem(), MemFootprintProbe::handleRequest(), KernelWorkload::initState(), RubyPort::MemSlavePort::isPhysMemAddress(), RubyPort::ruby_hit_callback(), NonCachingSimpleCPU::sendPacket(), and BaseTrafficGen::update().

◆ isTimingMode()

bool System::isTimingMode ( ) const

inline

Is the system in timing mode?

SimObjects are expected to use Port::sendTiming() and Port::recvTiming() when accessing memory in this mode.

Definition at line 142 of file system.hh.

References memoryMode.

Referenced by sc_gem5::TlmToGem5Bridge< BITWIDTH >::before_end_of_elaboration(), SMMUTranslationProcess::completeTransaction(), SMMUProcess::doDelay(), MinorCPU::drainResume(), DRAMCtrl::drainResume(), TrafficGen::initState(), SMMUTranslationProcess::issuePrefetch(), SMMUv3::processCommands(), SMMUTranslationProcess::resumeTransaction(), SMMUv3::runProcess(), Gicv3Its::runProcess(), DmaPort::sendDma(), X86ISA::I82094AA::signalInterrupt(), RiscvISA::Walker::start(), X86ISA::Walker::start(), DRAMCtrl::startup(), TimingSimpleCPU::verifyMemoryMode(), and FullO3CPU< O3CPUImpl >::verifyMemoryMode().

◆ leafMasterName()

std::string System::leafMasterName	(	const SimObject *	master,
		const std::string &	submaster
	)

protected

Helper function for constructing the full (sub)master name by providing the root master and the relative submaster name.

Definition at line 529 of file system.cc.

References SimObject::name().

Referenced by getMasterId(), and maxMasters().

◆ lookupMasterId() [1/2]

MasterID System::lookupMasterId ( const SimObject * obj ) const

Looks up the MasterID for a given SimObject returns an invalid MasterID (invldMasterId) if not found.

Definition at line 449 of file system.cc.

References fatal_if, ArmISA::i, ArmISA::id, Request::invldMasterId, and masters.

Referenced by QoS::PropFairPolicy::initMaster(), and QoS::Policy::pair().

◆ lookupMasterId() [2/2]

MasterID System::lookupMasterId ( const std::string & name ) const

Looks up the MasterID for a given object name string returns an invalid MasterID (invldMasterId) if not found.

Definition at line 472 of file system.cc.

References ArmISA::i, Request::invldMasterId, masters, SimObject::name(), and stripSystemName().

◆ m5opRange()

const AddrRange& System::m5opRange ( ) const

inline

Range used by memory-mapped m5 pseudo-ops if enabled.

Returns an invalid/empty range if disabled.

Definition at line 462 of file system.hh.

References _m5opRange, allocPhysPages(), drainResume(), InvalidContextID, registerThreadContext(), replaceThreadContext(), serialize(), and unserialize().

Referenced by ArmISA::TLB::TLB().

◆ markWorkItem()

int System::markWorkItem ( int index )

inline

Called by pseudo_inst to mark the cpus actively executing work items.

Returns the total number of cpus that have executed work item begin or ends.

Definition at line 416 of file system.hh.

References X86ISA::count, ArmISA::i, and MipsISA::index.

Referenced by PseudoInst::workbegin(), and PseudoInst::workend().

◆ maxMasters()

MasterID System::maxMasters ( )

inline

Get the number of masters registered in the system.

Definition at line 373 of file system.hh.

References _getMasterId(), leafMasterName(), and regStats().

Referenced by BaseCache::getNextQueueEntry(), BaseCache::handleTimingReqMiss(), BaseCache::incHitCount(), BaseCache::incMissCount(), BaseCache::recvTimingResp(), BaseTags::BaseTagStats::regStats(), QoS::MemCtrl::MemCtrlStats::regStats(), AbstractMemory::MemStats::regStats(), BaseCache::CacheStats::regStats(), DRAMCtrl::DRAMStats::regStats(), BaseCache::CacheCmdStats::regStatsFromParent(), NoncoherentCache::serviceMSHRTargets(), Cache::serviceMSHRTargets(), and MemTraceProbe::startup().

◆ memSize()

Addr System::memSize ( ) const

Amount of physical memory that exists.

Definition at line 342 of file system.cc.

References physmem, and PhysicalMemory::totalSize().

Referenced by getPhysMem(), and Linux::procMeminfo().

◆ numContexts()

unsigned System::numContexts ( ) const

inline

Definition at line 198 of file system.hh.

References numRunningContexts().

Referenced by ArmISA::TLBIOp::broadcast(), MuxingKvmGic::clearBankedDistRange(), MuxingKvmGic::copyBankedDistRange(), MuxingKvmGic::copyGicState(), Linux::cpuOnline(), exitImpl(), MuxingKvmGic::fromKvmToGicV2(), Iob::generateIpi(), Gicv3CPUInterface::generateSGI(), GicV2::genSwiMask(), getrlimitFunc(), FVPBasePwrCtrl::init(), Gicv3::init(), CpuLocalTimer::init(), DistIface::SyncEvent::process(), A9SCU::read(), Gicv3Redistributor::read(), SparcISA::ISA::readFSReg(), ArmISA::ISA::readMiscReg(), Gicv3Distributor::route(), CpuLocalTimer::serialize(), setpgidFunc(), X86ISA::I82094AA::signalInterrupt(), GicV2::softInt(), tgkillFunc(), DistIface::toggleSync(), CpuLocalTimer::unserialize(), Gicv3Distributor::update(), GicV2::updateIntState(), GicV2::updateRunPri(), and PseudoInst::wakeCPU().

◆ numRunningContexts()

int System::numRunningContexts ( )

Return number of running (non-halted) thread contexts in system.

These threads could be Active or Suspended.

Definition at line 275 of file system.cc.

References ThreadContext::Halted, ThreadContext::Halting, and threadContexts.

Referenced by numContexts(), GicV2::readCpu(), GicV2::readDistributor(), VGic::updateIntState(), GicV2::updateIntState(), and VGic::VGic().

◆ params()

const Params* System::params ( ) const

inline

Definition at line 456 of file system.hh.

References _params.

Referenced by PseudoInst::loadsymbol(), PseudoInst::readfile(), System(), PseudoInst::workbegin(), and PseudoInst::workend().

◆ printSystems()

void System::printSystems ( )

static

Definition at line 418 of file system.cc.

References ArmISA::i, SimObject::name(), and systemList.

Referenced by printSystems().

◆ registerThreadContext()

ContextID System::registerThreadContext	(	ThreadContext *	tc,
		ContextID	assigned = `InvalidContextID`
	)

Definition at line 206 of file system.cc.

References activeCpus, ArmISA::e, fatal_if, getRemoteGDBPort(), ArmISA::id, InvalidContextID, liveEvents, remoteGDB, PCEventScope::schedule(), and threadContexts.

Referenced by m5opRange(), and BaseCPU::registerThreadContexts().

◆ regStats()

void System::regStats ( )

overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from Stats::Group.

Definition at line 385 of file system.cc.

References ccprintf(), ArmISA::j, SimObject::name(), numWorkIds, Stats::Group::regStats(), and workItemStats.

Referenced by maxMasters().

◆ remove()

bool System::remove ( PCEvent * event )

overridevirtual

Implements PCEventScope.

Definition at line 265 of file system.cc.

References liveEvents, and threadContexts.

◆ replaceThreadContext()

void System::replaceThreadContext	(	ThreadContext *	tc,
		ContextID	context_id
	)

Definition at line 288 of file system.cc.

References ArmISA::e, liveEvents, panic, remoteGDB, PCEventScope::schedule(), and threadContexts.

Referenced by m5opRange(), and BaseCPU::takeOverFrom().

◆ schedule()

bool System::schedule ( PCEvent * event )

overridevirtual

Implements PCEventScope.

Definition at line 255 of file system.cc.

References liveEvents, and threadContexts.

◆ serialize()

void System::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from SimObject.

Definition at line 366 of file system.cc.

References pagePtr, physmem, SERIALIZE_SCALAR, and Serializable::serializeSection().

Referenced by m5opRange().

◆ setMemoryMode()

void System::setMemoryMode ( Enums::MemoryMode mode )

Change the memory mode of the system.

This should only be called by the Python!

Parameters

mode	Mode to change to (atomic/timing/...)

Definition at line 192 of file system.cc.

References Drained, Drainable::drainState(), memoryMode, and ArmISA::mode.

Referenced by getMemoryMode().

◆ startup()

void System::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from SimObject.

Definition at line 160 of file system.cc.

References ArmISA::id, inform, remoteGDB, SimObject::startup(), and threadContexts.