#include <cpu.hh>

Inheritance diagram for CheckerCPU:

Public Types
typedef CheckerCPUParams	Params

Public Types inherited from BaseCPU
typedef BaseCPUParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Types inherited from ExecContext
typedef TheISA::PCState	PCState

using	VecRegContainer = TheISA::VecRegContainer

using	VecElem = TheISA::VecElem

using	VecPredRegContainer = TheISA::VecPredRegContainer

Public Member Functions
void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

	CheckerCPU (Params *p)

virtual	~CheckerCPU ()

void	setSystem (System *system)

void	setIcachePort (MasterPort *icache_port)

void	setDcachePort (MasterPort *dcache_port)

Port &	getDataPort () override
	Purely virtual method that returns a reference to the data port. More...

Port &	getInstPort () override
	Purely virtual method that returns a reference to the instruction port. More...

BaseTLB *	getITBPtr ()

BaseTLB *	getDTBPtr ()

virtual Counter	totalInsts () const override

virtual Counter	totalOps () const override

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

RegVal	readIntRegOperand (const StaticInst *si, int idx) override
	Reads an integer register. More...

RegVal	readFloatRegOperandBits (const StaticInst *si, int idx) override
	Reads a floating point register in its binary format, instead of by value. More...

const VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const override
	Read source vector register operand. More...

VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx) override
	Read destination vector register operand for modification. More...

VecElem	readVecElemOperand (const StaticInst *si, int idx) const override
	Vector Elem Interfaces. More...

const VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const override
	Predicate registers interface. More...

VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx) override
	Gets destination predicate register operand for modification. More...

RegVal	readCCRegOperand (const StaticInst *si, int idx) override

template<typename T >
void	setScalarResult (T &&t)

template<typename T >
void	setVecResult (T &&t)

template<typename T >
void	setVecElemResult (T &&t)

template<typename T >
void	setVecPredResult (T &&t)

void	setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
	Sets an integer register to a value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
	Sets the bits of a floating point register of single width to a binary value. More...

void	setCCRegOperand (const StaticInst *si, int idx, RegVal val) override

void	setVecRegOperand (const StaticInst *si, int idx, const VecRegContainer &val) override
	Sets a destination vector register operand to a value. More...

void	setVecElemOperand (const StaticInst *si, int idx, const VecElem val) override
	Sets a vector register to a value. More...

void	setVecPredRegOperand (const StaticInst *si, int idx, const VecPredRegContainer &val) override
	Sets a destination predicate register operand to a value. More...

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

TheISA::PCState	pcState () const override

void	pcState (const TheISA::PCState &val) override

Addr	instAddr ()

Addr	nextInstAddr ()

MicroPC	microPC ()

RegVal	readMiscRegNoEffect (int misc_reg) const

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

void	setMiscRegNoEffect (int misc_reg, RegVal val)

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

void	recordPCChange (const TheISA::PCState &val)

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override

void	demapInstPage (Addr vaddr, uint64_t asn)

void	demapDataPage (Addr vaddr, uint64_t asn)

RequestPtr	genMemFragmentRequest (Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
	Helper function used to generate the request for a single fragment of a memory access. More...

Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...

void	wakeup (ThreadID tid) override

void	syscall (Fault *fault) override
	Executes a syscall. More...

void	handleError ()

bool	checkFlags (const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)
	Checks if the flags set by the Checker and Checkee match. More...

void	dumpAndExit ()

ThreadContext *	tcBase () const override
	Returns a pointer to the ThreadContext. More...

SimpleThread *	threadBase ()


virtual ConstVecLane8	readVec8BitLaneOperand (const StaticInst *si, int idx) const override
	Vector Register Lane Interfaces. More...

virtual ConstVecLane16	readVec16BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 16bit operand. More...

virtual ConstVecLane32	readVec32BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 32bit operand. More...

virtual ConstVecLane64	readVec64BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 64bit operand. More...

template<typename LD >
void	setVecLaneOperandT (const StaticInst *si, int idx, const LD &val)
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override

Public Member Functions inherited from BaseCPU
virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

MasterID	dataMasterId () const
	Reads this CPU's unique data requestor ID. More...

MasterID	instMasterId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadContext *tc) const

void	processProfileEvent ()

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	startup () override
	startup() is the final initialization call before simulation. More...

void	regStats () override
	Callback to set stat parameters. More...

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread. More...

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from SimObject
virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

const Params *	params () const

	SimObject (const Params *_params)

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Member Functions inherited from ExecContext
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
	Initiate a timing memory read operation. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >())=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

Public Attributes
SimpleThread *	thread

Counter	numLoad

Counter	startNumLoad

InstResult	unverifiedResult

RequestPtr	unverifiedReq

uint8_t *	unverifiedMemData

bool	changedPC

bool	willChangePC

TheISA::PCState	newPCState

bool	exitOnError

bool	updateOnError

bool	warnOnlyOnLoadError

InstSeqNum	youngestSN

Public Attributes inherited from BaseCPU
TheISA::MicrocodeRom	microcodeRom

EventFunctionWrapper *	profileEvent

ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Public Attributes inherited from ClockedObject
PowerState *	powerState

Protected Types
typedef TheISA::MachInst	MachInst

using	VecRegContainer = TheISA::VecRegContainer

Protected Types inherited from BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Attributes
MasterID	masterId
	id attached to all issued requests More...

std::vector< Process * >	workload

System *	systemPtr

MasterPort *	icachePort

MasterPort *	dcachePort

ThreadContext *	tc

BaseTLB *	itb

BaseTLB *	dtb

std::queue< InstResult >	result

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Counter	numInst

Counter	startNumInst

std::queue< int >	miscRegIdxs

Protected Attributes inherited from BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

MasterID	_instMasterId
	instruction side request id that must be placed in all requests More...

MasterID	_dataMasterId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Member Functions inherited from BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Detailed Description

CheckerCPU class.

Dynamically verifies instructions as they are completed by making sure that the instruction and its results match the independent execution of the benchmark inside the checker. The checker verifies instructions in order, regardless of the order in which instructions complete. There are certain results that can not be verified, specifically the result of a store conditional or the values of uncached accesses. In these cases, and with instructions marked as "IsUnverifiable", the checker assumes that the value from the main CPU's execution is correct and simply copies that value. It provides a CheckerThreadContext (see checker/thread_context.hh) that provides hooks for updating the Checker's state through any ThreadContext accesses. This allows the checker to be able to correctly verify instructions, even with external accesses to the ThreadContext that change state.

Definition at line 85 of file cpu.hh.

Member Typedef Documentation

◆ MachInst

typedef TheISA::MachInst CheckerCPU::MachInst

protected

Definition at line 88 of file cpu.hh.

◆ Params

typedef CheckerCPUParams CheckerCPU::Params

Definition at line 96 of file cpu.hh.

◆ VecRegContainer

using CheckerCPU::VecRegContainer = TheISA::VecRegContainer

protected

Definition at line 89 of file cpu.hh.

Constructor & Destructor Documentation

◆ CheckerCPU()

CheckerCPU::CheckerCPU ( Params * p )

Definition at line 64 of file cpu.cc.

References changedPC, curMacroStaticInst, curStaticInst, dtb, exitOnError, itb, numInst, numLoad, startNumInst, startNumLoad, updateOnError, warnOnlyOnLoadError, willChangePC, workload, and youngestSN.

◆ ~CheckerCPU()

CheckerCPU::~CheckerCPU ( )

virtual

Definition at line 90 of file cpu.cc.

Member Function Documentation

◆ amoMem()

Fault CheckerCPU::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverride

Definition at line 563 of file cpu.hh.

References panic.

◆ armMonitor()

void CheckerCPU::armMonitor ( Addr address )

inlineoverridevirtual

Implements ExecContext.

Definition at line 513 of file cpu.hh.

References BaseCPU::armMonitor().

◆ checkFlags()

bool CheckerCPU::checkFlags	(	const RequestPtr &	unverified_req,
		Addr	vAddr,
		Addr	pAddr,
		int	flags
	)

Checks if the flags set by the Checker and Checkee match.

Definition at line 362 of file cpu.cc.

Referenced by handleError(), readMem(), and writeMem().

◆ demapDataPage()

void CheckerCPU::demapDataPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 527 of file cpu.hh.

References addr, data, BaseTLB::demapPage(), genMemFragmentRequest(), readMem(), and writeMem().

◆ demapInstPage()

void CheckerCPU::demapInstPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 521 of file cpu.hh.

References BaseTLB::demapPage().

◆ demapPage()

void CheckerCPU::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 506 of file cpu.hh.

References BaseTLB::demapPage().

◆ dumpAndExit()

void CheckerCPU::dumpAndExit ( )

Definition at line 379 of file cpu.cc.

References curTick(), panic, SimpleThread::pcState(), thread, and warn.

Referenced by Checker< O3CPUImpl >::dumpAndExit(), handleError(), and Checker< O3CPUImpl >::handleError().

◆ genMemFragmentRequest()

RequestPtr CheckerCPU::genMemFragmentRequest	(	Addr	frag_addr,
		int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable,
		int &	frag_size,
		int &	size_left
	)		const

Helper function used to generate the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters

	frag_addr	Start address of the fragment.
	size	Total size of the memory access in bytes.
	flags	Request flags.
	byte_enable	Byte-enable mask for the entire memory access.
[out]	frag_size	Fragment size.
[in,out]	size_left	Size left to be processed in the memory access.

Returns: Pointer to the allocated Request, nullptr if the byte-enable mask is all-false for the fragment.

Definition at line 140 of file cpu.cc.

References addrBlockOffset(), BaseCPU::cacheLineSize(), ThreadContext::contextId(), isAnyActiveElement(), masterId, SimpleThread::pcState(), tc, and thread.

Referenced by demapDataPage(), readMem(), and writeMem().

◆ getAddrMonitor()

AddressMonitor* CheckerCPU::getAddrMonitor ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 517 of file cpu.hh.

References BaseCPU::getCpuAddrMonitor().

◆ getDataPort()

Port& CheckerCPU::getDataPort ( )

inlineoverridevirtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns: a reference to the data port

Implements BaseCPU.

Definition at line 107 of file cpu.hh.

References dcachePort.

◆ getDTBPtr()

BaseTLB* CheckerCPU::getDTBPtr ( )

inline

Definition at line 157 of file cpu.hh.

References dtb.

Referenced by BaseCPU::takeOverFrom().

◆ getInstPort()

Port& CheckerCPU::getInstPort ( )

inlineoverridevirtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns: a reference to the instruction port

Implements BaseCPU.

Definition at line 116 of file cpu.hh.

References icachePort.

◆ getITBPtr()

BaseTLB* CheckerCPU::getITBPtr ( )

inline

Definition at line 156 of file cpu.hh.

References itb.

Referenced by BaseCPU::takeOverFrom().

◆ getWritableVecPredRegOperand()

VecPredRegContainer& CheckerCPU::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements ExecContext.

Definition at line 314 of file cpu.hh.

References StaticInst::destRegIdx(), SimpleThread::getWritableVecPredReg(), RegId::isVecPredReg(), and X86ISA::reg.

◆ getWritableVecRegOperand()

VecRegContainer& CheckerCPU::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Read destination vector register operand for modification.

Implements ExecContext.

Definition at line 218 of file cpu.hh.

References StaticInst::destRegIdx(), SimpleThread::getWritableVecReg(), RegId::isVecReg(), and X86ISA::reg.

◆ handleError()

void CheckerCPU::handleError ( )

inline

Definition at line 583 of file cpu.hh.

References checkFlags(), dumpAndExit(), and exitOnError.

Referenced by readMem(), Checker< O3CPUImpl >::verify(), and writeMem().

◆ init()

void CheckerCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from BaseCPU.

Definition at line 59 of file cpu.cc.

◆ instAddr()

Addr CheckerCPU::instAddr ( )

inline

Definition at line 445 of file cpu.hh.

References SimpleThread::instAddr().

◆ microPC()

MicroPC CheckerCPU::microPC ( )

inline

Definition at line 447 of file cpu.hh.

References SimpleThread::microPC().

◆ mwait()

bool CheckerCPU::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements ExecContext.

Definition at line 514 of file cpu.hh.

References BaseCPU::mwait().

◆ mwaitAtomic()

void CheckerCPU::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements ExecContext.

Definition at line 515 of file cpu.hh.

References SimpleThread::dtb, and BaseCPU::mwaitAtomic().

◆ nextInstAddr()

Addr CheckerCPU::nextInstAddr ( )

inline

Definition at line 446 of file cpu.hh.

References SimpleThread::nextInstAddr().

◆ pcState() [1/2]

TheISA::PCState CheckerCPU::pcState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 437 of file cpu.hh.

References SimpleThread::pcState().

Referenced by Checker< O3CPUImpl >::advancePC(), Checker< O3CPUImpl >::handlePendingInt(), and Checker< O3CPUImpl >::verify().

◆ pcState() [2/2]

void CheckerCPU::pcState ( const TheISA::PCState & val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 439 of file cpu.hh.

References DPRINTF, and SimpleThread::pcState().

◆ readCCRegOperand()

RegVal CheckerCPU::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 322 of file cpu.hh.

References RegId::index(), RegId::isCCReg(), SimpleThread::readCCReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readFloatRegOperandBits()

RegVal CheckerCPU::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 196 of file cpu.hh.

References RegId::index(), RegId::isFloatReg(), SimpleThread::readFloatReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readIntRegOperand()

RegVal CheckerCPU::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 188 of file cpu.hh.

References RegId::index(), RegId::isIntReg(), SimpleThread::readIntReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readMem()

Fault CheckerCPU::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

override

Definition at line 173 of file cpu.cc.

References addr, checkFlags(), Packet::createRead(), curTick(), Packet::dataStatic(), dcachePort, dtb, genMemFragmentRequest(), handleError(), Request::NO_ACCESS, NoFault, BaseTLB::Read, MasterPort::sendFunctional(), tc, BaseTLB::translateFunctional(), unverifiedMemData, unverifiedReq, and warn.

Referenced by demapDataPage().

◆ readMemAccPredicate()

bool CheckerCPU::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 426 of file cpu.hh.

References SimpleThread::readMemAccPredicate().

◆ readMiscReg()

RegVal CheckerCPU::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 457 of file cpu.hh.

References SimpleThread::readMiscReg().

◆ readMiscRegNoEffect()

RegVal CheckerCPU::readMiscRegNoEffect ( int misc_reg ) const

inline

Definition at line 451 of file cpu.hh.

References SimpleThread::readMiscRegNoEffect().

◆ readMiscRegOperand()

RegVal CheckerCPU::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 481 of file cpu.hh.

References RegId::index(), RegId::isMiscReg(), SimpleThread::readMiscReg(), X86ISA::reg, and StaticInst::srcRegIdx().

virtual ConstVecLane8 CheckerCPU::readVec8BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Vector Register Lane Interfaces.

Reads source vector 8bit operand.

Implements ExecContext.

Definition at line 229 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::isVecReg(), SimpleThread::readVec8BitLaneReg(), and X86ISA::reg.

◆ readVecElemOperand()

VecElem CheckerCPU::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implements ExecContext.

Definition at line 299 of file cpu.hh.

References SimpleThread::readVecElem(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readVecPredRegOperand()

const VecPredRegContainer& CheckerCPU::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements ExecContext.

Definition at line 306 of file cpu.hh.

References RegId::isVecPredReg(), SimpleThread::readVecPredReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readVecRegOperand()

const VecRegContainer& CheckerCPU::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Read source vector register operand.

Implements ExecContext.

Definition at line 207 of file cpu.hh.

References RegId::isVecReg(), SimpleThread::readVecReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ recordPCChange()

void CheckerCPU::recordPCChange ( const TheISA::PCState & val )

inline

Definition at line 499 of file cpu.hh.

References changedPC, newPCState, and X86ISA::val.

Referenced by CheckerThreadContext< TC >::pcState().

◆ serialize()

void CheckerCPU::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize this object to the given output stream.

Note: CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The stream to serialize to.

Reimplemented from BaseCPU.

Definition at line 130 of file cpu.cc.

◆ setCCRegOperand()

void CheckerCPU::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 380 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isCCReg(), X86ISA::reg, SimpleThread::setCCReg(), setScalarResult(), and X86ISA::val.

◆ setDcachePort()

void CheckerCPU::setDcachePort ( MasterPort * dcache_port )

Definition at line 124 of file cpu.cc.

References dcachePort.

◆ setFloatRegOperandBits()

void CheckerCPU::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 371 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isFloatReg(), X86ISA::reg, SimpleThread::setFloatReg(), setScalarResult(), and X86ISA::val.

◆ setIcachePort()

void CheckerCPU::setIcachePort ( MasterPort * icache_port )

Definition at line 118 of file cpu.cc.

References icachePort.

◆ setIntRegOperand()

void CheckerCPU::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 362 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isIntReg(), X86ISA::reg, SimpleThread::setIntReg(), setScalarResult(), and X86ISA::val.

◆ setMemAccPredicate()

void CheckerCPU::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 432 of file cpu.hh.

References SimpleThread::setMemAccPredicate().

◆ setMiscReg()

void CheckerCPU::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 472 of file cpu.hh.

References DPRINTF, and SimpleThread::setMiscReg().

Referenced by setMiscRegOperand().

◆ setMiscRegNoEffect()

void CheckerCPU::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val
	)

inline

Definition at line 463 of file cpu.hh.

References DPRINTF, and SimpleThread::setMiscRegNoEffect().

◆ setMiscRegOperand()

void CheckerCPU::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 489 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isMiscReg(), X86ISA::reg, setMiscReg(), and X86ISA::val.

◆ setPredicate()

void CheckerCPU::setPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 420 of file cpu.hh.

References SimpleThread::setPredicate().

◆ setScalarResult()

template<typename T >

void CheckerCPU::setScalarResult ( T && t )

inline

Definition at line 331 of file cpu.hh.

References InstResult::Scalar, and ArmISA::t.

Referenced by setCCRegOperand(), setFloatRegOperandBits(), and setIntRegOperand().

◆ setStCondFailures()

void CheckerCPU::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 574 of file cpu.hh.

◆ setSystem()

void CheckerCPU::setSystem ( System * system )

Definition at line 95 of file cpu.cc.

References SimObject::_params, dtb, FullSystem, SimpleThread::getTC(), itb, ThreadState::kernelStats, MipsISA::p, BaseCPU::system, systemPtr, tc, thread, BaseCPU::threadContexts, and workload.

Referenced by BaseSimpleCPU::BaseSimpleCPU().

◆ setVecElemOperand()

void CheckerCPU::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const VecElem	val
	)

inlineoverridevirtual

Sets a vector register to a value.

Implements ExecContext.

Definition at line 399 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::isVecElem(), X86ISA::reg, SimpleThread::setVecElem(), and setVecElemResult().

◆ setVecElemResult()

template<typename T >

void CheckerCPU::setVecElemResult ( T && t )

inline

Definition at line 347 of file cpu.hh.

References ArmISA::t, and InstResult::VecElem.

Referenced by setVecElemOperand().

◆ setVecLaneOperand() [1/4]

virtual void CheckerCPU::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::Byte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 273 of file cpu.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [2/4]

virtual void CheckerCPU::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::TwoByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 279 of file cpu.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [3/4]

virtual void CheckerCPU::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::FourByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 285 of file cpu.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [4/4]

virtual void CheckerCPU::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::EightByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 291 of file cpu.hh.

References setVecLaneOperandT().

◆ setVecLaneOperandT()

template<typename LD >

void CheckerCPU::setVecLaneOperandT	(	const StaticInst *	si,
		int	idx,
		const LD &	val
	)

inline

Write a lane of the destination vector operand.

Definition at line 266 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::isVecReg(), X86ISA::reg, and SimpleThread::setVecLane().

Referenced by setVecLaneOperand().

◆ setVecPredRegOperand()

void CheckerCPU::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecPredRegContainer &	val
	)

inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements ExecContext.

Definition at line 408 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::isVecPredReg(), X86ISA::reg, SimpleThread::setVecPredReg(), and setVecPredResult().

◆ setVecPredResult()

template<typename T >

void CheckerCPU::setVecPredResult ( T && t )

inline

Definition at line 355 of file cpu.hh.

References ArmISA::t, and InstResult::VecPredReg.

Referenced by setVecPredRegOperand().

◆ setVecRegOperand()

void CheckerCPU::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecRegContainer &	val
	)

inlineoverridevirtual

Sets a destination vector register operand to a value.

Implements ExecContext.

Definition at line 389 of file cpu.hh.

References StaticInst::destRegIdx(), RegId::isVecReg(), X86ISA::reg, SimpleThread::setVecReg(), and setVecResult().

◆ setVecResult()

template<typename T >

void CheckerCPU::setVecResult ( T && t )

inline

Definition at line 339 of file cpu.hh.

References ArmISA::t, and InstResult::VecReg.

Referenced by setVecRegOperand().

◆ syscall()

void CheckerCPU::syscall ( Fault * fault )

inlineoverridevirtual

Executes a syscall.

Implements ExecContext.

Definition at line 580 of file cpu.hh.

◆ tcBase()

ThreadContext* CheckerCPU::tcBase ( ) const

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 594 of file cpu.hh.

References tc.

◆ threadBase()

SimpleThread* CheckerCPU::threadBase ( )

inline

Definition at line 595 of file cpu.hh.

References thread.

◆ totalInsts()

virtual Counter CheckerCPU::totalInsts ( ) const

inlineoverridevirtual

Implements BaseCPU.

Definition at line 159 of file cpu.hh.

◆ totalOps()

virtual Counter CheckerCPU::totalOps ( ) const

inlineoverridevirtual

Implements BaseCPU.

Definition at line 164 of file cpu.hh.

◆ unserialize()

void CheckerCPU::unserialize ( CheckpointIn & cp )

overridevirtual

Reconstruct the state of this object from a checkpoint.

Note: CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The checkpoint use.

Reimplemented from BaseCPU.

Definition at line 135 of file cpu.cc.

◆ wakeup()

void CheckerCPU::wakeup ( ThreadID tid )

inlineoverridevirtual

Implements BaseCPU.

Definition at line 577 of file cpu.hh.

◆ writeMem()

Fault CheckerCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

bool CheckerCPU::exitOnError

Definition at line 604 of file cpu.hh.

Referenced by CheckerCPU(), handleError(), and Checker< O3CPUImpl >::handleError().

◆ icachePort

MasterPort* CheckerCPU::icachePort

protected

Definition at line 130 of file cpu.hh.

Referenced by getInstPort(), and setIcachePort().

◆ itb

BaseTLB* CheckerCPU::itb

protected

Definition at line 135 of file cpu.hh.

Referenced by CheckerCPU(), getITBPtr(), and setSystem().

◆ masterId

RequestPtr CheckerCPU::unverifiedReq

Definition at line 598 of file cpu.hh.

Referenced by readMem(), and writeMem().

◆ unverifiedResult

InstResult CheckerCPU::unverifiedResult

Definition at line 597 of file cpu.hh.

◆ updateOnError

bool CheckerCPU::updateOnError

Definition at line 605 of file cpu.hh.

Referenced by CheckerCPU(), and Checker< O3CPUImpl >::handleError().

◆ warnOnlyOnLoadError

bool CheckerCPU::warnOnlyOnLoadError

Definition at line 606 of file cpu.hh.

Referenced by CheckerCPU().

◆ willChangePC

bool CheckerCPU::willChangePC

Definition at line 602 of file cpu.hh.

Referenced by CheckerCPU().

◆ workload

std::vector<Process*> CheckerCPU::workload

protected

Definition at line 126 of file cpu.hh.

Referenced by CheckerCPU(), and setSystem().

◆ youngestSN

InstSeqNum CheckerCPU::youngestSN

Definition at line 608 of file cpu.hh.

Referenced by CheckerCPU().

The documentation for this class was generated from the following files:

cpu/checker/cpu.hh
cpu/checker/cpu.cc

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ MachInst

◆ Params

◆ VecRegContainer

Constructor & Destructor Documentation

◆ CheckerCPU()

◆ ~CheckerCPU()

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ checkFlags()

◆ demapDataPage()

◆ demapInstPage()

◆ demapPage()

◆ dumpAndExit()

◆ genMemFragmentRequest()

◆ getAddrMonitor()

◆ getDataPort()

◆ getDTBPtr()

◆ getInstPort()

◆ getITBPtr()

◆ getWritableVecPredRegOperand()

◆ getWritableVecRegOperand()

◆ handleError()

◆ init()

◆ instAddr()

◆ microPC()

◆ mwait()

◆ mwaitAtomic()

◆ nextInstAddr()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readCCRegOperand()

◆ readFloatRegOperandBits()

◆ readIntRegOperand()

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ readVec16BitLaneOperand()

◆ readVec32BitLaneOperand()

◆ readVec64BitLaneOperand()

◆ readVec8BitLaneOperand()

◆ readVecElemOperand()

◆ readVecPredRegOperand()

◆ readVecRegOperand()

◆ recordPCChange()

◆ serialize()

◆ setCCRegOperand()

◆ setDcachePort()

◆ setFloatRegOperandBits()

◆ setIcachePort()

◆ setIntRegOperand()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegNoEffect()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setScalarResult()

◆ setStCondFailures()

◆ setSystem()

◆ setVecElemOperand()

◆ setVecElemResult()

◆ setVecLaneOperand() [1/4]

◆ setVecLaneOperand() [2/4]

◆ setVecLaneOperand() [3/4]

◆ setVecLaneOperand() [4/4]

◆ setVecLaneOperandT()

◆ setVecPredRegOperand()

◆ setVecPredResult()