gem5
v20.0.0.3
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#include <iosfwd>
#include <string>
#include <utility>
#include <vector>
#include "base/types.hh"
#include "dev/net/etherpkt.hh"
#include "dnet/os.h"
#include "dnet/eth.h"
#include "dnet/ip.h"
#include "dnet/ip6.h"
#include "dnet/addr.h"
#include "dnet/arp.h"
#include "dnet/icmp.h"
#include "dnet/tcp.h"
#include "dnet/udp.h"
#include "dnet/intf.h"
#include "dnet/route.h"
#include "dnet/fw.h"
#include "dnet/blob.h"
#include "dnet/rand.h"
Go to the source code of this file.
Classes | |
struct | Net::EthAddr |
struct | Net::EthHdr |
class | Net::EthPtr |
struct | Net::IpAddress |
struct | Net::IpNetmask |
struct | Net::IpWithPort |
struct | Net::IpHdr |
class | Net::IpPtr |
struct | Net::IpOpt |
struct | Net::Ip6Hdr |
class | Net::Ip6Ptr |
struct | Net::ip6_opt_fragment |
struct | Net::ip6_opt_routing_type2 |
struct | Net::ip6_opt_dstopts |
struct | Net::ip6_opt_hdr |
struct | Net::Ip6Opt |
struct | Net::TcpHdr |
class | Net::TcpPtr |
struct | Net::TcpOpt |
struct | Net::UdpHdr |
class | Net::UdpPtr |
Namespaces | |
Net | |
Macros | |
#define | HOME_ADDRESS_OPTION 0xC9 |
Functions | |
std::ostream & | Net::operator<< (std::ostream &stream, const EthAddr &ea) |
bool | Net::operator== (const EthAddr &left, const EthAddr &right) |
std::ostream & | Net::operator<< (std::ostream &stream, const IpAddress &ia) |
bool | Net::operator== (const IpAddress &left, const IpAddress &right) |
std::ostream & | Net::operator<< (std::ostream &stream, const IpNetmask &in) |
bool | Net::operator== (const IpNetmask &left, const IpNetmask &right) |
std::ostream & | Net::operator<< (std::ostream &stream, const IpWithPort &iwp) |
bool | Net::operator== (const IpWithPort &left, const IpWithPort &right) |
uint16_t | Net::cksum (const IpPtr &ptr) |
struct Net::ip6_opt_dstopts | Net::__attribute__ ((packed)) |
uint16_t | Net::cksum (const TcpPtr &tcp) |
uint16_t | Net::__tu_cksum6 (const Ip6Ptr &ip6) |
uint16_t | Net::__tu_cksum (const IpPtr &ip) |
uint16_t | Net::cksum (const UdpPtr &udp) |
int | Net::hsplit (const EthPacketPtr &ptr) |
Variables | |
uint8_t | type |
uint8_t | length |
ip6_addr_t | addr |
uint8_t | ext_nxt |
uint8_t | ext_len |
union { | |
struct ip6_opt_fragment fragment | |
struct ip6_opt_routing_type2 rtType2 | |
struct ip6_opt_dstopts dstOpts | |
} | ext_data |
Net::Ip6Opt | Net::__attribute__ |
ip6_addr_t addr |
Definition at line 330 of file inet.hh.
Referenced by SimpleCache::accessTiming(), Workload::addFuncEvent(), LSQ< Impl >::LSQRequest::addRequest(), addressToInt(), DRAMCtrl::addToReadQueue(), DRAMCtrl::addToWriteQueue(), BaseCache::allocateBlock(), amoMemAtomicBE(), amoMemAtomicLE(), ArmISA::ArmStaticInst::ArmStaticInst(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::AtomicInst(), bitSelect(), AbstractController::blockOnQueue(), SMMUTranslationProcess::bypass(), HsailISA::Call::calcAddr(), Prefetcher::IrregularStreamBuffer::calculatePrefetch(), Prefetcher::BOP::calculatePrefetch(), Prefetcher::PIF::calculatePrefetch(), Prefetcher::IndirectMemory::calculatePrefetch(), BaseRemoteGDB::cmd_clr_hw_bkpt(), BaseRemoteGDB::cmd_mem_r(), BaseRemoteGDB::cmd_mem_w(), BaseRemoteGDB::cmd_set_hw_bkpt(), Prefetcher::PIF::CompactorEntry::CompactorEntry(), connectFunc(), Prefetcher::Queued::createPrefetchRequest(), Linux::ThreadInfo::curThreadInfo(), DRAMCtrl::decodeAddr(), PseudoInst::decodeAddrOffset(), SkewedAssociative::dehash(), MSHR::delay(), BaseDynInst< Impl >::demapDataPage(), CheckerCPU::demapDataPage(), SparcISA::TLB::demapPage(), DMASequencer::descheduleDeadlockEvent(), SkewedAssociative::deskew(), IdeController::dispatchAccess(), GenericPciHost::dmaAddr(), SMMUProcess::doRead(), ItsProcess::doRead(), SMMUProcess::doWrite(), ItsProcess::doWrite(), Trace::IntelTraceRecord::dump(), ProfileNode::dump(), LSQ< Impl >::dumpInsts(), HsailISA::LdaInst< DestDataType, AddrOperandType >::execute(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORD::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORD::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4::execute(), Gcn3ISA::Inst_DS__DS_WRITE_B32::execute(), Gcn3ISA::Inst_DS__DS_WRITE2_B32::execute(), Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32::execute(), Gcn3ISA::Inst_DS__DS_WRITE_B8::execute(), Gcn3ISA::Inst_DS__DS_WRITE_B16::execute(), Gcn3ISA::Inst_DS__DS_READ_B32::execute(), Gcn3ISA::Inst_DS__DS_READ2_B32::execute(), Gcn3ISA::Inst_DS__DS_READ2ST64_B32::execute(), Gcn3ISA::Inst_DS__DS_READ_U8::execute(), Gcn3ISA::Inst_DS__DS_READ_U16::execute(), Gcn3ISA::Inst_DS__DS_WRITE_B64::execute(), Gcn3ISA::Inst_DS__DS_WRITE2_B64::execute(), Gcn3ISA::Inst_DS__DS_READ_B64::execute(), Gcn3ISA::Inst_DS__DS_READ2_B64::execute(), Gcn3ISA::Inst_DS__DS_READ2ST64_B64::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3::execute(), Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute(), Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute(), Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(), Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD::execute(), Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(), Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(), Prefetcher::StridePrefetcherHashedSetAssociative::extractTag(), Workload::fixFuncEventAddr(), TranslatingPortProxy::fixupAddr(), Gicv2m::frameFromAddr(), RubySystem::functionalWrite(), Network::functionalWrite(), HsailISA::LdaInst< DestDataType, AddrOperandType >::generateDisassembly(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::generateDisassembly(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::generateDisassembly(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::generateDisassembly(), GuestABI::Argument< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::get(), Linux::ThreadInfo::get_data(), ArmSemihosting::AbiBase::StateBase< Arg >::getAddr(), DRAMCtrl::DRAMPacket::getAddr(), Packet::getAddr(), RubyPort::MemSlavePort::getAddrRanges(), Gicv2m::getAddrRanges(), Prefetcher::DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(), CacheMemory::getDataLatency(), GPUCoalescer::getFirstResponseToCompletionDelayHist(), BaseKvmCPU::getGuestData(), AtomicSimpleCPU::getInstPort(), TimingSimpleCPU::getInstPort(), CallArgMem::getLaneAddr(), Minor::LSQ::getLastMemBarrier(), RandomGen::getNextPacket(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::getNumOperands(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::getNumOperands(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::getOperandSize(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::getOperandSize(), BaseGen::getPacket(), System::getPhysMem(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::getRegisterIndex(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::getRegisterIndex(), BaseCache::handleFill(), SkewedAssociative::hash(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), AbstractController::initNetworkPtr(), ArmISA::FsFreebsd::initState(), ArmLinuxProcess32::initState(), ArmISA::FsLinux::initState(), TempCacheBlk::insert(), BaseRemoteGDB::insertHardBreak(), Prefetcher::BOP::insertIntoRR(), intToAddress(), VIPERCoalescer::invL1(), RiscvISA::RiscvFault::invoke(), VIPERCoalescer::invwbL1(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::isCondRegister(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::isCondRegister(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::isScalarRegister(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::isScalarRegister(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::isSrcOperand(), QueueEntry::isUncacheable(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::isVectorRegister(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::isVectorRegister(), ArmISA::itState(), HsailISA::LdaInst< DestDataType, AddrOperandType >::LdaInst(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::LdInst(), Loader::SymbolTable::load(), PseudoInst::loadsymbol(), QoS::MemCtrl::logRequest(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), makeLineAddress(), maskLowOrderBits(), BloomFilter::Base::merge(), BaseCPU::mwaitAtomic(), PhysicalMemory::name(), TraceCPU::FixedRetryGen::name(), ComputeUnit::nextLocRdBus(), Prefetcher::Queued::nextPrefetchReadyTime(), Gicv3Distributor::nsAccessToSecInt(), std::hash< ChannelAddr >::operator()(), ArmISA::TLBIMVAA::operator()(), ArmISA::TLBIMVA::operator()(), ArmISA::ITLBIMVA::operator()(), ArmISA::DTLBIMVA::operator()(), ArmISA::TLBIIPA::operator()(), RubyPrefetcher::pageAddress(), Iris::ThreadContext::pcState(), WriteQueueEntry::popTarget(), BaseRemoteGDB::TrapEvent::process(), SMMUv3::processCommand(), Gicv3Redistributor::processorNumber(), ArmISA::purifyTaggedAddr(), Sp805::read(), NoMaliGpu::read(), FVPBasePwrCtrl::read(), Gicv3::read(), Gicv3Its::read(), ArmSemihosting::InPlaceArg::read(), VGic::read(), GenericTimerFrame::read(), GicV2::read(), GenericTimerMem::read(), MC146818::readData(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), readMemAtomicBE(), readMemAtomicLE(), ArmISA::readSymbol(), MessageBuffer::reanalyzeMessages(), SMMUControlPort::recvAtomic(), MemCheckerMonitor::recvFunctional(), MemCheckerMonitor::recvFunctionalSnoop(), MemCheckerMonitor::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), RealViewCtrl::registerDevice(), RangeAddrMapper::remapAddr(), SimpleLTInitiator1_dmi::run(), Prefetcher::Base::PrefetchInfo::sameAddr(), SC_MODULE(), ArmSemihosting::SemiCall::SemiCall(), TraceCPU::FixedRetryGen::send(), tlm::tlm_dmi::set_end_address(), tlm::tlm_dmi::set_start_address(), SubBlock::setAddress(), AccessTraceForAddress::setAddress(), VirtQueue::VirtRing< struct vring_used_elem >::setAddress(), RubyPrefetcher::setController(), ArmSystem::setResetAddr(), SnoopFilter::setSlavePorts(), SkewedAssociative::skew(), AbstractController::stallBuffer(), MessageBuffer::stallMessage(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::StInst(), StorageSpace::StorageSpace(), GuestABI::Result< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::store(), StoreTrace::StoreTrace(), SubBlock::SubBlock(), RiscvISA::Decoder::takeOverFrom(), TEST(), Trace::ExeTracerRecord::traceInst(), tryTranslate(), Loader::SymbolTable::unserialize(), AbstractController::wakeUpAllBuffers(), AbstractController::wakeUpBuffers(), RiscvISA::Walker::WalkerSenderState::WalkerSenderState(), RiscvISA::Walker::WalkerState::WalkerState(), VIPERCoalescer::wbL1(), Sp805::write(), NoMaliGpu::write(), FVPBasePwrCtrl::write(), Gicv3::write(), Gicv3Its::write(), ArmSemihosting::InPlaceArg::write(), VGic::write(), GenericTimerFrame::write(), GicV2::write(), GenericTimerMem::write(), Wavefront::writeCallArgMem(), MC146818::writeData(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), CheckerCPU::writeMem(), writeMemAtomicBE(), writeMemAtomicLE(), writeMemTimingBE(), writeMemTimingLE(), AddrMapper::~AddrMapper(), BaseIndexingPolicy::~BaseIndexingPolicy(), BaseTags::~BaseTags(), CompressedTags::~CompressedTags(), GenericArmPciHost::~GenericArmPciHost(), GpuDispatcher::~GpuDispatcher(), MemChecker::~MemChecker(), PortProxy::~PortProxy(), SectorTags::~SectorTags(), and SkewedAssociative::~SkewedAssociative().
union { ... } ext_data |
uint8_t ext_len |
Definition at line 329 of file inet.hh.
Referenced by Net::Ip6Opt::extlen().
uint8_t ext_nxt |
Definition at line 328 of file inet.hh.
Referenced by Net::Ip6Opt::nxt().
struct ip6_opt_fragment fragment |
Definition at line 331 of file inet.hh.
Referenced by Minor::LSQ::SplitDataRequest::makeFragmentPackets(), and Minor::LSQ::SplitDataRequest::makeFragmentRequests().
uint8_t length |
Definition at line 329 of file inet.hh.
Referenced by sc_dt::sc_proxy< sc_subref_r< X > >::check_bounds(), BaseRemoteGDB::cmd_query_var(), sc_dt::sc_int_subref_r::concat_get_uint64(), sc_dt::sc_uint_subref_r::concat_length(), sc_dt::sc_int_subref_r::concat_length(), sc_dt::sc_uint_base::concat_length(), sc_dt::sc_int_base::concat_length(), sc_dt::sc_uint_subref::concat_set(), sc_dt::sc_int_subref::concat_set(), dumpDmesgEntry(), MemState::extendMmap(), sc_dt::scfx_rep::from_string(), DictionaryCompressor< T >::Pattern::getSizeBits(), MemState::isUnmapped(), sc_dt::sc_int_bitref_r::length(), MemState::mapRegion(), HSADriver::mmap(), Shader::mmap(), mmap2Func(), sc_core::sc_unsigned_sigref::operator=(), sc_core::sc_signed_sigref::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_unsigned_subref::operator=(), sc_dt::sc_signed_subref::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), IGbE::RxDescCache::pktComplete(), PacketFifo::push(), Pl111::readFramebuffer(), Shader::registerCU(), MemState::remapRegion(), UFSHostDevice::SCSIResume(), EthPacketData::serialize(), tlm::tlm_generic_payload::set_data_length(), MemState::setMmapEnd(), sc_dt::sc_bitref_r< X >::size(), sc_dt::sc_subref_r< X >::size(), sc_dt::sc_concref_r< X, Y >::size(), tlm::tlm_to_hostendian_generic(), sc_dt::sc_int_subref_r::to_string(), sc_dt::sc_unsigned::to_string(), sc_dt::sc_signed::to_string(), truncate64Func(), truncateFunc(), MemState::unmapRegion(), EthPacketData::unserialize(), MemState::updateBrkRegion(), X86ISA::SMBios::SMBiosStructure::writeOut(), X86ISA::IntelMP::FloatingPointer::writeOut(), X86ISA::IntelMP::ExtConfigEntry::writeOut(), X86ISA::IntelMP::AddrSpaceMapping::writeOut(), writeOutString(), and MPP_StatisticalCorrector::BranchInfo::~BranchInfo().
uint8_t type |
Definition at line 328 of file inet.hh.
Referenced by __to_number(), Gcn3ISA::VecOperand< DataType, Const, NumDwords >::absModifier(), Stats::Hdf5::addMetaData(), CacheRecorder::addRecord(), ArmISA::TableWalker::LongDescriptor::af(), ArmISA::TableWalker::LongDescriptor::ap(), ArmISA::TableWalker::LongDescriptor::apTable(), PowerProcess::argsInit(), ArmProcess::argsInit(), ArmISA::ArmStaticInst::ArmStaticInst(), ArmISA::TableWalker::LongDescriptor::attrIndx(), broadcast(), GuestABI::callFrom(), GarnetNetwork::collateStats(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), ArmISA::TableWalker::LongDescriptor::contiguousHint(), KvmVM::createDevice(), createMachineID(), ArmISA::TableWalker::LongDescriptor::dbgHeader(), ArmISA::TableWalker::LongDescriptor::domain(), ArmV8KvmCPU::dump(), findRegDataType(), floorLog2(), ArmISA::MemoryReg64::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), GuestABI::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)<=8) >::type >::get(), VecPredRegT< VecElem, NumElems, Packed, Const >::get_raw(), ArmISA::PMU::getCounterTypeRegister(), ArmISA::PMU::getCounterValue(), GPUCoalescer::getFirstResponseToCompletionDelayHist(), Sequencer::getIncompleteTimes(), Throttle::getMsgCount(), Switch::getMsgCount(), ArmV8KvmCPU::getSysRegMap(), ArmISA::TableWalker::LongDescriptor::global(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), RubyPrefetcher::initializeStream(), Net::TcpOpt::isopt(), iGbReg::TxdOp::isType(), DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), LaneData< LS >::LaneData(), Net::IpOpt::len(), Net::TcpOpt::len(), MachineTypeAndNodeIDToMachineID(), mapAddressToRange(), ArmISA::TableWalker::LongDescriptor::memAttr(), ArmISA::TableWalker::LongDescriptor::nextDescAddr(), ArmISA::TableWalker::LongDescriptor::nextTableAddr(), ArmISA::TableWalker::LongDescriptor::offsetBits(), tlm::tlm_phase::operator unsigned int(), VecLaneT< VecElem, Const >::operator VecElem(), CircularQueue< T >::iterator::operator-(), LaneData< LS >::operator=(), VecLaneT< VecElem, Const >::operator=(), VecPredRegT< VecElem, NumElems, Packed, Const >::operator[](), VecRegT< VecElem, NumElems, Const >::operator[](), Gcn3ISA::VecOperand< DataType, Const, NumDwords >::operator[](), Iob::params(), PerfKvmCounterConfig::PerfKvmCounterConfig(), power(), ArmISA::TableWalker::LongDescriptor::pxn(), ArmISA::TableWalker::LongDescriptor::pxnTable(), Random::random(), Sequencer::recordMissLatency(), GPUCoalescer::recordMissLatency(), SimpleNetwork::regStats(), Switch::regStats(), Throttle::regStats(), BaseRemoteGDB::replaceThreadContext(), VecPredRegT< VecElem, NumElems, Packed, Const >::reset(), ArmISA::TableWalker::LongDescriptor::rw(), ArmISA::TableWalker::LongDescriptor::rwTable(), NSGigE::rxFilter(), ArmISA::TableWalker::L1Descriptor::secure(), ArmISA::TableWalker::LongDescriptor::secure(), ArmISA::TableWalker::LongDescriptor::secureTable(), VecPredRegT< VecElem, NumElems, Packed, Const >::set(), AccessTraceForAddress::setAddress(), Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >::setBit(), RubyPrefetcher::setController(), PipeFDEntry::setEndType(), Wavefront::setParent(), NetworkLink::setType(), ArmISA::TableWalker::LongDescriptor::sh(), socketFunc(), socketpairFunc(), to_lower(), BaseRemoteGDB::trap(), ElasticTrace::TraceInfo::typeToStr(), TraceCPU::ElasticDataGen::GraphNode::typeToStr(), ArmISA::TableWalker::LongDescriptor::user(), ArmISA::TableWalker::LongDescriptor::userTable(), VecLaneT< VecElem, Const >::VecLaneT(), VecPredRegT< VecElem, NumElems, Packed, Const >::VecPredRegT(), VecRegT< VecElem, NumElems, Const >::VecRegT(), Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >::write(), Iob::writeIob(), X86ISA::SMBios::SMBiosStructure::writeOut(), X86ISA::E820Table::writeTo(), ArmISA::TableWalker::LongDescriptor::xn(), ArmISA::TableWalker::LongDescriptor::xnTable(), VecRegT< VecElem, NumElems, Const >::zero(), and Gcn3ISA::ScalarOperand< DataType, Const, NumDwords >::~ScalarOperand().