system.hh

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/*
 * Copyright (c) 2010, 2012-2013, 2015-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __ARCH_ARM_SYSTEM_HH__
#define __ARCH_ARM_SYSTEM_HH__

#include <memory>
#include <string>
#include <vector>

#include "kern/linux/events.hh"
#include "params/ArmSystem.hh"
#include "sim/full_system.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"

class GenericTimer;
class BaseGic;
class FVPBasePwrCtrl;
class ThreadContext;

class ArmSystem : public System
{
  protected:
    const bool _haveSecurity;

    const bool _haveLPAE;

    const bool _haveVirtualization;

    const bool _haveCrypto;

    GenericTimer *_genericTimer;
    BaseGic *_gic;

    FVPBasePwrCtrl *_pwrCtrl;

    Addr _resetAddr;

    bool _highestELIs64;

    const uint8_t _physAddrRange64;

    const bool _haveLargeAsid64;

    const bool _haveSVE;

    const unsigned _sveVL;

    const bool _haveLSE;

    const unsigned _havePAN;

    ArmSemihosting *const semihosting;

  public:
    typedef ArmSystemParams Params;
    const Params *
    params() const
    {
        return dynamic_cast<const Params *>(_params);
    }

    ArmSystem(Params *p);

    bool multiProc;

    bool haveSecurity() const { return _haveSecurity; }

    bool haveLPAE() const { return _haveLPAE; }

    bool haveVirtualization() const { return _haveVirtualization; }

    bool haveCrypto() const { return _haveCrypto; }

    void
    setGenericTimer(GenericTimer *generic_timer)
    {
        _genericTimer = generic_timer;
    }

    void setGIC(BaseGic *gic) { _gic = gic; }

    void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
    {
        _pwrCtrl = pwr_ctrl;
    }

    GenericTimer *getGenericTimer() const { return _genericTimer; }

    BaseGic *getGIC() const { return _gic; }

    FVPBasePwrCtrl *getPowerController() const { return _pwrCtrl; }

    bool highestELIs64() const { return _highestELIs64; }

    ExceptionLevel
    highestEL() const
    {
        if (_haveSecurity)
            return EL3;
        if (_haveVirtualization)
            return EL2;
        return EL1;
    }

    Addr resetAddr() const { return _resetAddr; }
    void setResetAddr(Addr addr) { _resetAddr = addr; }

    bool haveLargeAsid64() const { return _haveLargeAsid64; }

    bool haveSVE() const { return _haveSVE; }

    unsigned sveVL() const { return _sveVL; }

    bool haveLSE() const { return _haveLSE; }

    bool havePAN() const { return _havePAN; }

    uint8_t physAddrRange64() const { return _physAddrRange64; }

    uint8_t
    physAddrRange() const
    {
        if (_highestELIs64)
            return _physAddrRange64;
        if (_haveLPAE)
            return 40;
        return 32;
    }

    Addr physAddrMask() const { return mask(physAddrRange()); }

    bool haveSemihosting() const { return semihosting != nullptr; }

    static ArmSystem*
    getArmSystem(ThreadContext *tc)
    {
        assert(FullSystem);
        return static_cast<ArmSystem *>(tc->getSystemPtr());
    }

    static bool haveSecurity(ThreadContext *tc);

    static bool haveVirtualization(ThreadContext *tc);

    static bool haveLPAE(ThreadContext *tc);

    static bool highestELIs64(ThreadContext *tc);

    static ExceptionLevel highestEL(ThreadContext *tc);

    static bool haveEL(ThreadContext *tc, ExceptionLevel el);

    static Addr resetAddr(ThreadContext *tc);

    static uint8_t physAddrRange(ThreadContext *tc);

    static Addr physAddrMask(ThreadContext *tc);

    static bool haveLargeAsid64(ThreadContext *tc);

    static bool haveSemihosting(ThreadContext *tc);

    static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);

    static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);

    static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);

    static void callSetStandByWfi(ThreadContext *tc);

    static void callClearStandByWfi(ThreadContext *tc);

    static bool callSetWakeRequest(ThreadContext *tc);

    static void callClearWakeRequest(ThreadContext *tc);
};

#endif