mem64.hh

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 * Copyright (c) 2011-2013,2017-2019 ARM Limited
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 *
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 * property including but not limited to intellectual property relating
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#ifndef __ARCH_ARM_MEM64_HH__
#define __ARCH_ARM_MEM64_HH__

#include "arch/arm/insts/misc64.hh"
#include "arch/arm/insts/static_inst.hh"

namespace ArmISA
{

class SysDC64 : public MiscRegOp64
{
  protected:
    IntRegIndex base;
    MiscRegIndex dest;
    uint64_t imm;

    // This is used for fault handling only
    mutable Addr faultAddr;

    SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
            IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
        : MiscRegOp64(mnem, _machInst, __opClass, false),
          base(_base), dest(_dest), imm(_imm), faultAddr(0)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MightBeMicro64 : public ArmStaticInst
{
  protected:
    MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
        : ArmStaticInst(mnem, _machInst, __opClass)
    {}

    void
    advancePC(PCState &pcState) const
    {
        if (flags[IsLastMicroop]) {
            pcState.uEnd();
        } else if (flags[IsMicroop]) {
            pcState.uAdvance();
        } else {
            pcState.advance();
        }
    }
};

class Memory64 : public MightBeMicro64
{
  public:
    enum AddrMode {
        AddrMd_Offset,
        AddrMd_PreIndex,
        AddrMd_PostIndex
    };

  protected:

    IntRegIndex dest;
    IntRegIndex base;
    bool baseIsSP;
    static const unsigned numMicroops = 3;

    StaticInstPtr *uops;

    Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
             IntRegIndex _dest, IntRegIndex _base)
        : MightBeMicro64(mnem, _machInst, __opClass),
          dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
    {
        baseIsSP = isSP(_base);
    }

    virtual
    ~Memory64()
    {
        delete [] uops;
    }

    StaticInstPtr
    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
    }

    void startDisassembly(std::ostream &os) const;

    unsigned memAccessFlags;

    void setExcAcRel(bool exclusive, bool acrel);
};

class MemoryImm64 : public Memory64
{
  protected:
    int64_t imm;

    MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
        : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryDImm64 : public MemoryImm64
{
  protected:
    IntRegIndex dest2;

    MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
                int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
          dest2(_dest2)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryDImmEx64 : public MemoryDImm64
{
  protected:
    IntRegIndex result;

    MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
                 IntRegIndex _base, int32_t _imm)
        : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
                     _base, _imm), result(_result)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryPreIndex64 : public MemoryImm64
{
  protected:
    MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
                     int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryPostIndex64 : public MemoryImm64
{
  protected:
    MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
                      OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
                      int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryReg64 : public Memory64
{
  protected:
    IntRegIndex offset;
    ArmExtendType type;
    uint64_t shiftAmt;

    MemoryReg64(const char *mnem, ExtMachInst _machInst,
                OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
                IntRegIndex _offset, ArmExtendType _type,
                uint64_t _shiftAmt)
        : Memory64(mnem, _machInst, __opClass, _dest, _base),
          offset(_offset), type(_type), shiftAmt(_shiftAmt)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryRaw64 : public Memory64
{
  protected:
    MemoryRaw64(const char *mnem, ExtMachInst _machInst,
                OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
        : Memory64(mnem, _machInst, __opClass, _dest, _base)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryEx64 : public Memory64
{
  protected:
    IntRegIndex result;

    MemoryEx64(const char *mnem, ExtMachInst _machInst,
               OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
               IntRegIndex _result)
        : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

class MemoryLiteral64 : public Memory64
{
  protected:
    int64_t imm;

    MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
                    OpClass __opClass, IntRegIndex _dest, int64_t _imm)
        : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
    {}

    std::string generateDisassembly(
            Addr pc, const Loader::SymbolTable *symtab) const override;
};

}

#endif //__ARCH_ARM_INSTS_MEM_HH__