types.hh File Reference

Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t. More...

#include <inttypes.h>
#include <cassert>
#include <memory>
#include <ostream>
#include <stdexcept>
#include "base/refcnt.hh"

Go to the source code of this file.

Classes
class	Cycles
	Cycles is a wrapper class for representing cycle counts, i.e. More...

Macros
#define	ULL(N)   ((uint64_t)N##ULL)
	uint64_t constant More...
#define	LL(N)   ((int64_t)N##LL)
	int64_t constant More...

Typedefs
typedef int64_t	Counter
	Statistics counter type. More...
typedef uint64_t	Tick
	Tick count type. More...
typedef uint64_t	Addr
	Address type This will probably be moved somewhere else in the near future. More...
typedef uint16_t	MicroPC
typedef uint64_t	RegVal
typedef int16_t	ThreadID
	Thread index/ID type. More...
typedef int	ContextID
	Globally unique thread context ID. More...
typedef int16_t	PortID
	Port index/ID type, and a symbolic name for an invalid port id. More...
typedef std::shared_ptr< FaultBase >	Fault

Enumerations
enum	ByteOrder { BigEndianByteOrder, LittleEndianByteOrder }

Functions
static MicroPC	romMicroPC (MicroPC upc)
static MicroPC	normalMicroPC (MicroPC upc)
static bool	isRomMicroPC (MicroPC upc)
static uint32_t	floatToBits32 (float val)
static uint64_t	floatToBits64 (double val)
static uint64_t	floatToBits (double val)
static uint32_t	floatToBits (float val)
static float	bitsToFloat32 (uint32_t val)
static double	bitsToFloat64 (uint64_t val)
static double	bitsToFloat (uint64_t val)
static float	bitsToFloat (uint32_t val)

Variables
const Tick	MaxTick = ULL(0xffffffffffffffff)
static const MicroPC	MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
const Addr	MaxAddr = (Addr)-1
const ThreadID	InvalidThreadID = (ThreadID)-1
const ContextID	InvalidContextID = (ContextID)-1
const PortID	InvalidPortID = (PortID)-1
decltype(nullptr) constexpr	NoFault = nullptr

Detailed Description

Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.

Definition in file types.hh.

Macro Definition Documentation

LL

#define LL

(

N

)

((int64_t)N##LL)

int64_t constant

Definition at line 50 of file types.hh.

Referenced by Gcn3ISA::Inst_SOPP__S_BRANCH::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC0::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC1::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCZ::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCNZ::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECZ::execute(), Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECNZ::execute(), Gcn3ISA::Inst_VOP3__V_MUL_LO_U32::execute(), Gcn3ISA::Inst_VOP3__V_MUL_HI_I32::execute(), mask(), Gcn3ISA::processDPP(), Sinic::Device::rxKick(), ArmISA::ArmStaticInst::satInt(), ArmISA::ArmStaticInst::saturateOp(), ArmISA::ArmStaticInst::uSatInt(), ArmISA::ArmStaticInst::uSaturateOp(), and ArmISA::vfpFpToFixed().

ULL

#define ULL

(

N

)

((uint64_t)N##ULL)

uint64_t constant

Definition at line 48 of file types.hh.

Referenced by MipsISA::addHalfLsb(), AddrRange::AddrRange(), PosixKvmTimer::arm(), BiModeBP::BiModeBP(), ArmISA::FpOp::binaryOp(), MPP_TAGE::bindex(), TAGE_SC_L_TAGE::bindex(), TAGEBase::bindex(), BiModeBP::btbUpdate(), TournamentBP::btbUpdate(), PosixKvmTimer::calcResolution(), X86ISA::ISA::clear(), RiscvISA::ISA::clear(), ArmISA::Interrupts::clear(), SparcISA::Interrupts::clear(), SparcISA::ISA::clear(), Gicv3Its::collectionOutOfRange(), Linux::ThreadInfo::curThreadInfo(), Gicv3Its::deviceOutOfRange(), DRAMCtrl::DRAMCtrl(), EtherDump::dumpPacket(), sc_gem5::Event::Event(), Gcn3ISA::Inst_SOP2__S_BFM_B64::execute(), Gcn3ISA::Inst_VOP3__V_ALIGNBYTE_B32::execute(), Trie< Addr, TlbEntry >::extendMask(), TAGE_SC_L_TAGE::F(), TAGEBase::F(), findOverflow(), Gcn3ISA::firstOppositeSignBit(), ArmISA::fixDest(), ArmISA::fixDivDest(), ArmISA::fixFpSFpDDest(), floorLog2(), ArmISA::flushToZero(), ArmISA::fp16_cvtf(), ArmISA::fp16_defaultNaN(), ArmISA::fp16_FPConvertNaN_32(), ArmISA::fp16_FPConvertNaN_64(), ArmISA::fp16_FPOnePointFive(), ArmISA::fp16_FPThree(), ArmISA::fp16_process_NaN(), ArmISA::fp16_round_(), ArmISA::fp16_unpack(), ArmISA::fp32_cvtf(), ArmISA::fp32_defaultNaN(), ArmISA::fp32_FPConvertNaN_16(), ArmISA::fp32_FPConvertNaN_64(), ArmISA::fp32_FPOnePointFive(), ArmISA::fp32_FPThree(), ArmISA::fp32_process_NaN(), ArmISA::fp32_round_(), ArmISA::fp32_unpack(), ArmISA::fp64_defaultNaN(), ArmISA::fp64_FPConvertNaN_16(), ArmISA::fp64_FPConvertNaN_32(), ArmISA::fp64_FPOnePointFive(), ArmISA::fp64_FPThree(), ArmISA::fp64_process_NaN(), ArmISA::fp64_round_(), ArmISA::fp64_unpack(), ArmISA::fplibAbs(), ArmISA::fplibConvert(), ArmISA::fplibExpA(), ArmISA::fplibFPToFixedJS(), ArmISA::fplibNeg(), ArmISA::fplibTrigMulAdd(), ArmISA::fplibTrigSMul(), ArmISA::fpMaxNum(), ArmISA::fpMinNum(), ArmISA::fpMulAdd(), ArmISA::fpRecipEstimate(), ArmISA::fprSqrtEstimate(), ArmISA::FPToFixed_16(), ArmISA::FPToFixed_32(), ArmISA::FPToFixed_64(), ArmSemihosting::gatherHeapInfo(), GicV2::genSwiMask(), SparcISA::getREDVector(), LoopPredictor::getSizeInBits(), TAGEBase::getSizeInBits(), TAGE_SC_L_TAGE::gindex(), TAGEBase::gindex(), AddrRange::granularity(), TAGE_SC_L_TAGE_8KB::gtag(), TAGE_SC_L_TAGE_64KB::gtag(), TAGEBase::gtag(), TAGEBase::handleAllocAndUReset(), MPP_TAGE::handleUReset(), TAGE_SC_L_TAGE::handleUReset(), TAGEBase::handleUReset(), SMMUTranslationProcess::hazard4kCheck(), SMMUTranslationProcess::hazard4kHold(), RiscvISA::ISA::hpmCounterEnabled(), X86ISA::I386Process::I386Process(), Gicv3Its::idOutOfRange(), TAGEBase::init(), StatTest::init(), LoopPredictor::init(), ArmISA::ISA::initID64(), ArmISA::FsFreebsd::initState(), SparcISA::PowerOnReset::invoke(), Iob::Iob(), ArmISA::isSnan(), Gicv3Its::lpiOutOfRange(), SMMUTranslationProcess::main(), SparcISA::TLB::MakeTsbPtr(), mask(), Gicv3Its::moveAllPendingState(), ArmISA::Interrupts::post(), SparcISA::Interrupts::post(), AnnotateDumpCallback::process(), SparcISA::ISA::processHSTickCompare(), ComputeUnit::DataPort::processMemRespEvent(), ArmISA::FpOp::processNans(), SparcISA::ISA::processSTickCompare(), ArmISA::TableWalker::processWalkLPAE(), GicV2::readCpu(), PseudoInst::readfile(), SparcISA::ISA::readFSReg(), X86ISA::Interrupts::readReg(), ArmISA::SkipFunc::returnFromFuncIn(), StatTest::run(), IGbE::rxStateMachine(), iGbReg::TxdOp::setDd(), SparcISA::ISA::setFSReg(), SparcISA::ISA::setMiscRegNoEffect(), X86ISA::Interrupts::setReg(), MipsISA::signExtend(), ArmISA::simd_modified_imm(), Sparc32Process::Sparc32Process(), Sparc64Process::Sparc64Process(), IdeDisk::startDma(), AddrRange::stripes(), swap_byte64(), SparcISA::TLB::TagRead(), MipsISA::ProcessInfo::task(), X86ISA::ProcessInfo::task(), ArmISA::ProcessInfo::task(), ArmISA::FpOp::ternaryOp(), TEST(), SparcISA::TlbEntry::TlbEntry(), AddrRange::to_string(), TournamentBP::TournamentBP(), ArmISA::FpOp::unaryOp(), ArmISA::unsignedRecipEstimate(), ArmISA::unsignedRSqrtEstimate(), TAGEBase::FoldedHistory::update(), TAGEBase::updateHistories(), TAGE_SC_L_TAGE::updatePathAndGlobalHistory(), A9GlobalTimer::Timer::write(), GicV2::writeCpu(), and X86ISA::X86_64Process::X86_64Process().

Typedef Documentation

Addr

typedef uint64_t Addr

Address type This will probably be moved somewhere else in the near future.

This should be at least as big as the biggest address width in use in the system, which will probably be 64 bits.

Definition at line 140 of file types.hh.

ContextID

typedef int ContextID

Globally unique thread context ID.

Definition at line 229 of file types.hh.

Counter

typedef int64_t Counter

Statistics counter type.

All counters are of 64-bit values.

Not much excuse for not using a 64-bit integer here, but if you're desperate and only run short simulations you could make this 32 bits.

Definition at line 56 of file types.hh.

Fault

typedef std::shared_ptr<FaultBase> Fault

Definition at line 238 of file types.hh.

MicroPC

typedef uint16_t MicroPC

Definition at line 142 of file types.hh.

PortID

typedef int16_t PortID

Port index/ID type, and a symbolic name for an invalid port id.

Definition at line 235 of file types.hh.

RegVal

typedef uint64_t RegVal

Definition at line 166 of file types.hh.

ThreadID

typedef int16_t ThreadID

Thread index/ID type.

Definition at line 225 of file types.hh.

Tick

typedef uint64_t Tick

Tick count type.

Definition at line 61 of file types.hh.

Enumeration Type Documentation

ByteOrder

enum ByteOrder

Enumerator
BigEndianByteOrder
LittleEndianByteOrder

Definition at line 245 of file types.hh.

Function Documentation

bitsToFloat() [1/2]

static double bitsToFloat ( uint64_t  val )

inlinestatic

Definition at line 219 of file types.hh.

References bitsToFloat64().

bitsToFloat() [2/2]

static float bitsToFloat ( uint32_t  val )

inlinestatic

Definition at line 220 of file types.hh.

References bitsToFloat32().

bitsToFloat32()

static float bitsToFloat32 ( uint32_t  val )

inlinestatic

Definition at line 196 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by bitsToFloat(), GuestABI::Argument< Aapcs32, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::get(), and Trace::TarmacTracerRecord::TraceRegEntry::updateFloat().

bitsToFloat64()

static double bitsToFloat64 ( uint64_t  val )

inlinestatic

Definition at line 208 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by bitsToFloat(), GuestABI::Argument< Aapcs32, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::get(), and updateKvmStateFPUCommon().

floatToBits() [1/2]

static uint64_t floatToBits ( double  val )

inlinestatic

Definition at line 192 of file types.hh.

References floatToBits64().

Referenced by GuestABI::Result< Aapcs32, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), and TEST().

floatToBits() [2/2]

static uint32_t floatToBits ( float  val )

inlinestatic

Definition at line 193 of file types.hh.

References floatToBits32().

floatToBits32()

static uint32_t floatToBits32 ( float  val )

inlinestatic

Definition at line 169 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by floatToBits(), and TEST().

floatToBits64()

static uint64_t floatToBits64 ( double  val )

inlinestatic

Definition at line 181 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by floatToBits(), TEST(), and updateThreadContextFPUCommon().

isRomMicroPC()

static bool isRomMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 159 of file types.hh.

References MicroPCRomBit.

Referenced by TimingSimpleCPU::fetch(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::pipelineIcacheAccesses(), BaseSimpleCPU::preExecute(), TEST(), AtomicSimpleCPU::tick(), and Checker< O3CPUImpl >::verify().

normalMicroPC()

static MicroPC normalMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 153 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISAInst::MicrocodeRom::fetchMicroop(), and TEST().

romMicroPC()

static MicroPC romMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 147 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISA::X86FaultBase::invoke(), X86ISA::InitInterrupt::invoke(), and TEST().

Variable Documentation

InvalidContextID

const ContextID InvalidContextID = (ContextID)-1

Definition at line 230 of file types.hh.

Referenced by AbstractMemory::checkLockedAddrList(), Sequencer::issueRequest(), System::m5opRange(), LockedAddr::matchesContext(), and System::registerThreadContext().

InvalidPortID

const PortID InvalidPortID = (PortID)-1

Definition at line 236 of file types.hh.

Referenced by EtherBus::busy(), DmaDevice::cacheBlockSize(), FastModel::CortexA76::clockPeriodUpdated(), AbstractController::collateStats(), BaseXBar::findPort(), CoherentXBar::forwardAtomic(), CoherentXBar::forwardFunctional(), CoherentXBar::forwardTiming(), SimpleMemobj::getPort(), SimpleCache::getPort(), System::getSystemPort(), ArmISA::TableWalker::haveLargeAsid64(), BaseCPU::instMasterId(), SimObject::name(), MemCheckerMonitor::params(), EtherSwitch::params(), CommMonitor::params(), X86ISA::I82094AA::params(), FastModel::CortexA76Cluster::params(), PioDevice::params(), EtherLink::params(), CopyEngine::params(), DistEtherLink::params(), NSGigE::params(), IGbE::params(), SnoopFilter::portToMask(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), CoherentXBar::recvFunctionalSnoop(), CoherentXBar::recvTimingReq(), NoncoherentXBar::recvTimingResp(), CoherentXBar::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopResp(), SnoopFilter::setSlavePorts(), DRAMCtrl::sortTime(), RiscvISA::Walker::WalkerSenderState::WalkerSenderState(), X86ISA::Walker::WalkerSenderState::WalkerSenderState(), AddrMapper::~AddrMapper(), RubyPort::~RubyPort(), and SMMUv3::~SMMUv3().

InvalidThreadID

const ThreadID InvalidThreadID = (ThreadID)-1

Definition at line 226 of file types.hh.

Referenced by DefaultFetch< Impl >::branchCount(), Minor::Execute::checkInterrupts(), DefaultFetch< Impl >::doSquash(), DefaultFetch< Impl >::drainSanityCheck(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Fetch1::evaluate(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::finishTranslation(), DefaultCommit< Impl >::getCommittingThread(), Minor::Execute::getCommittingThread(), DefaultFetch< Impl >::getFetchingThread(), FullO3CPU< O3CPUImpl >::getFreeTid(), Minor::Execute::getIssuingThread(), Minor::Decode::getScheduledThread(), Minor::Fetch2::getScheduledThread(), Minor::Fetch1::getScheduledThread(), DefaultFetch< Impl >::iqCount(), DefaultFetch< Impl >::lsqCount(), DefaultCommit< Impl >::oldestReady(), MipsISA::readRegOtherThread(), DefaultFetch< Impl >::recvReqRetry(), DefaultCommit< Impl >::roundRobin(), DefaultFetch< Impl >::roundRobin(), and MipsISA::setRegOtherThread().

MaxAddr

const Addr MaxAddr = (Addr)-1

Definition at line 164 of file types.hh.

Referenced by Prefetcher::SignaturePath::addPrefetch(), BPredUnit::BTBLookup(), Loader::ElfObject::buildImage(), Prefetcher::AccessMapPatternMatching::calculatePrefetch(), GenericTimerFrame::GenericTimerFrame(), MultiperspectivePerceptron::SGHISTPATH::getHash(), AddrRange::getOffset(), KernelWorkload::initState(), CacheBlk::invalidate(), TempCacheBlk::invalidate(), KernelWorkload::KernelWorkload(), Loader::MemoryImage::minAddr(), Prefetcher::STeMS::reconstructSequence(), TEST(), TAGEBase::BranchInfo::~BranchInfo(), MultiperspectivePerceptronTAGE::MPPTAGEBranchInfo::~MPPTAGEBranchInfo(), and TAGE::TageBranchInfo::~TageBranchInfo().

MaxTick

const Tick MaxTick = ULL(0xffffffffffffffff)

Definition at line 63 of file types.hh.

Referenced by ElasticTrace::addCommittedInst(), ElasticTrace::addSquashedInst(), PacketQueue::deferredPacketReadyTime(), BaseTrafficGen::drain(), CacheBlk::getWhenReady(), TraceCPU::FixedRetryGen::init(), CacheBlk::invalidate(), Trace::OstreamLogger::logMessage(), DRAMCtrl::minBankPrep(), ExitGen::nextPacketTick(), IdleGen::nextPacketTick(), RandomGen::nextPacketTick(), LinearGen::nextPacketTick(), TraceGen::nextPacketTick(), Prefetcher::Multi::nextPrefetchReadyTime(), Prefetcher::Queued::nextPrefetchReadyTime(), Queue< WriteQueueEntry >::nextReadyTime(), sc_gem5::Scheduler::oneCycle(), pybind_init_core(), pybind_init_event(), BaseCache::recvTimingReq(), BaseCache::recvTimingResp(), BaseTrafficGen::retryReq(), sc_core::sc_max_time(), sc_core::sc_start(), PacketQueue::schedSendEvent(), BaseTrafficGen::scheduleUpdate(), BaseCache::CacheReqPacketQueue::sendDeferredPacket(), simulate(), Sp805::stopCounter(), BaseKvmCPU::tick(), Sp805::timeoutExpired(), sc_gem5::Scheduler::timeToPending(), and BaseTrafficGen::transition().

MicroPCRomBit

const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)

static

Definition at line 144 of file types.hh.

Referenced by isRomMicroPC(), normalMicroPC(), romMicroPC(), and TEST().

NoFault

decltype(nullptr) constexpr NoFault = nullptr

Definition at line 243 of file types.hh.

Referenced by ArmISA::AArch64AArch32SystemAccessTrap(), RiscvISA::RemoteGDB::acc(), X86ISA::RemoteGDB::acc(), ElasticTrace::addCommittedInst(), ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACGA(), ArmISA::addPACIA(), ArmISA::addPACIB(), ElasticTrace::addSquashedInst(), TimingSimpleCPU::advanceInst(), BaseSimpleCPU::advancePC(), Checker< O3CPUImpl >::advancePC(), AtomicSimpleCPU::amoMem(), amoMemAtomic(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), LSQ< Impl >::SplitDataRequest::buildPackets(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), MipsISA::TLB::checkCacheability(), PowerISA::TLB::checkCacheability(), BaseSimpleCPU::checkForInterrupts(), ArmISA::ArmStaticInst::checkForWFxTrap32(), ArmISA::ArmStaticInst::checkForWFxTrap64(), ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), RiscvISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), ArmISA::ArmStaticInst::checkSETENDEnabled(), ArmISA::ArmStaticInst::checkSveTrap(), LSQUnit< Impl >::checkViolations(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), Minor::Execute::commitInst(), DefaultCommit< Impl >::commitInsts(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), DefaultCommit< Impl >::DefaultCommit(), ArmISA::TableWalker::doL1Descriptor(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2Descriptor(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptor(), ArmISA::TableWalker::doLongDescriptorWrapper(), BaseKvmCPU::doMMIOAccess(), InstructionQueue< Impl >::doSquash(), RiscvISA::TLB::doTranslate(), Minor::Decode::evaluate(), RiscvISA::MemFenceMicro::execute(), SparcISA::Nop::execute(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), SparcISA::WarnUnimplemented::execute(), WarnUnimplemented::execute(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::execute(), MiscRegImplDefined64::execute(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::execute(), McrMrcMiscInst::execute(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), DefaultIEW< Impl >::executeInsts(), LSQUnit< Impl >::executeLoad(), Minor::Execute::executeMemRefInst(), LSQUnit< Impl >::executeStore(), DefaultFetch< Impl >::fetchCacheLine(), ArmISA::TableWalker::fetchDescriptor(), Iris::TLB::finalizePhysical(), RiscvISA::TLB::finalizePhysical(), MipsISA::TLB::finalizePhysical(), X86ISA::TLB::finalizePhysical(), PowerISA::TLB::finalizePhysical(), SparcISA::TLB::finalizePhysical(), ArmISA::TLB::finalizePhysical(), ArmISA::Stage2MMU::Stage2Translation::finish(), ArmISA::Stage2LookUp::finish(), WholeTranslationState::finish(), Prefetcher::Queued::DeferredPacket::finish(), DataTranslation< ExecContextPtr >::finish(), Minor::LSQ::SingleDataRequest::finish(), Minor::LSQ::SplitDataRequest::finish(), LSQ< Impl >::SingleDataRequest::finish(), LSQ< Impl >::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), TimingSimpleCPU::finishTranslation(), WholeTranslationState::getFault(), RiscvISA::Interrupts::getInterrupt(), SparcISA::Interrupts::getInterrupt(), X86ISA::Interrupts::getInterrupt(), ArmISA::TLB::getResultTe(), ArmISA::Stage2LookUp::getTe(), ArmISA::TLB::getTE(), DefaultCommit< Impl >::handleInterrupt(), Minor::Execute::handleMemResponse(), Minor::Fetch1::handleTLBResponse(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initVars(), RiscvISA::SyscallFault::invokeSE(), DefaultCommit< Impl >::isDrained(), Minor::ForwardLineData::isFault(), Minor::MinorDynInst::isFault(), Minor::LSQ::LSQRequest::makePacket(), ArmISA::Stage2LookUp::mergeTe(), Minor::Fetch1::minorTraceResponseLine(), BaseCPU::mwaitAtomic(), Minor::operator<<(), FullO3CPU< O3CPUImpl >::processInterrupts(), Minor::Fetch1::processResponse(), ArmISA::TableWalker::processWalkWrapper(), DefaultCommit< Impl >::propagateInterrupt(), Minor::LSQ::pushRequest(), LSQ< Impl >::pushRequest(), LSQUnit< Impl >::read(), ArmISA::Stage2MMU::readDataUntimed(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), readMemAtomic(), X86ISA::readMemAtomic(), Trace::TarmacParserRecord::readMemNoEffect(), X86ISA::readPackedMemAtomic(), RiscvISA::Walker::WalkerState::recvPacket(), X86ISA::Walker::WalkerState::recvPacket(), Minor::ForwardLineData::reportData(), Minor::MinorDynInst::reportData(), Minor::LSQ::SplitDataRequest::retireResponse(), TimingSimpleCPU::sendFetch(), ArmISA::ISA::setMiscReg(), WholeTranslationState::setNoFault(), RiscvISA::Walker::start(), X86ISA::Walker::start(), RiscvISA::Walker::WalkerState::startFunctional(), X86ISA::Walker::WalkerState::startFunctional(), RiscvISA::Walker::WalkerState::startWalk(), X86ISA::Walker::WalkerState::startWalk(), RiscvISA::Walker::WalkerState::stepWalk(), X86ISA::Walker::WalkerState::stepWalk(), ArmISA::stripPAC(), Minor::Execute::takeInterrupt(), ArmISA::TLB::testTranslation(), ArmISA::TLB::testWalk(), AtomicSimpleCPU::tick(), X86ISA::TLB::translate(), RiscvISA::TLB::translate(), EmulationPageTable::translate(), X86ISA::GpuTLB::translate(), ArmISA::TLB::translateComplete(), SparcISA::TLB::translateData(), Iris::TLB::translateFunctional(), RiscvISA::TLB::translateFunctional(), X86ISA::TLB::translateFunctional(), SparcISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), ArmISA::TLB::translateMmuOn(), MiscRegOp64::trap(), ArmISA::trapPACUse(), ArmISA::ArmStaticInst::trapWFx(), TranslatingPortProxy::tryTLBsOnce(), Minor::Execute::tryToBranch(), Minor::Fetch1::tryToSendToTransfers(), Minor::LSQ::tryToSendToTransfers(), Minor::LSQ::LSQRequest::tryToSuppressFault(), tryTranslate(), ArmISA::ArmStaticInst::undefinedFault64(), Checker< O3CPUImpl >::validateState(), Checker< O3CPUImpl >::verify(), ArmISA::TableWalker::walk(), WholeTranslationState::WholeTranslationState(), LSQUnit< Impl >::write(), LSQUnit< Impl >::writeback(), DefaultIEW< Impl >::writebackInsts(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), CheckerCPU::writeMem(), writeMemAtomic(), X86ISA::writeMemAtomic(), and BaseDynInst< Impl >::~BaseDynInst().