gem5  v20.1.0.0
AbstractCacheEntry.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
42 
43 #include "base/trace.hh"
44 #include "debug/RubyCache.hh"
45 
47 {
48  m_Permission = AccessPermission_NotPresent;
49  m_Address = 0;
50  m_locked = -1;
52  m_htmInReadSet = false;
53  m_htmInWriteSet = false;
54 }
55 
57 {
58 }
59 
60 // Get cache permission
61 AccessPermission
63 {
64  return m_Permission;
65 }
66 
67 void
68 AbstractCacheEntry::changePermission(AccessPermission new_perm)
69 {
70  m_Permission = new_perm;
71  if ((new_perm == AccessPermission_Invalid) ||
72  (new_perm == AccessPermission_NotPresent)) {
73  m_locked = -1;
74  }
75 }
76 
77 void
79 {
80  DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", m_Address, context);
81  m_locked = context;
82 }
83 
84 void
86 {
87  DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", m_Address);
88  m_locked = -1;
89 }
90 
91 bool
92 AbstractCacheEntry::isLocked(int context) const
93 {
94  DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
95  m_Address, m_locked, context);
96  return m_locked == context;
97 }
98 
99 void
101 {
103 }
104 
105 void
107 {
109 }
110 
111 bool
113 {
114  return m_htmInReadSet;
115 }
116 
117 bool
119 {
120  return m_htmInWriteSet;
121 }
ReplaceableEntry
A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement func...
Definition: replaceable_entry.hh:53
AbstractCacheEntry::setInHtmWriteSet
void setInHtmWriteSet(bool val)
Definition: AbstractCacheEntry.cc:106
AbstractCacheEntry::AbstractCacheEntry
AbstractCacheEntry()
Definition: AbstractCacheEntry.cc:46
AbstractCacheEntry::setLocked
void setLocked(int context)
Definition: AbstractCacheEntry.cc:78
AbstractCacheEntry::m_Permission
AccessPermission m_Permission
Definition: AbstractCacheEntry.hh:97
AbstractCacheEntry::m_htmInReadSet
bool m_htmInReadSet
Definition: AbstractCacheEntry.hh:115
AbstractCacheEntry::m_locked
int m_locked
Definition: AbstractCacheEntry.hh:95
AbstractCacheEntry::getInHtmWriteSet
bool getInHtmWriteSet() const
Definition: AbstractCacheEntry.cc:118
AbstractCacheEntry::m_Address
Addr m_Address
Definition: AbstractCacheEntry.hh:92
AbstractCacheEntry::setInHtmReadSet
void setInHtmReadSet(bool val)
Definition: AbstractCacheEntry.cc:100
AbstractCacheEntry::m_last_touch_tick
Tick m_last_touch_tick
Definition: AbstractCacheEntry.hh:61
AbstractCacheEntry::getInHtmReadSet
bool getInHtmReadSet() const
Definition: AbstractCacheEntry.cc:112
AbstractCacheEntry::m_htmInWriteSet
bool m_htmInWriteSet
Definition: AbstractCacheEntry.hh:116
AbstractCacheEntry.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
AbstractCacheEntry::~AbstractCacheEntry
virtual ~AbstractCacheEntry()=0
Definition: AbstractCacheEntry.cc:56
AbstractCacheEntry::clearLocked
void clearLocked()
Definition: AbstractCacheEntry.cc:85
AbstractCacheEntry::changePermission
void changePermission(AccessPermission new_perm)
Definition: AbstractCacheEntry.cc:68
AbstractCacheEntry::getPermission
AccessPermission getPermission() const
Definition: AbstractCacheEntry.cc:62
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
AbstractCacheEntry::isLocked
bool isLocked(int context) const
Definition: AbstractCacheEntry.cc:92
trace.hh

Generated on Wed Sep 30 2020 14:02:13 for gem5 by doxygen 1.8.17