gem5  v20.1.0.0
misc.hh
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37 
38 #ifndef __ARCH_X86_MISCREGS_HH__
39 #define __ARCH_X86_MISCREGS_HH__
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "arch/x86/x86_traits.hh"
43 #include "base/bitunion.hh"
44 #include "base/logging.hh"
45 
46 //These get defined in some system headers (at least termbits.h). That confuses
47 //things here significantly.
48 #undef CR0
49 #undef CR2
50 #undef CR3
51 
52 namespace X86ISA
53 {
54  enum CondFlagBit {
55  CFBit = 1 << 0,
56  PFBit = 1 << 2,
57  ECFBit = 1 << 3,
58  AFBit = 1 << 4,
59  EZFBit = 1 << 5,
60  ZFBit = 1 << 6,
61  SFBit = 1 << 7,
62  DFBit = 1 << 10,
63  OFBit = 1 << 11
64  };
65 
66  const uint32_t cfofMask = CFBit | OFBit;
67  const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
68 
69  enum RFLAGBit {
70  TFBit = 1 << 8,
71  IFBit = 1 << 9,
72  NTBit = 1 << 14,
73  RFBit = 1 << 16,
74  VMBit = 1 << 17,
75  ACBit = 1 << 18,
76  VIFBit = 1 << 19,
77  VIPBit = 1 << 20,
78  IDBit = 1 << 21
79  };
80 
81  enum X87StatusBit {
82  // Exception Flags
83  IEBit = 1 << 0,
84  DEBit = 1 << 1,
85  ZEBit = 1 << 2,
86  OEBit = 1 << 3,
87  UEBit = 1 << 4,
88  PEBit = 1 << 5,
89 
90  // !Exception Flags
91  StackFaultBit = 1 << 6,
92  ErrSummaryBit = 1 << 7,
93  CC0Bit = 1 << 8,
94  CC1Bit = 1 << 9,
95  CC2Bit = 1 << 10,
96  CC3Bit = 1 << 14,
97  BusyBit = 1 << 15,
98  };
99 
101  {
102  // Control registers
103  // Most of these are invalid. See isValidMiscReg() below.
121 
122  // Debug registers
132 
133  // Flags register
135 
136  //Register to keep handy values like the CPU mode in.
138 
139  /*
140  * Model Specific Registers
141  */
142  // Time stamp counter
144 
146 
150 
154 
156 
161 
172 
183 
195 
197 
199 
210 
221 
232 
243 
244  // Extended feature enable register
246 
250 
252 
254 
256 
263 
270 
272 
277 
282 
285 
290 
291  /*
292  * Segment registers
293  */
294  // Segment selectors
309 
310  // Hidden segment base field
325 
326  // The effective segment base, ie what is actually added to an
327  // address. In 64 bit mode this can be different from the above,
328  // namely 0.
343 
344  // Hidden segment limit field
359 
360  // Hidden segment limit attributes
375 
376  // Floating point control registers
379 
390 
391  //XXX Add "Model-Specific Registers"
392 
394 
395  // "Fake" MSRs for internally implemented devices
397 
399  };
400 
401  static inline bool
403  {
404  return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
405  index != MISCREG_CR1 &&
406  !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
407  !(index > MISCREG_CR8 && index <= MISCREG_CR15));
408  }
409 
410  static inline MiscRegIndex
412  {
413  assert(index >= 0 && index < NumCRegs);
414  return (MiscRegIndex)(MISCREG_CR_BASE + index);
415  }
416 
417  static inline MiscRegIndex
419  {
420  assert(index >= 0 && index < NumDRegs);
421  return (MiscRegIndex)(MISCREG_DR_BASE + index);
422  }
423 
424  static inline MiscRegIndex
426  {
427  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
430  }
431 
432  static inline MiscRegIndex
434  {
435  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
438  }
439 
440  static inline MiscRegIndex
442  {
443  assert(index >= 0 && index < (MISCREG_MC_CTL_END -
446  }
447 
448  static inline MiscRegIndex
450  {
451  assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
454  }
455 
456  static inline MiscRegIndex
458  {
459  assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
462  }
463 
464  static inline MiscRegIndex
466  {
467  assert(index >= 0 && index < (MISCREG_MC_MISC_END -
470  }
471 
472  static inline MiscRegIndex
474  {
475  assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
478  }
479 
480  static inline MiscRegIndex
482  {
483  assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
486  }
487 
488  static inline MiscRegIndex
490  {
491  assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
494  }
495 
496  static inline MiscRegIndex
498  {
499  assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
502  }
503 
504  static inline MiscRegIndex
506  {
507  assert(index >= 0 && index < NUM_SEGMENTREGS);
509  }
510 
511  static inline MiscRegIndex
513  {
514  assert(index >= 0 && index < NUM_SEGMENTREGS);
516  }
517 
518  static inline MiscRegIndex
520  {
521  assert(index >= 0 && index < NUM_SEGMENTREGS);
523  }
524 
525  static inline MiscRegIndex
527  {
528  assert(index >= 0 && index < NUM_SEGMENTREGS);
530  }
531 
532  static inline MiscRegIndex
534  {
535  assert(index >= 0 && index < NUM_SEGMENTREGS);
537  }
538 
543  BitUnion64(CCFlagBits)
544  Bitfield<11> of;
545  Bitfield<7> sf;
546  Bitfield<6> zf;
547  Bitfield<5> ezf;
548  Bitfield<4> af;
549  Bitfield<3> ecf;
550  Bitfield<2> pf;
551  Bitfield<0> cf;
552  EndBitUnion(CCFlagBits)
553 
554 
557  BitUnion64(RFLAGS)
558  Bitfield<21> id; // ID Flag
559  Bitfield<20> vip; // Virtual Interrupt Pending
560  Bitfield<19> vif; // Virtual Interrupt Flag
561  Bitfield<18> ac; // Alignment Check
562  Bitfield<17> vm; // Virtual-8086 Mode
563  Bitfield<16> rf; // Resume Flag
564  Bitfield<14> nt; // Nested Task
565  Bitfield<13, 12> iopl; // I/O Privilege Level
566  Bitfield<11> of; // Overflow Flag
567  Bitfield<10> df; // Direction Flag
568  Bitfield<9> intf; // Interrupt Flag
569  Bitfield<8> tf; // Trap Flag
570  Bitfield<7> sf; // Sign Flag
571  Bitfield<6> zf; // Zero Flag
572  Bitfield<4> af; // Auxiliary Flag
573  Bitfield<2> pf; // Parity Flag
574  Bitfield<0> cf; // Carry Flag
575  EndBitUnion(RFLAGS)
576 
577  BitUnion64(HandyM5Reg)
578  Bitfield<0> mode;
579  Bitfield<3, 1> submode;
580  Bitfield<5, 4> cpl;
581  Bitfield<6> paging;
582  Bitfield<7> prot;
583  Bitfield<9, 8> defOp;
584  Bitfield<11, 10> altOp;
585  Bitfield<13, 12> defAddr;
586  Bitfield<15, 14> altAddr;
587  Bitfield<17, 16> stack;
588  EndBitUnion(HandyM5Reg)
589 
590 
593  BitUnion64(CR0)
594  Bitfield<31> pg; // Paging
595  Bitfield<30> cd; // Cache Disable
596  Bitfield<29> nw; // Not Writethrough
597  Bitfield<18> am; // Alignment Mask
598  Bitfield<16> wp; // Write Protect
599  Bitfield<5> ne; // Numeric Error
600  Bitfield<4> et; // Extension Type
601  Bitfield<3> ts; // Task Switched
602  Bitfield<2> em; // Emulation
603  Bitfield<1> mp; // Monitor Coprocessor
604  Bitfield<0> pe; // Protection Enabled
605  EndBitUnion(CR0)
606 
607  // Page Fault Virtual Address
608  BitUnion64(CR2)
609  Bitfield<31, 0> legacy;
610  EndBitUnion(CR2)
611 
612  BitUnion64(CR3)
613  Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
614  // Base Address
615  Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
616  // Base Address
617  Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
618  // Base Address
619  Bitfield<4> pcd; // Page-Level Cache Disable
620  Bitfield<3> pwt; // Page-Level Writethrough
621  EndBitUnion(CR3)
622 
623  BitUnion64(CR4)
624  Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
625  Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
626  // WRGSBASE instructions
627  Bitfield<10> osxmmexcpt; // Operating System Unmasked
628  // Exception Support
629  Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
630  Bitfield<8> pce; // Performance-Monitoring Counter Enable
631  Bitfield<7> pge; // Page-Global Enable
632  Bitfield<6> mce; // Machine Check Enable
633  Bitfield<5> pae; // Physical-Address Extension
634  Bitfield<4> pse; // Page Size Extensions
635  Bitfield<3> de; // Debugging Extensions
636  Bitfield<2> tsd; // Time Stamp Disable
637  Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
638  Bitfield<0> vme; // Virtual-8086 Mode Extensions
639  EndBitUnion(CR4)
640 
641  BitUnion64(CR8)
642  Bitfield<3, 0> tpr; // Task Priority Register
643  EndBitUnion(CR8)
644 
645  BitUnion64(DR6)
646  Bitfield<0> b0;
647  Bitfield<1> b1;
648  Bitfield<2> b2;
649  Bitfield<3> b3;
650  Bitfield<13> bd;
651  Bitfield<14> bs;
652  Bitfield<15> bt;
653  EndBitUnion(DR6)
654 
655  BitUnion64(DR7)
656  Bitfield<0> l0;
657  Bitfield<1> g0;
658  Bitfield<2> l1;
659  Bitfield<3> g1;
660  Bitfield<4> l2;
661  Bitfield<5> g2;
662  Bitfield<6> l3;
663  Bitfield<7> g3;
664  Bitfield<8> le;
665  Bitfield<9> ge;
666  Bitfield<13> gd;
667  Bitfield<17, 16> rw0;
668  Bitfield<19, 18> len0;
669  Bitfield<21, 20> rw1;
670  Bitfield<23, 22> len1;
671  Bitfield<25, 24> rw2;
672  Bitfield<27, 26> len2;
673  Bitfield<29, 28> rw3;
674  Bitfield<31, 30> len3;
675  EndBitUnion(DR7)
676 
677  // MTRR capabilities
678  BitUnion64(MTRRcap)
679  Bitfield<7, 0> vcnt; // Variable-Range Register Count
680  Bitfield<8> fix; // Fixed-Range Registers
681  Bitfield<10> wc; // Write-Combining
682  EndBitUnion(MTRRcap)
683 
687  BitUnion64(SysenterCS)
688  Bitfield<15, 0> targetCS;
689  EndBitUnion(SysenterCS)
690 
691  BitUnion64(SysenterESP)
692  Bitfield<31, 0> targetESP;
693  EndBitUnion(SysenterESP)
694 
695  BitUnion64(SysenterEIP)
696  Bitfield<31, 0> targetEIP;
697  EndBitUnion(SysenterEIP)
698 
702  BitUnion64(McgCap)
703  Bitfield<7, 0> count; // Number of error reporting register banks
704  Bitfield<8> MCGCP; // MCG_CTL register present.
705  EndBitUnion(McgCap)
706 
707  BitUnion64(McgStatus)
708  Bitfield<0> ripv; // Restart-IP valid
709  Bitfield<1> eipv; // Error-IP valid
710  Bitfield<2> mcip; // Machine check in-progress
711  EndBitUnion(McgStatus)
712 
713  BitUnion64(DebugCtlMsr)
714  Bitfield<0> lbr; // Last-branch record
715  Bitfield<1> btf; // Branch single step
716  Bitfield<2> pb0; // Performance monitoring pin control 0
717  Bitfield<3> pb1; // Performance monitoring pin control 1
718  Bitfield<4> pb2; // Performance monitoring pin control 2
719  Bitfield<5> pb3; // Performance monitoring pin control 3
720  /*uint64_t pb(int index)
721  {
722  return bits(__data, index + 2);
723  }*/
724  EndBitUnion(DebugCtlMsr)
725 
726  BitUnion64(MtrrPhysBase)
727  Bitfield<7, 0> type; // Default memory type
728  Bitfield<51, 12> physbase; // Range physical base address
729  EndBitUnion(MtrrPhysBase)
730 
731  BitUnion64(MtrrPhysMask)
732  Bitfield<11> valid; // MTRR pair enable
733  Bitfield<51, 12> physmask; // Range physical mask
734  EndBitUnion(MtrrPhysMask)
735 
736  BitUnion64(MtrrFixed)
737  /*uint64_t type(int index)
738  {
739  return bits(__data, index * 8 + 7, index * 8);
740  }*/
741  EndBitUnion(MtrrFixed)
742 
743  BitUnion64(Pat)
744  /*uint64_t pa(int index)
745  {
746  return bits(__data, index * 8 + 2, index * 8);
747  }*/
748  EndBitUnion(Pat)
749 
750  BitUnion64(MtrrDefType)
751  Bitfield<7, 0> type; // Default type
752  Bitfield<10> fe; // Fixed range enable
753  Bitfield<11> e; // MTRR enable
754  EndBitUnion(MtrrDefType)
755 
759  BitUnion64(McStatus)
760  Bitfield<15,0> mcaErrorCode;
761  Bitfield<31,16> modelSpecificCode;
762  Bitfield<56,32> otherInfo;
763  Bitfield<57> pcc; // Processor-context corrupt
764  Bitfield<58> addrv; // Error-address register valid
765  Bitfield<59> miscv; // Miscellaneous-error register valid
766  Bitfield<60> en; // Error condition enabled
767  Bitfield<61> uc; // Uncorrected error
768  Bitfield<62> over; // Status register overflow
769  Bitfield<63> val; // Valid
770  EndBitUnion(McStatus)
771 
772  BitUnion64(McCtl)
773  /*uint64_t en(int index)
774  {
775  return bits(__data, index);
776  }*/
777  EndBitUnion(McCtl)
778 
779  // Extended feature enable register
780  BitUnion64(Efer)
781  Bitfield<0> sce; // System call extensions
782  Bitfield<8> lme; // Long mode enable
783  Bitfield<10> lma; // Long mode active
784  Bitfield<11> nxe; // No-execute enable
785  Bitfield<12> svme; // Secure virtual machine enable
786  Bitfield<14> ffxsr; // Fast fxsave/fxrstor
787  EndBitUnion(Efer)
788 
789  BitUnion64(Star)
790  Bitfield<31,0> targetEip;
791  Bitfield<47,32> syscallCsAndSs;
792  Bitfield<63,48> sysretCsAndSs;
793  EndBitUnion(Star)
794 
795  BitUnion64(SfMask)
796  Bitfield<31,0> mask;
797  EndBitUnion(SfMask)
798 
799  BitUnion64(PerfEvtSel)
800  Bitfield<7,0> eventMask;
801  Bitfield<15,8> unitMask;
802  Bitfield<16> usr; // User mode
803  Bitfield<17> os; // Operating-system mode
804  Bitfield<18> e; // Edge detect
805  Bitfield<19> pc; // Pin control
806  Bitfield<20> intEn; // Interrupt enable
807  Bitfield<22> en; // Counter enable
808  Bitfield<23> inv; // Invert mask
809  Bitfield<31,24> counterMask;
810  EndBitUnion(PerfEvtSel)
811 
812  BitUnion32(Syscfg)
813  Bitfield<18> mfde; // MtrrFixDramEn
814  Bitfield<19> mfdm; // MtrrFixDramModEn
815  Bitfield<20> mvdm; // MtrrVarDramEn
816  Bitfield<21> tom2; // MtrrTom2En
817  EndBitUnion(Syscfg)
818 
819  BitUnion64(IorrBase)
820  Bitfield<3> wr; // WrMem Enable
821  Bitfield<4> rd; // RdMem Enable
822  Bitfield<51,12> physbase; // Range physical base address
823  EndBitUnion(IorrBase)
824 
825  BitUnion64(IorrMask)
826  Bitfield<11> v; // I/O register pair enable (valid)
827  Bitfield<51,12> physmask; // Range physical mask
828  EndBitUnion(IorrMask)
829 
830  BitUnion64(Tom)
831  Bitfield<51,23> physAddr; // Top of memory physical address
832  EndBitUnion(Tom)
833 
834  BitUnion64(VmCrMsr)
835  Bitfield<0> dpd;
836  Bitfield<1> rInit;
837  Bitfield<2> disA20M;
838  EndBitUnion(VmCrMsr)
839 
840  BitUnion64(IgnneMsr)
841  Bitfield<0> ignne;
842  EndBitUnion(IgnneMsr)
843 
844  BitUnion64(SmmCtlMsr)
845  Bitfield<0> dismiss;
846  Bitfield<1> enter;
847  Bitfield<2> smiCycle;
848  Bitfield<3> exit;
849  Bitfield<4> rsmCycle;
850  EndBitUnion(SmmCtlMsr)
851 
855  BitUnion64(SegSelector)
856  // The following bitfield is not defined in the ISA, but it's useful
857  // when checking selectors in larger data types to make sure they
858  // aren't too large.
859  Bitfield<63, 3> esi; // Extended selector
860  Bitfield<15, 3> si; // Selector Index
861  Bitfield<2> ti; // Table Indicator
862  Bitfield<1, 0> rpl; // Requestor Privilege Level
863  EndBitUnion(SegSelector)
864 
869  class SegDescriptorBase
870  {
871  public:
872  uint32_t
873  getter(const uint64_t &storage) const
874  {
875  return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16);
876  }
877 
878  void
879  setter(uint64_t &storage, uint32_t base)
880  {
881  replaceBits(storage, 63, 56, bits(base, 31, 24));
882  replaceBits(storage, 39, 16, bits(base, 23, 0));
883  }
884  };
885 
887  {
888  public:
889  uint32_t
890  getter(const uint64_t &storage) const
891  {
892  uint32_t limit = (bits(storage, 51, 48) << 16) |
893  bits(storage, 15, 0);
894  if (bits(storage, 55))
895  limit = (limit << 12) | mask(12);
896  return limit;
897  }
898 
899  void
900  setter(uint64_t &storage, uint32_t limit)
901  {
902  bool g = (bits(limit, 31, 24) != 0);
903  panic_if(g && bits(limit, 11, 0) != mask(12),
904  "Inlimitid segment limit %#x", limit);
905  if (g)
906  limit = limit >> 12;
907  replaceBits(storage, 51, 48, bits(limit, 23, 16));
908  replaceBits(storage, 15, 0, bits(limit, 15, 0));
909  replaceBits(storage, 55, g ? 1 : 0);
910  }
911  };
912 
913  BitUnion64(SegDescriptor)
914  Bitfield<63, 56> baseHigh;
915  Bitfield<39, 16> baseLow;
916  BitfieldType<SegDescriptorBase> base;
917  Bitfield<55> g; // Granularity
918  Bitfield<54> d; // Default Operand Size
919  Bitfield<54> b; // Default Operand Size
920  Bitfield<53> l; // Long Attribute Bit
921  Bitfield<52> avl; // Available To Software
922  Bitfield<51, 48> limitHigh;
923  Bitfield<15, 0> limitLow;
925  Bitfield<47> p; // Present
926  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
927  Bitfield<44> s; // System
928  SubBitUnion(type, 43, 40)
929  // Specifies whether this descriptor is for code or data.
930  Bitfield<43> codeOrData;
931 
932  // These bit fields are for code segments
933  Bitfield<42> c; // Conforming
934  Bitfield<41> r; // Readable
935 
936  // These bit fields are for data segments
937  Bitfield<42> e; // Expand-Down
938  Bitfield<41> w; // Writable
939 
940  // This is used for both code and data segments.
941  Bitfield<40> a; // Accessed
943  EndBitUnion(SegDescriptor)
944 
949  BitUnion64(TSSlow)
950  Bitfield<63, 56> baseHigh;
951  Bitfield<39, 16> baseLow;
952  BitfieldType<SegDescriptorBase> base;
953  Bitfield<55> g; // Granularity
954  Bitfield<52> avl; // Available To Software
955  Bitfield<51, 48> limitHigh;
956  Bitfield<15, 0> limitLow;
958  Bitfield<47> p; // Present
959  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
960  SubBitUnion(type, 43, 40)
961  // Specifies whether this descriptor is for code or data.
962  Bitfield<43> codeOrData;
963 
964  // These bit fields are for code segments
965  Bitfield<42> c; // Conforming
966  Bitfield<41> r; // Readable
967 
968  // These bit fields are for data segments
969  Bitfield<42> e; // Expand-Down
970  Bitfield<41> w; // Writable
971 
972  // This is used for both code and data segments.
973  Bitfield<40> a; // Accessed
975  EndBitUnion(TSSlow)
976 
981  BitUnion64(TSShigh)
982  Bitfield<31, 0> base;
983  EndBitUnion(TSShigh)
984 
985  BitUnion64(SegAttr)
986  Bitfield<1, 0> dpl;
987  Bitfield<2> unusable;
988  Bitfield<3> defaultSize;
989  Bitfield<4> longMode;
990  Bitfield<5> avl;
991  Bitfield<6> granularity;
992  Bitfield<7> present;
993  Bitfield<11, 8> type;
994  Bitfield<12> writable;
995  Bitfield<13> readable;
996  Bitfield<14> expandDown;
997  Bitfield<15> system;
998  EndBitUnion(SegAttr)
999 
1000  BitUnion64(GateDescriptor)
1001  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1002  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1003  Bitfield<31, 16> selector; // Target Code-Segment Selector
1004  Bitfield<47> p; // Present
1005  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1006  Bitfield<43, 40> type;
1007  Bitfield<36, 32> count; // Parameter Count
1008  EndBitUnion(GateDescriptor)
1009 
1013  BitUnion64(GateDescriptorLow)
1014  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1015  Bitfield<47> p; // Present
1016  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1017  Bitfield<43, 40> type;
1018  Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling
1019  Bitfield<31, 16> selector; // Target Code-Segment Selector
1020  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1021  EndBitUnion(GateDescriptorLow)
1022 
1023  BitUnion64(GateDescriptorHigh)
1024  Bitfield<31, 0> offset; // Target Code-Segment Offset
1025  EndBitUnion(GateDescriptorHigh)
1026 
1030  BitUnion64(GDTR)
1031  EndBitUnion(GDTR)
1032 
1033  BitUnion64(IDTR)
1034  EndBitUnion(IDTR)
1035 
1036  BitUnion64(LDTR)
1037  EndBitUnion(LDTR)
1038 
1042  BitUnion64(TR)
1043  EndBitUnion(TR)
1044 
1045 
1049  BitUnion64(LocalApicBase)
1050  Bitfield<51, 12> base;
1051  Bitfield<11> enable;
1052  Bitfield<8> bsp;
1053  EndBitUnion(LocalApicBase)
1054 }
1055 
1056 #endif // __ARCH_X86_INTREGS_HH__
X86ISA::MISCREG_FOSEG
@ MISCREG_FOSEG
Definition: misc.hh:387
X86ISA::l
Bitfield< 53 > l
Definition: misc.hh:920
X86ISA::vip
Bitfield< 20 > vip
Definition: misc.hh:559
X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:137
X86ISA::s
Bitfield< 44 > s
Definition: misc.hh:927
X86ISA::MISCREG_MTRR_PHYS_BASE_6
@ MISCREG_MTRR_PHYS_BASE_6
Definition: misc.hh:169
X86ISA::MISCREG_HS
@ MISCREG_HS
Definition: misc.hh:302
X86ISA::MISCREG_MC_MISC_BASE
@ MISCREG_MC_MISC_BASE
Definition: misc.hh:233
X86ISA::cd
Bitfield< 30 > cd
Definition: misc.hh:595
X86ISA::MISCREG_MC_MISC_END
@ MISCREG_MC_MISC_END
Definition: misc.hh:242
X86ISA::MISCREG_SMM_CTL
@ MISCREG_SMM_CTL
Definition: misc.hh:288
X86ISA::MISCREG_FS_ATTR
@ MISCREG_FS_ATTR
Definition: misc.hh:366
X86ISA::MISCREG_MTRR_FIX_4K_D8000
@ MISCREG_MTRR_FIX_4K_D8000
Definition: misc.hh:190
X86ISA::lme
Bitfield< 8 > lme
Definition: misc.hh:782
X86ISA::esi
esi
Definition: misc.hh:859
X86ISA::intEn
Bitfield< 20 > intEn
Definition: misc.hh:806
X86ISA::MISCREG_MTRR_PHYS_MASK
static MiscRegIndex MISCREG_MTRR_PHYS_MASK(int index)
Definition: misc.hh:433
X86ISA::OFBit
@ OFBit
Definition: misc.hh:63
x86_traits.hh
X86ISA::r
Bitfield< 41 > r
Definition: misc.hh:934
X86ISA::ge
Bitfield< 9 > ge
Definition: misc.hh:665
X86ISA::pcc
Bitfield< 57 > pcc
Definition: misc.hh:763
X86ISA::MISCREG_CR10
@ MISCREG_CR10
Definition: misc.hh:115
X86ISA::SubBitUnion
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
X86ISA::limitHigh
Bitfield< 51, 48 > limitHigh
Definition: misc.hh:922
X86ISA::MISCREG_IORR_BASE0
@ MISCREG_IORR_BASE0
Definition: misc.hh:274
X86ISA::mvdm
Bitfield< 20 > mvdm
Definition: misc.hh:815
X86ISA::BitUnion32
BitUnion32(TriggerIntMessage) Bitfield< 7
X86ISA::MISCREG_PERF_EVT_SEL
static MiscRegIndex MISCREG_PERF_EVT_SEL(int index)
Definition: misc.hh:473
X86ISA::MISCREG_MCG_CAP
@ MISCREG_MCG_CAP
Definition: misc.hh:151
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
X86ISA::MISCREG_DS_LIMIT
@ MISCREG_DS_LIMIT
Definition: misc.hh:349
replaceBits
void replaceBits(T &val, int first, int last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:179
X86ISA::c
Bitfield< 42 > c
Definition: misc.hh:933
X86ISA::unitMask
Bitfield< 15, 8 > unitMask
Definition: misc.hh:801
X86ISA::g1
Bitfield< 3 > g1
Definition: misc.hh:659
X86ISA::MISCREG_PERF_EVT_CTR2
@ MISCREG_PERF_EVT_CTR2
Definition: misc.hh:267
X86ISA::CondFlagBit
CondFlagBit
Definition: misc.hh:54
X86ISA::MISCREG_FOP
@ MISCREG_FOP
Definition: misc.hh:389
X86ISA::MISCREG_MC7_ADDR
@ MISCREG_MC7_ADDR
Definition: misc.hh:230
X86ISA::MISCREG_MC_CTL
static MiscRegIndex MISCREG_MC_CTL(int index)
Definition: misc.hh:441
X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:393
X86ISA::enter
Bitfield< 1 > enter
Definition: misc.hh:846
X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:354
X86ISA::MISCREG_GS_BASE
@ MISCREG_GS_BASE
Definition: misc.hh:317
X86ISA::MISCREG_MC_STATUS_END
@ MISCREG_MC_STATUS_END
Definition: misc.hh:220
X86ISA::writable
Bitfield< 12 > writable
Definition: misc.hh:994
X86ISA::NumCRegs
const int NumCRegs
Definition: x86_traits.hh:61
X86ISA::MISCREG_MTRRCAP
@ MISCREG_MTRRCAP
Definition: misc.hh:145
X86ISA::MISCREG_MC2_MISC
@ MISCREG_MC2_MISC
Definition: misc.hh:236
X86ISA::df
Bitfield< 10 > df
Definition: misc.hh:567
X86ISA::ne
Bitfield< 5 > ne
Definition: misc.hh:599
X86ISA::SFBit
@ SFBit
Definition: misc.hh:61
X86ISA::MISCREG_IORR_MASK
static MiscRegIndex MISCREG_IORR_MASK(int index)
Definition: misc.hh:497
X86ISA::ErrSummaryBit
@ ErrSummaryBit
Definition: misc.hh:92
X86ISA::wp
Bitfield< 16 > wp
Definition: misc.hh:598
X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:860
X86ISA::DEBit
@ DEBit
Definition: misc.hh:84
X86ISA::MISCREG_MTRR_PHYS_MASK_4
@ MISCREG_MTRR_PHYS_MASK_4
Definition: misc.hh:178
X86ISA::fe
Bitfield< 10 > fe
Definition: misc.hh:752
X86ISA::MISCREG_CR_BASE
@ MISCREG_CR_BASE
Definition: misc.hh:104
X86ISA::MISCREG_IDTR_EFF_BASE
@ MISCREG_IDTR_EFF_BASE
Definition: misc.hh:342
X86ISA::MISCREG_ES_BASE
@ MISCREG_ES_BASE
Definition: misc.hh:312
X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:848
X86ISA::MISCREG_LS_LIMIT
@ MISCREG_LS_LIMIT
Definition: misc.hh:355
X86ISA::MISCREG_IDTR
@ MISCREG_IDTR
Definition: misc.hh:308
X86ISA::MISCREG_MS
@ MISCREG_MS
Definition: misc.hh:306
X86ISA::MISCREG_X87_TOP
@ MISCREG_X87_TOP
Definition: misc.hh:377
X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:303
X86ISA::len2
Bitfield< 27, 26 > len2
Definition: misc.hh:672
X86ISA::MISCREG_MC4_MISC
@ MISCREG_MC4_MISC
Definition: misc.hh:238
X86ISA::MISCREG_TR_EFF_BASE
@ MISCREG_TR_EFF_BASE
Definition: misc.hh:341
X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:296
X86ISA::gd
Bitfield< 13 > gd
Definition: misc.hh:666
X86ISA::MISCREG_MC_MISC
static MiscRegIndex MISCREG_MC_MISC(int index)
Definition: misc.hh:465
X86ISA::sysretCsAndSs
Bitfield< 63, 48 > sysretCsAndSs
Definition: misc.hh:792
X86ISA::MISCREG_FISEG
@ MISCREG_FISEG
Definition: misc.hh:385
X86ISA::pf
Bitfield< 2 > pf
Definition: misc.hh:550
X86ISA::MISCREG_LAST_EXCEPTION_FROM_IP
@ MISCREG_LAST_EXCEPTION_FROM_IP
Definition: misc.hh:159
X86ISA::MISCREG_MC_ADDR
static MiscRegIndex MISCREG_MC_ADDR(int index)
Definition: misc.hh:457
X86ISA::MISCREG_TOP_MEM2
@ MISCREG_TOP_MEM2
Definition: misc.hh:284
X86ISA::MISCREG_MCG_CTL
@ MISCREG_MCG_CTL
Definition: misc.hh:153
X86ISA::MISCREG_TR_LIMIT
@ MISCREG_TR_LIMIT
Definition: misc.hh:357
X86ISA::MISCREG_MC7_STATUS
@ MISCREG_MC7_STATUS
Definition: misc.hh:219
X86ISA::len0
Bitfield< 19, 18 > len0
Definition: misc.hh:668
X86ISA::vif
Bitfield< 19 > vif
Definition: misc.hh:560
X86ISA::ac
Bitfield< 18 > ac
Definition: misc.hh:561
X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:297
X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:992
X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
X86ISA::MISCREG_IDTR_ATTR
@ MISCREG_IDTR_ATTR
Definition: misc.hh:374
X86ISA::pb3
Bitfield< 5 > pb3
Definition: misc.hh:719
X86ISA::nxe
Bitfield< 11 > nxe
Definition: misc.hh:784
X86ISA::rw3
Bitfield< 29, 28 > rw3
Definition: misc.hh:673
X86ISA::SegDescriptorLimit::setter
void setter(uint64_t &storage, uint32_t limit)
Definition: misc.hh:900
X86ISA::MISCREG_MTRR_PHYS_MASK_3
@ MISCREG_MTRR_PHYS_MASK_3
Definition: misc.hh:177
X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:526
X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:638
X86ISA::MISCREG_MTRR_FIX_16K_A0000
@ MISCREG_MTRR_FIX_16K_A0000
Definition: misc.hh:186
X86ISA::ts
Bitfield< 3 > ts
Definition: misc.hh:601
X86ISA::bt
Bitfield< 15 > bt
Definition: misc.hh:652
X86ISA::altOp
Bitfield< 11, 10 > altOp
Definition: misc.hh:584
X86ISA::MCGCP
Bitfield< 8 > MCGCP
Definition: misc.hh:704
X86ISA::le
Bitfield< 8 > le
Definition: misc.hh:664
X86ISA::MISCREG_MS_ATTR
@ MISCREG_MS_ATTR
Definition: misc.hh:372
X86ISA::MISCREG_PERF_EVT_SEL3
@ MISCREG_PERF_EVT_SEL3
Definition: misc.hh:261
X86ISA::bd
Bitfield< 13 > bd
Definition: misc.hh:650
X86ISA::smiCycle
Bitfield< 2 > smiCycle
Definition: misc.hh:847
X86ISA::IDBit
@ IDBit
Definition: misc.hh:78
X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:107
X86ISA::MISCREG_PERF_EVT_SEL2
@ MISCREG_PERF_EVT_SEL2
Definition: misc.hh:260
X86ISA::MISCREG_ES_EFF_BASE
@ MISCREG_ES_EFF_BASE
Definition: misc.hh:330
X86ISA::ffxsr
Bitfield< 14 > ffxsr
Definition: misc.hh:786
X86ISA::MISCREG_SYSENTER_CS
@ MISCREG_SYSENTER_CS
Definition: misc.hh:147
X86ISA::MISCREG_MTRR_PHYS_MASK_BASE
@ MISCREG_MTRR_PHYS_MASK_BASE
Definition: misc.hh:173
X86ISA::MISCREG_IGNNE
@ MISCREG_IGNNE
Definition: misc.hh:287
X86ISA::BusyBit
@ BusyBit
Definition: misc.hh:97
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
X86ISA::MISCREG_VM_HSAVE_PA
@ MISCREG_VM_HSAVE_PA
Definition: misc.hh:289
X86ISA::paging
Bitfield< 6 > paging
Definition: misc.hh:581
X86ISA::tf
Bitfield< 8 > tf
Definition: misc.hh:569
X86ISA::CC0Bit
@ CC0Bit
Definition: misc.hh:93
X86ISA::MISCREG_MTRR_PHYS_BASE_3
@ MISCREG_MTRR_PHYS_BASE_3
Definition: misc.hh:166
X86ISA::MISCREG_MTRR_PHYS_BASE_0
@ MISCREG_MTRR_PHYS_BASE_0
Definition: misc.hh:163
X86ISA::X87StatusBit
X87StatusBit
Definition: misc.hh:81
X86ISA::count
count
Definition: misc.hh:703
X86ISA::MISCREG_DEF_TYPE
@ MISCREG_DEF_TYPE
Definition: misc.hh:198
X86ISA::MISCREG_CSTAR
@ MISCREG_CSTAR
Definition: misc.hh:249
X86ISA::MISCREG_CR13
@ MISCREG_CR13
Definition: misc.hh:118
X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:245
X86ISA::wc
Bitfield< 10 > wc
Definition: misc.hh:681
X86ISA::MISCREG_PERF_EVT_CTR3
@ MISCREG_PERF_EVT_CTR3
Definition: misc.hh:268
X86ISA::MISCREG_MTRR_PHYS_MASK_7
@ MISCREG_MTRR_PHYS_MASK_7
Definition: misc.hh:181
X86ISA::MISCREG_MTRR_PHYS_MASK_2
@ MISCREG_MTRR_PHYS_MASK_2
Definition: misc.hh:176
X86ISA::MISCREG_DR1
@ MISCREG_DR1
Definition: misc.hh:125
X86ISA::MISCREG_CR14
@ MISCREG_CR14
Definition: misc.hh:119
X86ISA::MISCREG_PERF_EVT_SEL1
@ MISCREG_PERF_EVT_SEL1
Definition: misc.hh:259
X86ISA::MISCREG_MS_BASE
@ MISCREG_MS_BASE
Definition: misc.hh:322
X86ISA::defaultSize
Bitfield< 3 > defaultSize
Definition: misc.hh:988
X86ISA::svme
Bitfield< 12 > svme
Definition: misc.hh:785
X86ISA::cpl
Bitfield< 5, 4 > cpl
Definition: misc.hh:580
X86ISA::MISCREG_LAST_BRANCH_FROM_IP
@ MISCREG_LAST_BRANCH_FROM_IP
Definition: misc.hh:157
X86ISA::ECFBit
@ ECFBit
Definition: misc.hh:57
X86ISA::physAddr
physAddr
Definition: misc.hh:831
X86ISA::MISCREG_LS_BASE
@ MISCREG_LS_BASE
Definition: misc.hh:321
X86ISA::EndSubBitUnion
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
X86ISA::MISCREG_MC5_STATUS
@ MISCREG_MC5_STATUS
Definition: misc.hh:217
X86ISA::fsgsbase
Bitfield< 16 > fsgsbase
Definition: misc.hh:625
X86ISA::MISCREG_MTRR_FIX_4K_D0000
@ MISCREG_MTRR_FIX_4K_D0000
Definition: misc.hh:189
X86ISA::v
Bitfield< 6, 3 > v
Definition: types.hh:120
X86ISA::vm
Bitfield< 17 > vm
Definition: misc.hh:562
X86ISA::granularity
Bitfield< 6 > granularity
Definition: misc.hh:991
X86ISA::stack
Bitfield< 17, 16 > stack
Definition: misc.hh:587
X86ISA::af
Bitfield< 4 > af
Definition: misc.hh:548
X86ISA::MISCREG_HS_LIMIT
@ MISCREG_HS_LIMIT
Definition: misc.hh:352
X86ISA::pwt
Bitfield< 3 > pwt
Definition: pagetable.hh:148
X86ISA::MISCREG_MC3_CTL
@ MISCREG_MC3_CTL
Definition: misc.hh:204
X86ISA::MISCREG_TSG_ATTR
@ MISCREG_TSG_ATTR
Definition: misc.hh:370
X86ISA::MISCREG_IORR_MASK_END
@ MISCREG_IORR_MASK_END
Definition: misc.hh:281
X86ISA::targetESP
targetESP
Definition: misc.hh:692
X86ISA::MISCREG_TR_ATTR
@ MISCREG_TR_ATTR
Definition: misc.hh:373
X86ISA::rsmCycle
Bitfield< 4 > rsmCycle
Definition: misc.hh:849
X86ISA::MISCREG_SEG_SEL
static MiscRegIndex MISCREG_SEG_SEL(int index)
Definition: misc.hh:505
X86ISA::MISCREG_TR_BASE
@ MISCREG_TR_BASE
Definition: misc.hh:323
X86ISA::offsetLow
Bitfield< 15, 0 > offsetLow
Definition: misc.hh:1002
X86ISA::addrv
Bitfield< 58 > addrv
Definition: misc.hh:764
X86ISA::et
Bitfield< 4 > et
Definition: misc.hh:600
X86ISA::MISCREG_MTRR_FIX_16K_80000
@ MISCREG_MTRR_FIX_16K_80000
Definition: misc.hh:185
X86ISA::pb2
Bitfield< 4 > pb2
Definition: misc.hh:718
X86ISA::targetEip
targetEip
Definition: misc.hh:790
X86ISA::MISCREG_STAR
@ MISCREG_STAR
Definition: misc.hh:247
X86ISA::MISCREG_MTRR_PHYS_BASE_5
@ MISCREG_MTRR_PHYS_BASE_5
Definition: misc.hh:168
X86ISA::MISCREG_MC5_MISC
@ MISCREG_MC5_MISC
Definition: misc.hh:239
X86ISA::rw0
Bitfield< 17, 16 > rw0
Definition: misc.hh:667
X86ISA::MISCREG_MCG_STATUS
@ MISCREG_MCG_STATUS
Definition: misc.hh:152
X86ISA::MISCREG_DS_EFF_BASE
@ MISCREG_DS_EFF_BASE
Definition: misc.hh:333
X86ISA::pse
Bitfield< 4 > pse
Definition: misc.hh:634
X86ISA::MISCREG_DR_BASE
@ MISCREG_DR_BASE
Definition: misc.hh:123
X86ISA::MISCREG_MTRR_PHYS_BASE_7
@ MISCREG_MTRR_PHYS_BASE_7
Definition: misc.hh:170
X86ISA::MISCREG_SYSENTER_EIP
@ MISCREG_SYSENTER_EIP
Definition: misc.hh:149
X86ISA::MISCREG_SEG_EFF_BASE_BASE
@ MISCREG_SEG_EFF_BASE_BASE
Definition: misc.hh:329
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
X86ISA::MISCREG_MC_CTL_BASE
@ MISCREG_MC_CTL_BASE
Definition: misc.hh:200
X86ISA::inv
Bitfield< 23 > inv
Definition: misc.hh:808
X86ISA::physbase
Bitfield< 51, 12 > physbase
Definition: misc.hh:728
X86ISA::longPdtb
longPdtb
Definition: misc.hh:613
X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:299
X86ISA::nw
Bitfield< 29 > nw
Definition: misc.hh:596
X86ISA::MISCREG_TSC_AUX
@ MISCREG_TSC_AUX
Definition: misc.hh:255
X86ISA::physmask
Bitfield< 51, 12 > physmask
Definition: misc.hh:733
X86ISA::expandDown
Bitfield< 14 > expandDown
Definition: misc.hh:996
X86ISA::MISCREG_CR1
@ MISCREG_CR1
Definition: misc.hh:106
X86ISA::MISCREG_DR5
@ MISCREG_DR5
Definition: misc.hh:129
X86ISA::MISCREG_CR7
@ MISCREG_CR7
Definition: misc.hh:112
X86ISA::MISCREG_MC3_STATUS
@ MISCREG_MC3_STATUS
Definition: misc.hh:215
X86ISA::MISCREG_SYSENTER_ESP
@ MISCREG_SYSENTER_ESP
Definition: misc.hh:148
X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:109
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:93
X86ISA::len3
Bitfield< 31, 30 > len3
Definition: misc.hh:674
X86ISA::g2
Bitfield< 5 > g2
Definition: misc.hh:661
X86ISA::altAddr
Bitfield< 15, 14 > altAddr
Definition: misc.hh:586
X86ISA::VIFBit
@ VIFBit
Definition: misc.hh:76
X86ISA::TFBit
@ TFBit
Definition: misc.hh:70
X86ISA::MISCREG_CR5
@ MISCREG_CR5
Definition: misc.hh:110
X86ISA::MISCREG_MC0_STATUS
@ MISCREG_MC0_STATUS
Definition: misc.hh:212
X86ISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:398
X86ISA::MISCREG_SS_ATTR
@ MISCREG_SS_ATTR
Definition: misc.hh:364
X86ISA::MISCREG_FS_LIMIT
@ MISCREG_FS_LIMIT
Definition: misc.hh:350
X86ISA::MISCREG_TOP_MEM
@ MISCREG_TOP_MEM
Definition: misc.hh:283
X86ISA::dpl
Bitfield< 46, 45 > dpl
Definition: misc.hh:926
X86ISA::MISCREG_MTRR_PHYS_BASE_END
@ MISCREG_MTRR_PHYS_BASE_END
Definition: misc.hh:171
X86ISA::MISCREG_MC2_CTL
@ MISCREG_MC2_CTL
Definition: misc.hh:203
X86ISA::am
Bitfield< 18 > am
Definition: misc.hh:597
X86ISA::b2
Bitfield< 2 > b2
Definition: misc.hh:648
X86ISA::MISCREG_SEG_SEL_BASE
@ MISCREG_SEG_SEL_BASE
Definition: misc.hh:295
X86ISA::MISCREG_CR
static MiscRegIndex MISCREG_CR(int index)
Definition: misc.hh:411
X86ISA::rw1
Bitfield< 21, 20 > rw1
Definition: misc.hh:669
X86ISA::MISCREG_RFLAGS
@ MISCREG_RFLAGS
Definition: misc.hh:134
X86ISA::readable
Bitfield< 13 > readable
Definition: misc.hh:995
X86ISA::MISCREG_MC_CTL_END
@ MISCREG_MC_CTL_END
Definition: misc.hh:209
X86ISA::MISCREG_VM_CR
@ MISCREG_VM_CR
Definition: misc.hh:286
X86ISA::MISCREG_SEG_LIMIT_BASE
@ MISCREG_SEG_LIMIT_BASE
Definition: misc.hh:345
X86ISA::MISCREG_IORR_BASE_BASE
@ MISCREG_IORR_BASE_BASE
Definition: misc.hh:273
X86ISA::MISCREG_MTRR_FIX_4K_E8000
@ MISCREG_MTRR_FIX_4K_E8000
Definition: misc.hh:192
X86ISA::MISCREG_DS_ATTR
@ MISCREG_DS_ATTR
Definition: misc.hh:365
X86ISA::MISCREG_HS_BASE
@ MISCREG_HS_BASE
Definition: misc.hh:318
X86ISA::counterMask
Bitfield< 31, 24 > counterMask
Definition: misc.hh:809
X86ISA::nt
Bitfield< 14 > nt
Definition: misc.hh:564
X86ISA::MISCREG_MTRR_FIX_64K_00000
@ MISCREG_MTRR_FIX_64K_00000
Definition: misc.hh:184
segment.hh
X86ISA::PEBit
@ PEBit
Definition: misc.hh:88
X86ISA::sf
Bitfield< 7 > sf
Definition: misc.hh:545
X86ISA::MISCREG_DR7
@ MISCREG_DR7
Definition: misc.hh:131
X86ISA::MISCREG_GS_EFF_BASE
@ MISCREG_GS_EFF_BASE
Definition: misc.hh:335
X86ISA::IEBit
@ IEBit
Definition: misc.hh:83
X86ISA::targetEIP
targetEIP
Definition: misc.hh:696
X86ISA::MISCREG_DS_BASE
@ MISCREG_DS_BASE
Definition: misc.hh:315
bitunion.hh
X86ISA::zf
Bitfield< 6 > zf
Definition: misc.hh:546
X86ISA::MISCREG_MC2_STATUS
@ MISCREG_MC2_STATUS
Definition: misc.hh:214
X86ISA::MISCREG_DEBUG_CTL_MSR
@ MISCREG_DEBUG_CTL_MSR
Definition: misc.hh:155
X86ISA::MISCREG_IORR_MASK_BASE
@ MISCREG_IORR_MASK_BASE
Definition: misc.hh:278
X86ISA::MISCREG_MTRR_PHYS_MASK_6
@ MISCREG_MTRR_PHYS_MASK_6
Definition: misc.hh:180
X86ISA::MISCREG_IORR_MASK1
@ MISCREG_IORR_MASK1
Definition: misc.hh:280
X86ISA::MISCREG_MC1_STATUS
@ MISCREG_MC1_STATUS
Definition: misc.hh:213
X86ISA::over
Bitfield< 62 > over
Definition: misc.hh:768
X86ISA::MISCREG_SS_EFF_BASE
@ MISCREG_SS_EFF_BASE
Definition: misc.hh:332
X86ISA::MISCREG_PERF_EVT_SEL_END
@ MISCREG_PERF_EVT_SEL_END
Definition: misc.hh:262
X86ISA::OEBit
@ OEBit
Definition: misc.hh:86
X86ISA::l2
Bitfield< 4 > l2
Definition: misc.hh:660
X86ISA::MISCREG_MC0_MISC
@ MISCREG_MC0_MISC
Definition: misc.hh:234
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
X86ISA::ccFlagMask
const uint32_t ccFlagMask
Definition: misc.hh:67
X86ISA::CC1Bit
@ CC1Bit
Definition: misc.hh:94
X86ISA::b1
Bitfield< 1 > b1
Definition: misc.hh:647
X86ISA::b3
Bitfield< 3 > b3
Definition: misc.hh:649
X86ISA::MISCREG_LAST_EXCEPTION_TO_IP
@ MISCREG_LAST_EXCEPTION_TO_IP
Definition: misc.hh:160
X86ISA::syscallCsAndSs
Bitfield< 47, 32 > syscallCsAndSs
Definition: misc.hh:791
X86ISA::MISCREG_MTRR_FIX_4K_E0000
@ MISCREG_MTRR_FIX_4K_E0000
Definition: misc.hh:191
X86ISA::mce
Bitfield< 6 > mce
Definition: misc.hh:632
X86ISA::VMBit
@ VMBit
Definition: misc.hh:74
X86ISA::MISCREG_CS_EFF_BASE
@ MISCREG_CS_EFF_BASE
Definition: misc.hh:331
X86ISA::AFBit
@ AFBit
Definition: misc.hh:58
X86ISA::b
Bitfield< 54 > b
Definition: misc.hh:919
X86ISA::prot
Bitfield< 7 > prot
Definition: misc.hh:582
X86ISA::isValidMiscReg
static bool isValidMiscReg(int index)
Definition: misc.hh:402
X86ISA::MISCREG_MC_ADDR_END
@ MISCREG_MC_ADDR_END
Definition: misc.hh:231
X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:563
X86ISA::limitLow
Bitfield< 15, 0 > limitLow
Definition: misc.hh:923
X86ISA::MISCREG_MC6_CTL
@ MISCREG_MC6_CTL
Definition: misc.hh:207
X86ISA::MISCREG_MC5_ADDR
@ MISCREG_MC5_ADDR
Definition: misc.hh:228
X86ISA::em
Bitfield< 2 > em
Definition: misc.hh:602
X86ISA::avl
Bitfield< 11, 9 > avl
Definition: pagetable.hh:142
X86ISA::MISCREG_PERF_EVT_CTR1
@ MISCREG_PERF_EVT_CTR1
Definition: misc.hh:266
X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:533
X86ISA::rw2
Bitfield< 25, 24 > rw2
Definition: misc.hh:671
X86ISA::MISCREG_MC7_CTL
@ MISCREG_MC7_CTL
Definition: misc.hh:208
X86ISA::MISCREG_GS_LIMIT
@ MISCREG_GS_LIMIT
Definition: misc.hh:351
BitfieldType
Definition: bitunion.hh:113
X86ISA::intf
Bitfield< 9 > intf
Definition: misc.hh:568
X86ISA::MISCREG_MS_LIMIT
@ MISCREG_MS_LIMIT
Definition: misc.hh:356
X86ISA::SegDescriptorLimit::getter
uint32_t getter(const uint64_t &storage) const
Definition: misc.hh:890
X86ISA::MISCREG_LS_ATTR
@ MISCREG_LS_ATTR
Definition: misc.hh:371
X86ISA::MISCREG_CR12
@ MISCREG_CR12
Definition: misc.hh:117
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
X86ISA::w
Bitfield< 1 > w
Definition: pagetable.hh:150
X86ISA::VIPBit
@ VIPBit
Definition: misc.hh:77
X86ISA::MISCREG_PCI_CONFIG_ADDRESS
@ MISCREG_PCI_CONFIG_ADDRESS
Definition: misc.hh:396
X86ISA::MISCREG_MTRR_FIX_4K_F8000
@ MISCREG_MTRR_FIX_4K_F8000
Definition: misc.hh:194
X86ISA::fix
Bitfield< 8 > fix
Definition: misc.hh:680
X86ISA::MISCREG_DR4
@ MISCREG_DR4
Definition: misc.hh:128
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::MISCREG_SF_MASK
@ MISCREG_SF_MASK
Definition: misc.hh:251
X86ISA::MISCREG_CS_ATTR
@ MISCREG_CS_ATTR
Definition: misc.hh:363
X86ISA::DFBit
@ DFBit
Definition: misc.hh:62
X86ISA::MISCREG_DR0
@ MISCREG_DR0
Definition: misc.hh:124
X86ISA::MISCREG_CR9
@ MISCREG_CR9
Definition: misc.hh:114
X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:300
X86ISA::MISCREG_MTRR_FIX_4K_C0000
@ MISCREG_MTRR_FIX_4K_C0000
Definition: misc.hh:187
X86ISA::MISCREG_DR3
@ MISCREG_DR3
Definition: misc.hh:127
X86ISA::MISCREG_LSTAR
@ MISCREG_LSTAR
Definition: misc.hh:248
X86ISA::MISCREG_MC6_MISC
@ MISCREG_MC6_MISC
Definition: misc.hh:240
X86ISA::pvi
Bitfield< 1 > pvi
Definition: misc.hh:637
X86ISA::MISCREG_PERF_EVT_SEL_BASE
@ MISCREG_PERF_EVT_SEL_BASE
Definition: misc.hh:257
X86ISA::a
Bitfield< 5 > a
Definition: pagetable.hh:146
X86ISA::StackFaultBit
@ StackFaultBit
Definition: misc.hh:91
X86ISA::MISCREG_FTW
@ MISCREG_FTW
Definition: misc.hh:383
X86ISA::MISCREG_MTRR_FIX_4K_F0000
@ MISCREG_MTRR_FIX_4K_F0000
Definition: misc.hh:193
X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:108
X86ISA::MISCREG_TSG_EFF_BASE
@ MISCREG_TSG_EFF_BASE
Definition: misc.hh:338
X86ISA::offset
offset
Definition: misc.hh:1024
X86ISA::MISCREG_MC4_STATUS
@ MISCREG_MC4_STATUS
Definition: misc.hh:216
X86ISA::legacy
legacy
Definition: misc.hh:609
X86ISA::MISCREG_SYSCFG
@ MISCREG_SYSCFG
Definition: misc.hh:271
X86ISA::MISCREG_MC3_ADDR
@ MISCREG_MC3_ADDR
Definition: misc.hh:226
X86ISA::NumDRegs
const int NumDRegs
Definition: x86_traits.hh:62
X86ISA::CFBit
@ CFBit
Definition: misc.hh:55
X86ISA::longMode
Bitfield< 4 > longMode
Definition: misc.hh:989
X86ISA::MISCREG_MC5_CTL
@ MISCREG_MC5_CTL
Definition: misc.hh:206
X86ISA::PFBit
@ PFBit
Definition: misc.hh:56
X86ISA::mcaErrorCode
mcaErrorCode
Definition: misc.hh:760
X86ISA::MISCREG_MC4_ADDR
@ MISCREG_MC4_ADDR
Definition: misc.hh:227
X86ISA::MISCREG_MTRR_PHYS_BASE
static MiscRegIndex MISCREG_MTRR_PHYS_BASE(int index)
Definition: misc.hh:425
X86ISA::pae
Bitfield< 5 > pae
Definition: misc.hh:633
X86ISA::MISCREG_IORR_BASE_END
@ MISCREG_IORR_BASE_END
Definition: misc.hh:276
X86ISA::btf
Bitfield< 1 > btf
Definition: misc.hh:715
X86ISA::MISCREG_MC6_ADDR
@ MISCREG_MC6_ADDR
Definition: misc.hh:229
X86ISA::de
Bitfield< 3 > de
Definition: misc.hh:635
X86ISA::offsetHigh
offsetHigh
Definition: misc.hh:1001
X86ISA::MISCREG_DR2
@ MISCREG_DR2
Definition: misc.hh:126
X86ISA::MISCREG_MC0_ADDR
@ MISCREG_MC0_ADDR
Definition: misc.hh:223
X86ISA::MISCREG_HS_ATTR
@ MISCREG_HS_ATTR
Definition: misc.hh:368
X86ISA::pge
Bitfield< 7 > pge
Definition: misc.hh:631
X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:519
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:298
X86ISA::vcnt
vcnt
Definition: misc.hh:679
X86ISA::MISCREG_DR6
@ MISCREG_DR6
Definition: misc.hh:130
X86ISA::MISCREG_ES_LIMIT
@ MISCREG_ES_LIMIT
Definition: misc.hh:346
X86ISA::SegDescriptorLimit
Definition: misc.hh:886
X86ISA::MISCREG_MTRR_FIX_4K_C8000
@ MISCREG_MTRR_FIX_4K_C8000
Definition: misc.hh:188
X86ISA::MISCREG_MC3_MISC
@ MISCREG_MC3_MISC
Definition: misc.hh:237
X86ISA::IFBit
@ IFBit
Definition: misc.hh:71
X86ISA::g3
Bitfield< 7 > g3
Definition: misc.hh:663
X86ISA::MISCREG_HS_EFF_BASE
@ MISCREG_HS_EFF_BASE
Definition: misc.hh:336
X86ISA::cf
Bitfield< 0 > cf
Definition: misc.hh:551
X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:62
X86ISA::eventMask
eventMask
Definition: misc.hh:800
X86ISA::RFLAGBit
RFLAGBit
Definition: misc.hh:69
X86ISA::bs
Bitfield< 14 > bs
Definition: misc.hh:651
X86ISA::rInit
Bitfield< 1 > rInit
Definition: misc.hh:836
X86ISA::osxmmexcpt
Bitfield< 10 > osxmmexcpt
Definition: misc.hh:627
X86ISA::MISCREG_MC1_ADDR
@ MISCREG_MC1_ADDR
Definition: misc.hh:224
X86ISA::MISCREG_SS_LIMIT
@ MISCREG_SS_LIMIT
Definition: misc.hh:348
X86ISA::l1
Bitfield< 2 > l1
Definition: misc.hh:658
X86ISA::eipv
Bitfield< 1 > eipv
Definition: misc.hh:709
X86ISA::targetCS
targetCS
Definition: misc.hh:688
X86ISA::MISCREG_MC7_MISC
@ MISCREG_MC7_MISC
Definition: misc.hh:241
X86ISA::MISCREG_MC0_CTL
@ MISCREG_MC0_CTL
Definition: misc.hh:201
X86ISA::defOp
Bitfield< 9, 8 > defOp
Definition: misc.hh:583
X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
X86ISA::pb0
Bitfield< 2 > pb0
Definition: misc.hh:716
X86ISA::rpl
Bitfield< 1, 0 > rpl
Definition: misc.hh:862
X86ISA::MISCREG_TSL_EFF_BASE
@ MISCREG_TSL_EFF_BASE
Definition: misc.hh:337
X86ISA::baseHigh
baseHigh
Definition: misc.hh:914
X86ISA::MISCREG_LS
@ MISCREG_LS
Definition: misc.hh:305
X86ISA::MISCREG_MC_STATUS
static MiscRegIndex MISCREG_MC_STATUS(int index)
Definition: misc.hh:449
X86ISA::g0
Bitfield< 1 > g0
Definition: misc.hh:657
X86ISA::MISCREG_MS_EFF_BASE
@ MISCREG_MS_EFF_BASE
Definition: misc.hh:340
X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1051
X86ISA::MISCREG_PERF_EVT_SEL0
@ MISCREG_PERF_EVT_SEL0
Definition: misc.hh:258
X86ISA::iopl
Bitfield< 13, 12 > iopl
Definition: misc.hh:565
X86ISA::MISCREG_SEG_ATTR_BASE
@ MISCREG_SEG_ATTR_BASE
Definition: misc.hh:361
X86ISA::pe
Bitfield< 0 > pe
Definition: misc.hh:604
X86ISA::d
Bitfield< 6 > d
Definition: pagetable.hh:145
X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) namespace DeliveryMode
Definition: intmessage.hh:49
X86ISA::MISCREG_CS_LIMIT
@ MISCREG_CS_LIMIT
Definition: misc.hh:347
X86ISA::pce
Bitfield< 8 > pce
Definition: misc.hh:630
X86ISA::paePdtb
Bitfield< 31, 5 > paePdtb
Definition: misc.hh:617
X86ISA::MISCREG_FS_EFF_BASE
@ MISCREG_FS_EFF_BASE
Definition: misc.hh:334
X86ISA::MISCREG_FIOFF
@ MISCREG_FIOFF
Definition: misc.hh:386
X86ISA::pcd
Bitfield< 4 > pcd
Definition: pagetable.hh:147
X86ISA::mp
Bitfield< 1 > mp
Definition: misc.hh:603
X86ISA::MISCREG_MTRR_PHYS_BASE_1
@ MISCREG_MTRR_PHYS_BASE_1
Definition: misc.hh:164
X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:105
X86ISA::rd
Bitfield< 4 > rd
Definition: misc.hh:821
X86ISA::MISCREG_LAST_BRANCH_TO_IP
@ MISCREG_LAST_BRANCH_TO_IP
Definition: misc.hh:158
X86ISA::MISCREG_IORR_MASK0
@ MISCREG_IORR_MASK0
Definition: misc.hh:279
X86ISA::MISCREG_IORR_BASE1
@ MISCREG_IORR_BASE1
Definition: misc.hh:275
X86ISA::MISCREG_IORR_BASE
static MiscRegIndex MISCREG_IORR_BASE(int index)
Definition: misc.hh:489
X86ISA::pdtb
Bitfield< 31, 12 > pdtb
Definition: misc.hh:615
X86ISA::MISCREG_MTRR_PHYS_BASE_BASE
@ MISCREG_MTRR_PHYS_BASE_BASE
Definition: misc.hh:162
logging.hh
X86ISA::IST
Bitfield< 35, 32 > IST
Definition: misc.hh:1018
X86ISA::MISCREG_TSL_LIMIT
@ MISCREG_TSL_LIMIT
Definition: misc.hh:353
X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:307
X86ISA::modelSpecificCode
Bitfield< 31, 16 > modelSpecificCode
Definition: misc.hh:761
X86ISA::selector
Bitfield< 31, 16 > selector
Definition: misc.hh:1003
MipsISA::wr
Bitfield< 3 > wr
Definition: pra_constants.hh:241
X86ISA::limit
BitfieldType< SegDescriptorLimit > limit
Definition: misc.hh:924
X86ISA::lma
Bitfield< 10 > lma
Definition: misc.hh:783
X86ISA::CC2Bit
@ CC2Bit
Definition: misc.hh:95
X86ISA::ACBit
@ ACBit
Definition: misc.hh:75
X86ISA::MISCREG_FTAG
@ MISCREG_FTAG
Definition: misc.hh:384
X86ISA::pb1
Bitfield< 3 > pb1
Definition: misc.hh:717
X86ISA::MISCREG_PERF_EVT_CTR0
@ MISCREG_PERF_EVT_CTR0
Definition: misc.hh:265
X86ISA::MISCREG_MC1_MISC
@ MISCREG_MC1_MISC
Definition: misc.hh:235
X86ISA::miscv
Bitfield< 59 > miscv
Definition: misc.hh:765
X86ISA::tsd
Bitfield< 2 > tsd
Definition: misc.hh:636
X86ISA::mask
mask
Definition: misc.hh:796
X86ISA::MISCREG_IDTR_BASE
@ MISCREG_IDTR_BASE
Definition: misc.hh:324
X86ISA::type
type
Definition: misc.hh:727
X86ISA::e
Bitfield< 11 > e
Definition: misc.hh:753
X86ISA::MISCREG_GS_ATTR
@ MISCREG_GS_ATTR
Definition: misc.hh:367
X86ISA::NTBit
@ NTBit
Definition: misc.hh:72
X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:512
X86ISA::MISCREG_MTRR_PHYS_MASK_END
@ MISCREG_MTRR_PHYS_MASK_END
Definition: misc.hh:182
X86ISA::MISCREG_IDTR_LIMIT
@ MISCREG_IDTR_LIMIT
Definition: misc.hh:358
X86ISA::mcip
Bitfield< 2 > mcip
Definition: misc.hh:710
X86ISA::UEBit
@ UEBit
Definition: misc.hh:87
X86ISA::CC3Bit
@ CC3Bit
Definition: misc.hh:96
X86ISA::ZFBit
@ ZFBit
Definition: misc.hh:60
X86ISA::osfxsr
Bitfield< 9 > osfxsr
Definition: misc.hh:629
X86ISA::MISCREG_MXCSR
@ MISCREG_MXCSR
Definition: misc.hh:380
X86ISA::bsp
Bitfield< 8 > bsp
Definition: misc.hh:1052
X86ISA::MISCREG_CR6
@ MISCREG_CR6
Definition: misc.hh:111
X86ISA::ZEBit
@ ZEBit
Definition: misc.hh:85
X86ISA::RFBit
@ RFBit
Definition: misc.hh:73
X86ISA::MISCREG_CR11
@ MISCREG_CR11
Definition: misc.hh:116
X86ISA::disA20M
Bitfield< 2 > disA20M
Definition: misc.hh:837
X86ISA::MISCREG_TSL_BASE
@ MISCREG_TSL_BASE
Definition: misc.hh:319
X86ISA::MISCREG_CR15
@ MISCREG_CR15
Definition: misc.hh:120
X86ISA::MISCREG_PAT
@ MISCREG_PAT
Definition: misc.hh:196
X86ISA::MISCREG_FSW
@ MISCREG_FSW
Definition: misc.hh:382
X86ISA::len1
Bitfield< 23, 22 > len1
Definition: misc.hh:670
X86ISA::MISCREG_MTRR_PHYS_BASE_4
@ MISCREG_MTRR_PHYS_BASE_4
Definition: misc.hh:167
X86ISA::MISCREG_MC1_CTL
@ MISCREG_MC1_CTL
Definition: misc.hh:202
X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:301
X86ISA::g
Bitfield< 8 > g
Definition: pagetable.hh:143
X86ISA::MISCREG_MTRR_PHYS_MASK_1
@ MISCREG_MTRR_PHYS_MASK_1
Definition: misc.hh:175
X86ISA::ecf
Bitfield< 3 > ecf
Definition: misc.hh:549
X86ISA::MISCREG_KERNEL_GS_BASE
@ MISCREG_KERNEL_GS_BASE
Definition: misc.hh:253
X86ISA::MISCREG_MC_STATUS_BASE
@ MISCREG_MC_STATUS_BASE
Definition: misc.hh:211
X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
X86ISA::MISCREG_MTRR_PHYS_MASK_0
@ MISCREG_MTRR_PHYS_MASK_0
Definition: misc.hh:174
X86ISA::MISCREG_CS_BASE
@ MISCREG_CS_BASE
Definition: misc.hh:313
X86ISA::MISCREG_MC6_STATUS
@ MISCREG_MC6_STATUS
Definition: misc.hh:218
X86ISA::usr
Bitfield< 16 > usr
Definition: misc.hh:802
X86ISA::MISCREG_CR8
@ MISCREG_CR8
Definition: misc.hh:113
X86ISA::MISCREG_SEG_BASE_BASE
@ MISCREG_SEG_BASE_BASE
Definition: misc.hh:311
X86ISA::MISCREG_FOOFF
@ MISCREG_FOOFF
Definition: misc.hh:388
X86ISA::unusable
Bitfield< 2 > unusable
Definition: misc.hh:987
X86ISA::MISCREG_TSL_ATTR
@ MISCREG_TSL_ATTR
Definition: misc.hh:369
X86ISA::of
Bitfield< 11 > of
Definition: misc.hh:566
X86ISA::MISCREG_DR
static MiscRegIndex MISCREG_DR(int index)
Definition: misc.hh:418
X86ISA::submode
Bitfield< 3, 1 > submode
Definition: misc.hh:579
X86ISA::MISCREG_PERF_EVT_CTR
static MiscRegIndex MISCREG_PERF_EVT_CTR(int index)
Definition: misc.hh:481
X86ISA::MISCREG_PERF_EVT_CTR_END
@ MISCREG_PERF_EVT_CTR_END
Definition: misc.hh:269
X86ISA::MISCREG_MC_ADDR_BASE
@ MISCREG_MC_ADDR_BASE
Definition: misc.hh:222
X86ISA::cfofMask
const uint32_t cfofMask
Definition: misc.hh:66
X86ISA::MISCREG_TSG
@ MISCREG_TSG
Definition: misc.hh:304
X86ISA::MISCREG_FS_BASE
@ MISCREG_FS_BASE
Definition: misc.hh:316
X86ISA::MISCREG_MTRR_PHYS_BASE_2
@ MISCREG_MTRR_PHYS_BASE_2
Definition: misc.hh:165
X86ISA::otherInfo
Bitfield< 56, 32 > otherInfo
Definition: misc.hh:762
QARMA::b0
Bitfield< 3, 0 > b0
Definition: qarma.hh:63
X86ISA::tpr
tpr
Definition: misc.hh:642
X86ISA::defAddr
Bitfield< 13, 12 > defAddr
Definition: misc.hh:585
X86ISA::MISCREG_LS_EFF_BASE
@ MISCREG_LS_EFF_BASE
Definition: misc.hh:339
X86ISA::tom2
Bitfield< 21 > tom2
Definition: misc.hh:816
X86ISA::MISCREG_TSC
@ MISCREG_TSC
Definition: misc.hh:143
X86ISA::EZFBit
@ EZFBit
Definition: misc.hh:59
X86ISA::ti
Bitfield< 2 > ti
Definition: misc.hh:861
X86ISA::MISCREG_MC2_ADDR
@ MISCREG_MC2_ADDR
Definition: misc.hh:225
X86ISA::en
Bitfield< 60 > en
Definition: misc.hh:766
X86ISA::MISCREG_ES_ATTR
@ MISCREG_ES_ATTR
Definition: misc.hh:362
X86ISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:100
X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:320
ArmISA::id
Bitfield< 33 > id
Definition: miscregs_types.hh:247
X86ISA::l3
Bitfield< 6 > l3
Definition: misc.hh:662
X86ISA::MISCREG_PERF_EVT_CTR_BASE
@ MISCREG_PERF_EVT_CTR_BASE
Definition: misc.hh:264
X86ISA::mfdm
Bitfield< 19 > mfdm
Definition: misc.hh:814
X86ISA::MISCREG_SS_BASE
@ MISCREG_SS_BASE
Definition: misc.hh:314
X86ISA::MISCREG_MC4_CTL
@ MISCREG_MC4_CTL
Definition: misc.hh:205
X86ISA::MISCREG_FCW
@ MISCREG_FCW
Definition: misc.hh:381
X86ISA::uc
Bitfield< 61 > uc
Definition: misc.hh:767
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
X86ISA::MISCREG_MTRR_PHYS_MASK_5
@ MISCREG_MTRR_PHYS_MASK_5
Definition: misc.hh:179
X86ISA::ezf
Bitfield< 5 > ezf
Definition: misc.hh:547
X86ISA::baseLow
Bitfield< 39, 16 > baseLow
Definition: misc.hh:915

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