gem5  v20.1.0.0
DMASequencer.hh
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28 
29 #ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
30 #define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
31 
32 #include <memory>
33 #include <ostream>
34 #include <unordered_map>
35 
38 #include "mem/ruby/protocol/DMASequencerRequestType.hh"
40 #include "params/DMASequencer.hh"
41 
42 struct DMARequest
43 {
44  DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed,
45  int bytes_issued, uint8_t *data, PacketPtr pkt);
46 
47  uint64_t start_paddr;
48  int len;
49  bool write;
52  uint8_t *data;
54 };
55 
56 class DMASequencer : public RubyPort
57 {
58  public:
59  typedef DMASequencerParams Params;
60  DMASequencer(const Params *);
61  void init() override;
62 
63  /* external interface */
64  RequestStatus makeRequest(PacketPtr pkt) override;
65  bool busy() { return m_outstanding_count > 0; }
66  int outstandingCount() const override { return m_outstanding_count; }
67  bool isDeadlockEventScheduled() const override { return false; }
68  void descheduleDeadlockEvent() override {}
69 
70  /* SLICC callback */
71  void dataCallback(const DataBlock &dblk, const Addr &addr);
72  void ackCallback(const Addr &addr);
73 
74  void recordRequestType(DMASequencerRequestType requestType);
75 
76  private:
77  void issueNext(const Addr &addr);
78 
80 
81  typedef std::unordered_map<Addr, DMARequest> RequestTable;
83 
86 };
87 
88 #endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
DMASequencer::isDeadlockEventScheduled
bool isDeadlockEventScheduled() const override
Definition: DMASequencer.hh:67
DMASequencer::descheduleDeadlockEvent
void descheduleDeadlockEvent() override
Definition: DMASequencer.hh:68
DMARequest
Definition: DMASequencer.hh:42
DMASequencer::RequestTable
std::unordered_map< Addr, DMARequest > RequestTable
Definition: DMASequencer.hh:81
DMARequest::bytes_issued
int bytes_issued
Definition: DMASequencer.hh:51
DMASequencer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: DMASequencer.hh:85
DMARequest::data
uint8_t * data
Definition: DMASequencer.hh:52
DMASequencer
Definition: DMASequencer.hh:56
DMARequest::bytes_completed
int bytes_completed
Definition: DMASequencer.hh:50
DMASequencer::m_RequestTable
RequestTable m_RequestTable
Definition: DMASequencer.hh:82
DMASequencer::m_outstanding_count
int m_outstanding_count
Definition: DMASequencer.hh:84
DMASequencer::outstandingCount
int outstandingCount() const override
Definition: DMASequencer.hh:66
DMASequencer::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: DMASequencer.cc:55
DataBlock
Definition: DataBlock.hh:40
DMARequest::pkt
PacketPtr pkt
Definition: DMASequencer.hh:53
DMASequencer::dataCallback
void dataCallback(const DataBlock &dblk, const Addr &addr)
Definition: DMASequencer.cc:173
DMASequencer::Params
DMASequencerParams Params
Definition: DMASequencer.hh:59
DMARequest::DMARequest
DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed, int bytes_issued, uint8_t *data, PacketPtr pkt)
Definition: DMASequencer.cc:39
DataBlock.hh
RubyPort
Definition: RubyPort.hh:58
DMASequencer::recordRequestType
void recordRequestType(DMASequencerRequestType requestType)
Definition: DMASequencer.cc:200
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
DMASequencer::DMASequencer
DMASequencer(const Params *)
Definition: DMASequencer.cc:48
DMARequest::len
int len
Definition: DMASequencer.hh:48
DMASequencer::issueNext
void issueNext(const Addr &addr)
Definition: DMASequencer.cc:121
DMASequencer::makeRequest
RequestStatus makeRequest(PacketPtr pkt) override
Definition: DMASequencer.cc:65
Address.hh
DMASequencer::m_data_block_mask
uint64_t m_data_block_mask
Definition: DMASequencer.hh:79
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
addr
ip6_addr_t addr
Definition: inet.hh:423
DMARequest::start_paddr
uint64_t start_paddr
Definition: DMASequencer.hh:47
DMASequencer::ackCallback
void ackCallback(const Addr &addr)
Definition: DMASequencer.cc:193
RubyPort.hh
DMARequest::write
bool write
Definition: DMASequencer.hh:49
DMASequencer::busy
bool busy()
Definition: DMASequencer.hh:65

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