gem5  v20.1.0.0
DMASequencer.cc
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1 /*
2  * Copyright (c) 2008 Mark D. Hill and David A. Wood
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28 
30 
31 #include <memory>
32 
33 #include "debug/RubyDma.hh"
34 #include "debug/RubyStats.hh"
35 #include "mem/ruby/protocol/SequencerMsg.hh"
36 #include "mem/ruby/protocol/SequencerRequestType.hh"
38 
39 DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,
40  int bytes_completed, int bytes_issued, uint8_t *data,
41  PacketPtr pkt)
42  : start_paddr(start_paddr), len(len), write(write),
43  bytes_completed(bytes_completed), bytes_issued(bytes_issued), data(data),
44  pkt(pkt)
45 {
46 }
47 
49  : RubyPort(p), m_outstanding_count(0),
50  m_max_outstanding_requests(p->max_outstanding_requests)
51 {
52 }
53 
54 void
56 {
59 
60  for (const auto &response_port : response_ports)
61  response_port->sendRangeChange();
62 }
63 
64 RequestStatus
66 {
68  return RequestStatus_BufferFull;
69  }
70 
71  Addr paddr = pkt->getAddr();
72  uint8_t* data = pkt->getPtr<uint8_t>();
73  int len = pkt->getSize();
74  bool write = pkt->isWrite();
75 
77  Addr line_addr = makeLineAddress(paddr);
78  auto emplace_pair =
79  m_RequestTable.emplace(std::piecewise_construct,
80  std::forward_as_tuple(line_addr),
81  std::forward_as_tuple(paddr, len, write, 0,
82  0, data, pkt));
83  DMARequest& active_request = emplace_pair.first->second;
84 
85  // This is pretty conservative. A regular Sequencer with a more beefy
86  // request table that can track multiple requests for a cache line should
87  // be used if a more aggressive policy is needed.
88  if (!emplace_pair.second) {
89  DPRINTF(RubyDma, "DMA aliased: addr %p, len %d\n", line_addr, len);
90  return RequestStatus_Aliased;
91  }
92 
93  DPRINTF(RubyDma, "DMA req created: addr %p, len %d\n", line_addr, len);
94 
95  std::shared_ptr<SequencerMsg> msg =
96  std::make_shared<SequencerMsg>(clockEdge());
97  msg->getPhysicalAddress() = paddr;
98  msg->getLineAddress() = line_addr;
99  msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
100  int offset = paddr & m_data_block_mask;
101 
102  msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
104 
105  if (write && (data != NULL)) {
106  if (active_request.data != NULL) {
107  msg->getDataBlk().setData(data, offset, msg->getLen());
108  }
109  }
110 
112 
113  assert(m_mandatory_q_ptr != NULL);
115  active_request.bytes_issued += msg->getLen();
116 
117  return RequestStatus_Issued;
118 }
119 
120 void
122 {
123  RequestTable::iterator i = m_RequestTable.find(address);
124  assert(i != m_RequestTable.end());
125 
126  DMARequest &active_request = i->second;
127 
129  active_request.bytes_completed = active_request.bytes_issued;
130  if (active_request.len == active_request.bytes_completed) {
131  DPRINTF(RubyDma, "DMA request completed: addr %p, size %d\n",
132  address, active_request.len);
134  PacketPtr pkt = active_request.pkt;
135  m_RequestTable.erase(i);
136  ruby_hit_callback(pkt);
137  return;
138  }
139 
140  std::shared_ptr<SequencerMsg> msg =
141  std::make_shared<SequencerMsg>(clockEdge());
142  msg->getPhysicalAddress() = active_request.start_paddr +
143  active_request.bytes_completed;
144 
145  assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
146  msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
147 
148  msg->getType() = (active_request.write ? SequencerRequestType_ST :
149  SequencerRequestType_LD);
150 
151  msg->getLen() =
152  (active_request.len -
154  active_request.len - active_request.bytes_completed :
156 
157  if (active_request.write) {
158  msg->getDataBlk().
159  setData(&active_request.data[active_request.bytes_completed],
160  0, msg->getLen());
161  }
162 
163  assert(m_mandatory_q_ptr != NULL);
165  active_request.bytes_issued += msg->getLen();
166  DPRINTF(RubyDma,
167  "DMA request bytes issued %d, bytes completed %d, total len %d\n",
168  active_request.bytes_issued, active_request.bytes_completed,
169  active_request.len);
170 }
171 
172 void
173 DMASequencer::dataCallback(const DataBlock & dblk, const Addr& address)
174 {
175 
176  RequestTable::iterator i = m_RequestTable.find(address);
177  assert(i != m_RequestTable.end());
178 
179  DMARequest &active_request = i->second;
180  int len = active_request.bytes_issued - active_request.bytes_completed;
181  int offset = 0;
182  if (active_request.bytes_completed == 0)
183  offset = active_request.start_paddr & m_data_block_mask;
184  assert(!active_request.write);
185  if (active_request.data != NULL) {
186  memcpy(&active_request.data[active_request.bytes_completed],
187  dblk.getData(offset, len), len);
188  }
189  issueNext(address);
190 }
191 
192 void
194 {
195  assert(m_RequestTable.find(address) != m_RequestTable.end());
196  issueNext(address);
197 }
198 
199 void
200 DMASequencer::recordRequestType(DMASequencerRequestType requestType)
201 {
202  DPRINTF(RubyStats, "Recorded statistic: %s\n",
203  DMASequencerRequestType_to_string(requestType));
204 }
205 
206 DMASequencer *
207 DMASequencerParams::create()
208 {
209  return new DMASequencer(this);
210 }
DMARequest
Definition: DMASequencer.hh:42
RubyPort::ruby_hit_callback
void ruby_hit_callback(PacketPtr pkt)
Definition: RubyPort.cc:432
RubyPort::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: RubyPort.cc:85
RubySystem::getBlockSizeBytes
static uint32_t getBlockSizeBytes()
Definition: RubySystem.hh:62
data
const char data[]
Definition: circlebuf.test.cc:42
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:54
DMARequest::bytes_issued
int bytes_issued
Definition: DMASequencer.hh:51
DMASequencer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: DMASequencer.hh:85
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
DMASequencer.hh
DMARequest::data
uint8_t * data
Definition: DMASequencer.hh:52
DMASequencer
Definition: DMASequencer.hh:56
DMARequest::bytes_completed
int bytes_completed
Definition: DMASequencer.hh:50
DMASequencer::m_RequestTable
RequestTable m_RequestTable
Definition: DMASequencer.hh:82
Packet::getSize
unsigned getSize() const
Definition: packet.hh:764
DMASequencer::m_outstanding_count
int m_outstanding_count
Definition: DMASequencer.hh:84
MessageBuffer::enqueue
void enqueue(MsgPtr message, Tick curTime, Tick delta)
Definition: MessageBuffer.cc:162
DMASequencer::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: DMASequencer.cc:55
DataBlock
Definition: DataBlock.hh:40
RubyPort::m_mandatory_q_ptr
MessageBuffer * m_mandatory_q_ptr
Definition: RubyPort.hh:191
DMARequest::pkt
PacketPtr pkt
Definition: DMASequencer.hh:53
RubyPort::response_ports
std::vector< MemResponsePort * > response_ports
Definition: RubyPort.hh:195
DMASequencer::dataCallback
void dataCallback(const DataBlock &dblk, const Addr &addr)
Definition: DMASequencer.cc:173
DMASequencer::Params
DMASequencerParams Params
Definition: DMASequencer.hh:59
Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:224
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
DataBlock::getData
const uint8_t * getData(int offset, int len) const
Definition: DataBlock.cc:95
DMARequest::DMARequest
DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed, int bytes_issued, uint8_t *data, PacketPtr pkt)
Definition: DMASequencer.cc:39
RubyPort
Definition: RubyPort.hh:58
Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:174
RubySystem.hh
DMASequencer::recordRequestType
void recordRequestType(DMASequencerRequestType requestType)
Definition: DMASequencer.cc:200
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
DMASequencer::DMASequencer
DMASequencer(const Params *)
Definition: DMASequencer.cc:48
DMARequest::len
int len
Definition: DMASequencer.hh:48
DMASequencer::issueNext
void issueNext(const Addr &addr)
Definition: DMASequencer.cc:121
DMASequencer::makeRequest
RequestStatus makeRequest(PacketPtr pkt) override
Definition: DMASequencer.cc:65
DMASequencer::m_data_block_mask
uint64_t m_data_block_mask
Definition: DMASequencer.hh:79
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Packet::isWrite
bool isWrite() const
Definition: packet.hh:557
Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1157
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
DMARequest::start_paddr
uint64_t start_paddr
Definition: DMASequencer.hh:47
DMASequencer::ackCallback
void ackCallback(const Addr &addr)
Definition: DMASequencer.cc:193
DMARequest::write
bool write
Definition: DMASequencer.hh:49
RubySystem::getBlockSizeBits
static uint32_t getBlockSizeBits()
Definition: RubySystem.hh:63
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:153

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