A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache). More...

#include <packet.hh>

Inheritance diagram for Packet:

Classes
class	PrintReqState
	Object used to maintain state of a PrintReq. More...

struct	SenderState
	A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet. More...

Public Types
typedef uint32_t	FlagsType

typedef ::Flags< FlagsType >	Flags

typedef MemCmd::Command	Command

Public Member Functions
void	pushSenderState (SenderState *sender_state)
	Push a new sender state to the packet and make the current sender state the predecessor of the new one. More...

SenderState *	popSenderState ()
	Pop the top of the state stack and return a pointer to it. More...

template<typename T >
T *	findNextSenderState () const
	Go through the sender state stack and return the first instance that is of type T (as determined by a dynamic_cast). More...

const std::string &	cmdString () const
	Return the string name of the cmd field (for debugging and tracing). More...

int	cmdToIndex () const
	Return the index of this command. More...

bool	isRead () const

bool	isWrite () const

bool	isUpgrade () const

bool	isRequest () const

bool	isResponse () const

bool	needsWritable () const

bool	needsResponse () const

bool	isInvalidate () const

bool	isEviction () const

bool	isClean () const

bool	fromCache () const

bool	isWriteback () const

bool	hasData () const

bool	hasRespData () const

bool	isLLSC () const

bool	isError () const

bool	isPrint () const

bool	isFlush () const

bool	isWholeLineWrite (unsigned blk_size)

void	setCacheResponding ()
	Snoop flags. More...

bool	cacheResponding () const

void	setHasSharers ()
	On fills, the hasSharers flag is used by the caches in combination with the cacheResponding flag, as clarified above. More...

bool	hasSharers () const

void	setExpressSnoop ()
	The express snoop flag is used for two purposes. More...

bool	isExpressSnoop () const

void	setResponderHadWritable ()
	On responding to a snoop request (which only happens for Modified or Owned lines), make sure that we can transform an Owned response to a Modified one. More...

bool	responderHadWritable () const

void	copyResponderFlags (const PacketPtr pkt)
	Copy the reponse flags from an input packet to this packet. More...

void	setWriteThrough ()
	A writeback/writeclean cmd gets propagated further downstream by the receiver when the flag is set. More...

void	clearWriteThrough ()

bool	writeThrough () const

void	setSatisfied ()
	Set when a request hits in a cache and the cache is not going to respond. More...

bool	satisfied () const

void	setSuppressFuncError ()

bool	suppressFuncError () const

void	setBlockCached ()

bool	isBlockCached () const

void	clearBlockCached ()

uint8_t	qosValue () const
	QoS Value getter Returns 0 if QoS value was never set (constructor default). More...

void	qosValue (const uint8_t qos_value)
	QoS Value setter Interface for setting QoS priority value of the packet. More...

RequestorID	requestorId () const

void	setBadAddress ()

void	copyError (Packet *pkt)

Addr	getAddr () const

void	setAddr (Addr _addr)
	Update the address of this packet mid-transaction. More...

unsigned	getSize () const

AddrRange	getAddrRange () const
	Get address range to which this packet belongs. More...

Addr	getOffset (unsigned int blk_size) const

Addr	getBlockAddr (unsigned int blk_size) const

bool	isSecure () const

AtomicOpFunctor *	getAtomicOp () const
	Accessor function to atomic op. More...

bool	isAtomicOp () const

void	convertScToWrite ()
	It has been determined that the SC packet should successfully update memory. More...

void	convertLlToRead ()
	When ruby is in use, Ruby will monitor the cache line and the phys memory should treat LL ops as normal reads. More...

	Packet (const RequestPtr &_req, MemCmd _cmd)
	Constructor. More...

	Packet (const RequestPtr &_req, MemCmd _cmd, int _blkSize, PacketId _id=0)
	Alternate constructor if you are trying to create a packet with a request that is for a whole block, not the address from the req. More...

	Packet (const PacketPtr pkt, bool clear_flags, bool alloc_data)
	Alternate constructor for copying a packet. More...

	~Packet ()
	clean up packet variables More...

void	makeResponse ()
	Take a request packet and modify it in place to be suitable for returning as a response to that request. More...

void	makeAtomicResponse ()

void	makeTimingResponse ()

void	setFunctionalResponseStatus (bool success)

void	setSize (unsigned size)

bool	matchBlockAddr (const Addr addr, const bool is_secure, const int blk_size) const
	Check if packet corresponds to a given block-aligned address and address space. More...

bool	matchBlockAddr (const PacketPtr pkt, const int blk_size) const
	Check if this packet refers to the same block-aligned address and address space as another packet. More...

bool	matchAddr (const Addr addr, const bool is_secure) const
	Check if packet corresponds to a given address and address space. More...

bool	matchAddr (const PacketPtr pkt) const
	Check if this packet refers to the same address and address space as another packet. More...

template<typename T >
T	getRaw () const
	Get the data in the packet without byte swapping. More...

template<typename T >
void	setRaw (T v)
	Set the value in the data pointer to v without byte swapping. More...

bool	trySatisfyFunctional (PacketPtr other)
	Check a functional request against a memory value stored in another packet (i.e. More...

bool	mustCheckAbove () const
	Does the request need to check for cached copies of the same block in the memory hierarchy above. More...

bool	isCleanEviction () const
	Is this packet a clean eviction, including both actual clean evict packets, but also clean writebacks. More...

bool	isMaskedWrite () const

bool	trySatisfyFunctional (Printable obj, Addr base, bool is_secure, int size, uint8_t _data)
	Check a functional request against a memory value represented by a base/size pair and an associated data array. More...

void	pushLabel (const std::string &lbl)
	Push label for PrintReq (safe to call unconditionally). More...

void	popLabel ()
	Pop label for PrintReq (safe to call unconditionally). More...

void	print (std::ostream &o, int verbosity=0, const std::string &prefix="") const

std::string	print () const
	A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overheads in fast mode. More...

void	makeHtmTransactionalReqResponse (const HtmCacheFailure ret_code)
	Communicates to the core that a packet was processed by the memory subsystem while running in transactional mode. More...

void	setHtmTransactional (uint64_t val)
	Stipulates that this packet/request originates in the CPU executing in transactional mode, i.e. More...

bool	isHtmTransactional () const
	Returns whether or not this packet/request originates in the CPU executing in transactional mode, i.e. More...

uint64_t	getHtmTransactionUid () const
	If a packet/request originates in a CPU executing in transactional mode, i.e. More...

void	setHtmTransactionFailedInCache (const HtmCacheFailure ret_code)
	Stipulates that this packet/request has returned from the cache hierarchy in a failed transaction. More...

bool	htmTransactionFailedInCache () const
	Returns whether or not this packet/request has returned from the cache hierarchy in a failed transaction. More...

HtmCacheFailure	getHtmTransactionFailedInCacheRC () const
	If a packet/request has returned from the cache hierarchy in a failed transaction, this function returns the failure reason. More...

Data accessor mehtods
template<typename T >
void	dataStatic (T *p)
	Set the data pointer to the following value that should not be freed. More...

template<typename T >
void	dataStaticConst (const T *p)
	Set the data pointer to the following value that should not be freed. More...

template<typename T >
void	dataDynamic (T *p)
	Set the data pointer to a value that should have delete [] called on it. More...

template<typename T >
T *	getPtr ()
	get a pointer to the data ptr. More...

template<typename T >
const T *	getConstPtr () const

template<typename T >
T	getBE () const
	Get the data in the packet byte swapped from big endian to host endian. More...

template<typename T >
T	getLE () const
	Get the data in the packet byte swapped from little endian to host endian. More...

template<typename T >
T	get (ByteOrder endian) const
	Get the data in the packet byte swapped from the specified endianness. More...

template<typename T >
void	setBE (T v)
	Set the value in the data pointer to v as big endian. More...

template<typename T >
void	setLE (T v)
	Set the value in the data pointer to v as little endian. More...

template<typename T >
void	set (T v, ByteOrder endian)
	Set the value in the data pointer to v using the specified endianness. More...

uint64_t	getUintX (ByteOrder endian) const
	Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits. More...

void	setUintX (uint64_t w, ByteOrder endian)
	Set the value in the word w after truncating it to the length of the packet and then byteswapping it to the desired endianness. More...

void	setData (const uint8_t *p)
	Copy data into the packet from the provided pointer. More...

void	setDataFromBlock (const uint8_t *blk_data, int blkSize)
	Copy data into the packet from the provided block pointer, which is aligned to the given block size. More...

void	writeData (uint8_t *p) const
	Copy data from the packet to the memory at the provided pointer. More...

void	writeDataToBlock (uint8_t *blk_data, int blkSize) const
	Copy data from the packet to the provided block pointer, which is aligned to the given block size. More...

void	deleteData ()
	delete the data pointed to in the data pointer. More...

void	allocate ()
	Allocate memory for the packet. More...

Public Member Functions inherited from Printable
	Printable ()

virtual	~Printable ()

Static Public Member Functions
static MemCmd	makeReadCmd (const RequestPtr &req)
	Generate the appropriate read MemCmd based on the Request flags. More...

static MemCmd	makeWriteCmd (const RequestPtr &req)
	Generate the appropriate write MemCmd based on the Request flags. More...

static PacketPtr	createRead (const RequestPtr &req)
	Constructor-like methods that return Packets based on Request objects. More...

static PacketPtr	createWrite (const RequestPtr &req)

Public Attributes
MemCmd	cmd
	The command field of the packet. More...

const PacketId	id

RequestPtr	req
	A pointer to the original request. More...

uint32_t	headerDelay
	The extra delay from seeing the packet until the header is transmitted. More...

uint32_t	snoopDelay
	Keep track of the extra delay incurred by snooping upwards before sending a request down the memory system. More...

uint32_t	payloadDelay
	The extra pipelining delay from seeing the packet until the end of payload is transmitted by the component that provided it (if any). More...

SenderState *	senderState
	This packet's sender state. More...

Private Types
enum	: FlagsType { COPY_FLAGS = 0x000000FF, RESPONDER_FLAGS = 0x00000009, HAS_SHARERS = 0x00000001, EXPRESS_SNOOP = 0x00000002, RESPONDER_HAD_WRITABLE = 0x00000004, CACHE_RESPONDING = 0x00000008, WRITE_THROUGH = 0x00000010, SATISFIED = 0x00000020, FAILS_TRANSACTION = 0x00000040, FROM_TRANSACTION = 0x00000080, VALID_ADDR = 0x00000100, VALID_SIZE = 0x00000200, STATIC_DATA = 0x00001000, DYNAMIC_DATA = 0x00002000, SUPPRESS_FUNC_ERROR = 0x00008000, BLOCK_CACHED = 0x00010000 }

Private Attributes
Flags	flags

PacketDataPtr	data
	A pointer to the data being transferred. More...

Addr	addr
	The address of the request. More...

bool	_isSecure
	True if the request targets the secure memory space. More...

unsigned	size
	The size of the request or transfer. More...

std::vector< bool >	bytesValid
	Track the bytes found that satisfy a functional read. More...

uint8_t	_qosValue

HtmCacheFailure	htmReturnReason
	Holds the return status of the transaction. More...

uint64_t	htmTransactionUid
	A global unique identifier of the transaction. More...

Detailed Description

A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache).

(In contrast, a single Request travels all the way from the requestor to the ultimate destination and back, possibly being conveyed by several different Packets along the way.)

Definition at line 257 of file packet.hh.

Member Typedef Documentation

◆ Command

typedef MemCmd::Command Packet::Command

Definition at line 332 of file packet.hh.

◆ Flags

typedef ::Flags<FlagsType> Packet::Flags

Definition at line 261 of file packet.hh.

◆ FlagsType

typedef uint32_t Packet::FlagsType

Definition at line 260 of file packet.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum : FlagsType

private

Enumerator
COPY_FLAGS
RESPONDER_FLAGS
HAS_SHARERS
EXPRESS_SNOOP	Special timing-mode atomic snoop for multi-level coherence.
RESPONDER_HAD_WRITABLE	Allow a responding cache to inform the cache hierarchy that it had a writable copy before responding. See setResponderHadWritable below.
CACHE_RESPONDING
WRITE_THROUGH
SATISFIED
FAILS_TRANSACTION
FROM_TRANSACTION
VALID_ADDR	Are the 'addr' and 'size' fields valid?
VALID_SIZE
STATIC_DATA	Is the data pointer set to a value that shouldn't be freed when the packet is destroyed?
DYNAMIC_DATA	The data pointer points to a value that should be freed when the packet is destroyed. The pointer is assumed to be pointing to an array, and delete [] is consequently called
SUPPRESS_FUNC_ERROR	suppress the error if this packet encounters a functional access failure.
BLOCK_CACHED

Definition at line 265 of file packet.hh.

Constructor & Destructor Documentation

◆ Packet() [1/3]

Packet::Packet	(	const RequestPtr &	_req,
		MemCmd	_cmd
	)

inline

Constructor.

Note that a Request object must be constructed first, but the Requests's physical address and size fields need not be valid. The command must be supplied.

hardware transactional memory

This is a bit of a hack! Technically the address of a HTM command is set to zero but is not valid. The reason that we pretend it's valid is to void the getAddr() function from failing. It would be cumbersome to add control flow in many places to check if the packet represents a HTM command before calling getAddr().

Definition at line 824 of file packet.hh.

References _isSecure, addr, Flags< T >::clear(), flags, req, Flags< T >::set(), size, VALID_ADDR, and VALID_SIZE.

Referenced by createRead(), and createWrite().

◆ Packet() [2/3]

Packet::Packet	(	const RequestPtr &	_req,
		MemCmd	_cmd,
		int	_blkSize,
		PacketId	_id = `0`
	)

inline

Alternate constructor if you are trying to create a packet with a request that is for a whole block, not the address from the req.

this allows for overriding the size/addr of the req.

Definition at line 865 of file packet.hh.

References _isSecure, addr, Flags< T >::clear(), flags, req, Flags< T >::set(), size, VALID_ADDR, and VALID_SIZE.

◆ Packet() [3/3]

Packet::Packet	(	const PacketPtr	pkt,
		bool	clear_flags,
		bool	alloc_data
	)

inline

Alternate constructor for copying a packet.

Copy all fields except if the original packet's data was dynamic, don't copy that, as we can't guarantee that the new packet's lifetime is less than that of the original packet. In this case the new packet should allocate its own data.

Definition at line 891 of file packet.hh.

References allocate(), COPY_FLAGS, data, flags, getHtmTransactionFailedInCacheRC(), getHtmTransactionUid(), htmTransactionFailedInCache(), isHtmTransactional(), Flags< T >::isSet(), Flags< T >::set(), setHtmTransactional(), setHtmTransactionFailedInCache(), STATIC_DATA, VALID_ADDR, and VALID_SIZE.

◆ ~Packet()

Packet::~Packet ( )

inline

clean up packet variables

Definition at line 994 of file packet.hh.

References deleteData().

Member Function Documentation

◆ allocate()

void Packet::allocate ( )

inline

Allocate memory for the packet.

Definition at line 1299 of file packet.hh.

References data, DYNAMIC_DATA, flags, getSize(), hasData(), hasRespData(), Flags< T >::noneSet(), Flags< T >::set(), and STATIC_DATA.

Referenced by SimpleCache::accessTiming(), X86ISA::buildIntPacket(), Cache::cleanEvictBlk(), NoncoherentCache::createMissPacket(), Cache::createMissPacket(), Prefetcher::Queued::DeferredPacket::createPkt(), InvalidateGenerator::initiate(), SeriesRequestGenerator::initiate(), Minor::Fetch1::FetchRequest::makePacket(), Minor::makePacketForRequest(), Packet(), replaceUpgrade(), AbstractController::serviceMemoryQueue(), BaseCache::writebackBlk(), and BaseCache::writecleanBlk().

◆ cacheResponding()

bool Packet::cacheResponding ( ) const

inline

Definition at line 619 of file packet.hh.

References CACHE_RESPONDING, flags, and Flags< T >::isSet().

Referenced by AbstractMemory::access(), copyResponderFlags(), CoherentXBar::forwardAtomic(), BaseCache::handleFill(), Cache::handleSnoop(), Cache::isCachedAbove(), SnoopFilter::lookupRequest(), NoncoherentCache::recvAtomic(), Cache::recvAtomic(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomic(), SimpleMemory::recvAtomic(), DRAMSim2::recvAtomic(), Bridge::BridgeResponsePort::recvAtomic(), DRAMsim3::recvAtomic(), QoS::MemSinkCtrl::recvAtomic(), CommMonitor::recvAtomic(), MemCtrl::recvAtomic(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomicBackdoor(), NoncoherentCache::recvTimingReq(), SimpleTimingPort::recvTimingReq(), HMCController::recvTimingReq(), RubyPort::MemResponsePort::recvTimingReq(), Cache::recvTimingReq(), NoncoherentXBar::recvTimingReq(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), Bridge::BridgeResponsePort::recvTimingReq(), DRAMSim2::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), DRAMsim3::recvTimingReq(), AddrMapper::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CommMonitor::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCtrl::recvTimingReq(), DefaultFetch< Impl >::IcachePort::recvTimingResp(), DmaPort::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), Cache::sendMSHRQueuePacket(), BaseCache::sendMSHRQueuePacket(), setResponderHadWritable(), CoherentXBar::sinkPacket(), SnoopFilter::updateSnoopForward(), and SnoopFilter::updateSnoopResponse().

◆ clearBlockCached()

void Packet::clearBlockCached ( )

inline

Definition at line 721 of file packet.hh.

References BLOCK_CACHED, Flags< T >::clear(), and flags.

Referenced by BaseCache::access().

◆ clearWriteThrough()

void Packet::clearWriteThrough ( )

inline

Definition at line 701 of file packet.hh.

References Flags< T >::clear(), flags, and WRITE_THROUGH.

Referenced by CoherentXBar::recvAtomicBackdoor(), and CoherentXBar::recvTimingReq().

◆ cmdString()

const std::string& Packet::cmdString ( ) const

inline

Return the string name of the cmd field (for debugging and tracing).

Definition at line 551 of file packet.hh.

References cmd, and MemCmd::toString().

Referenced by AbstractMemory::functionalAccess(), DmaPort::handleResp(), Sequencer::hitCallback(), print(), MemCtrl::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), RubyPort::MemResponsePort::recvFunctional(), NoncoherentXBar::recvFunctional(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), HMCController::recvTimingReq(), RubyPort::MemResponsePort::recvTimingReq(), NoncoherentXBar::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), Bridge::BridgeResponsePort::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), MemCtrl::recvTimingReq(), NoncoherentXBar::recvTimingResp(), SerialLink::SerialLinkRequestPort::recvTimingResp(), Bridge::BridgeRequestPort::recvTimingResp(), LSQ< Impl >::recvTimingSnoopReq(), RubyPort::ruby_hit_callback(), PacketQueue::schedSendTiming(), AtomicSimpleCPU::threadSnoop(), trySatisfyFunctional(), DmaPort::trySendTimingReq(), and BaseTrafficGen::update().

◆ cmdToIndex()

int Packet::cmdToIndex ( ) const

inline

Return the index of this command.

Definition at line 554 of file packet.hh.

References cmd, and MemCmd::toInt().

Referenced by NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), HMCController::recvTimingReq(), NoncoherentXBar::recvTimingReq(), CoherentXBar::recvTimingReq(), NoncoherentXBar::recvTimingResp(), CoherentXBar::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), and CoherentXBar::recvTimingSnoopResp().

◆ convertLlToRead()

void Packet::convertLlToRead ( )

inline

When ruby is in use, Ruby will monitor the cache line and the phys memory should treat LL ops as normal reads.

Definition at line 812 of file packet.hh.

References cmd, isLLSC(), isRead(), and MemCmd::ReadReq.

Referenced by RubyPort::MemResponsePort::hitCallback().

◆ convertScToWrite()

void Packet::convertScToWrite ( )

inline

It has been determined that the SC packet should successfully update memory.

Therefore, convert this SC packet to a normal write.

Definition at line 800 of file packet.hh.

References cmd, isLLSC(), isWrite(), and MemCmd::WriteReq.

Referenced by RubyPort::MemResponsePort::hitCallback().

◆ copyError()

void Packet::copyError ( Packet * pkt )

inline

Definition at line 752 of file packet.hh.

References cmd, and isError().

Referenced by NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), NoncoherentCache::serviceMSHRTargets(), and Cache::serviceMSHRTargets().

◆ copyResponderFlags()

void Packet::copyResponderFlags ( const PacketPtr pkt )

Copy the reponse flags from an input packet to this packet.

The reponse flags determine whether a responder has been found and the state at which the block will be at the destination.

@pkt The packet that we will copy flags from

Definition at line 322 of file packet.cc.

References cacheResponding(), flags, isRequest(), RESPONDER_FLAGS, and Flags< T >::set().

Referenced by Cache::handleSnoop(), and Cache::serviceMSHRTargets().

◆ createRead()

static PacketPtr Packet::createRead ( const RequestPtr & req )

inlinestatic

Constructor-like methods that return Packets based on Request objects.

Fine-tune the MemCmd type if it's not a vanilla read or write.

Definition at line 980 of file packet.hh.

References makeReadCmd(), Packet(), and req.

Referenced by TimingSimpleCPU::buildPacket(), LSQ< Impl >::SingleDataRequest::buildPackets(), LSQ< Impl >::SplitDataRequest::buildPackets(), TraceCPU::ElasticDataGen::executeMemReq(), FullO3CPU< O3CPUImpl >::htmSendAbortSignal(), Minor::makePacketForRequest(), CheckerCPU::readMem(), LSQ< Impl >::SplitDataRequest::recvTimingResp(), and AbstractController::serviceMemoryQueue().

◆ createWrite()

static PacketPtr Packet::createWrite ( const RequestPtr & req )

inlinestatic

Definition at line 986 of file packet.hh.

References makeWriteCmd(), Packet(), and req.

Referenced by TimingSimpleCPU::buildPacket(), LSQ< Impl >::SingleDataRequest::buildPackets(), LSQ< Impl >::SplitDataRequest::buildPackets(), TraceCPU::ElasticDataGen::executeMemReq(), Minor::makePacketForRequest(), LSQ< Impl >::SplitDataRequest::recvTimingResp(), and AbstractController::serviceMemoryQueue().

◆ dataDynamic()

template<typename T >

void Packet::dataDynamic ( T * p )

inline

Set the data pointer to a value that should have delete [] called on it.

Dynamic data is local to this packet, and as the packet travels from source to destination, forwarded packets will allocate their own data. When a packet reaches the final destination it will populate the dynamic data of that specific packet, and on the way back towards the source, memcpy will be invoked in every step where a new packet was created e.g. in the caches. Ultimately when the response reaches the source a final memcpy is needed to extract the data from the packet before it is deallocated.

Definition at line 1145 of file packet.hh.

References data, DYNAMIC_DATA, flags, Flags< T >::noneSet(), MipsISA::p, Flags< T >::set(), and STATIC_DATA.

Referenced by LSQ< Impl >::SplitDataRequest::buildPackets(), TimingSimpleCPU::buildSplitPacket(), TraceCPU::ElasticDataGen::executeMemReq(), DefaultFetch< Impl >::finishTranslation(), GarnetSyntheticTraffic::generatePkt(), BaseGen::getPacket(), Check::initiateAction(), Check::initiateCheck(), Check::initiatePrefetch(), SimpleCache::insert(), Minor::makePacketForRequest(), TraceCPU::FixedRetryGen::send(), TimingSimpleCPU::sendData(), AbstractController::serviceMemoryQueue(), and MemTest::tick().

◆ dataStatic()

template<typename T >

void Packet::dataStatic ( T * p )

inline

Set the data pointer to the following value that should not be freed.

Static data allows us to do a single memcpy even if multiple packets are required to get from source to destination and back. In essence the pointer is set calling dataStatic on the original packet, and whenever this packet is copied and forwarded the same pointer is passed on. When a packet eventually reaches the destination holding the data, it is copied once into the location originally set. On the way back to the source, no copies are necessary.

Definition at line 1107 of file packet.hh.

References data, DYNAMIC_DATA, flags, Flags< T >::noneSet(), MipsISA::p, Flags< T >::set(), and STATIC_DATA.

Referenced by AtomicSimpleCPU::amoMem(), LSQ< Impl >::SplitDataRequest::buildPackets(), TimingSimpleCPU::buildSplitPacket(), DmaPort::dmaAction(), Shader::doFunctionalAccess(), BaseKvmCPU::doMMIOAccess(), CacheRecorder::enqueueNextFetchRequest(), FetchUnit::fetch(), ArmISA::TableWalker::fetchDescriptor(), X86KvmCPU::handleKvmExitIO(), LSQ< Impl >::SplitDataRequest::handleLocalAccess(), FullO3CPU< O3CPUImpl >::htmSendAbortSignal(), initMemReqHelper(), initMemReqScalarHelper(), LSQUnit< Impl >::read(), PortProxy::readBlobPhys(), ArmISA::Stage2MMU::readDataUntimed(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), ComputeUnit::DTLBPort::recvTimingResp(), LSQ< Impl >::SplitDataRequest::recvTimingResp(), ComputeUnit::ScalarDTLBPort::recvTimingResp(), TimingSimpleCPU::sendFetch(), ComputeUnit::sendRequest(), AtomicSimpleCPU::tick(), Checker< O3CPUImpl >::verify(), LSQUnit< Impl >::writebackStores(), BaseCache::writebackVisitor(), and AtomicSimpleCPU::writeMem().

◆ dataStaticConst()

template<typename T >

void Packet::dataStaticConst ( const T * p )

inline

Set the data pointer to the following value that should not be freed.

This version of the function allows the pointer passed to us to be const. To avoid issues down the line we cast the constness away, the alternative would be to keep both a const and non-const data pointer and cleverly choose between them. Note that this is only allowed for static data.

Definition at line 1124 of file packet.hh.

References data, DYNAMIC_DATA, flags, Flags< T >::noneSet(), MipsISA::p, Flags< T >::set(), and STATIC_DATA.

Referenced by PortProxy::writeBlobPhys().

◆ deleteData()

void Packet::deleteData ( )

inline

delete the data pointed to in the data pointer.

Ok to call to matter how data was allocted.

Definition at line 1288 of file packet.hh.

References Flags< T >::clear(), data, DYNAMIC_DATA, flags, Flags< T >::isSet(), and STATIC_DATA.

Referenced by ~Packet().

◆ findNextSenderState()

template<typename T >

T* Packet::findNextSenderState ( ) const

inline

Go through the sender state stack and return the first instance that is of type T (as determined by a dynamic_cast).

If there is no sender state of type T, NULL is returned.

Returns: The topmost state of type T

Definition at line 538 of file packet.hh.

References Packet::SenderState::predecessor, senderState, and ArmISA::t.

Referenced by MSHR::TargetList::add(), Sequencer::hitCallback(), and Minor::LSQ::tryToSend().

◆ fromCache()

bool Packet::fromCache ( ) const

inline

Definition at line 574 of file packet.hh.

References cmd, and MemCmd::fromCache().

Referenced by AbstractMemory::access(), BaseCache::access(), Cache::handleAtomicReqMiss(), SnoopFilter::lookupRequest(), Cache::satisfyRequest(), and MSHR::TargetList::updateFlags().

◆ get()

template<typename T >

T Packet::get ( ByteOrder endian ) const

inline

Get the data in the packet byte swapped from the specified endianness.

Definition at line 82 of file packet_access.hh.

References panic.

Referenced by getMem().

◆ getAddr()

Addr Packet::getAddr ( ) const

inline

Definition at line 754 of file packet.hh.

References addr, flags, Flags< T >::isSet(), and VALID_ADDR.

Referenced by Cache::access(), AbstractMemory::access(), BaseCache::access(), DRAMSim2::accessAndRespond(), DRAMsim3::accessAndRespond(), MemCtrl::accessAndRespond(), SimpleCache::accessTiming(), MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), BaseCache::allocateBlock(), SMMUv3DeviceInterface::atsRecvAtomic(), SMMUv3DeviceInterface::atsRecvTimingReq(), SMMUv3DeviceInterface::atsRecvTimingResp(), LSQUnit< Impl >::checkSnoop(), GPUCoalescer::coalescePacket(), LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeIfetch(), NoncoherentCache::createMissPacket(), Cache::createMissPacket(), IdeController::dispatchAccess(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), AddressMonitor::doMonitor(), SMMUTranslRequest::fromPacket(), MessageBuffer::functionalAccess(), AbstractMemory::functionalAccess(), BaseCache::functionalAccess(), RubySystem::functionalRead(), RubySystem::functionalWrite(), RubyRequest::functionalWrite(), getAddrRange(), getBlockAddr(), getOffset(), Prefetcher::Queued::getPacket(), NoncoherentCache::handleAtomicReqMiss(), BaseCache::handleFill(), MipsISA::handleLockedSnoop(), ArmISA::handleLockedSnoop(), RiscvISA::handleLockedSnoop(), Minor::Execute::handleMemResponse(), SimpleMemobj::handleRequest(), SimpleCache::handleRequest(), DmaPort::handleResp(), SimpleMemobj::handleResponse(), SimpleCache::handleResponse(), Cache::handleSnoop(), BaseCache::handleTimingReqMiss(), RubyPort::MemResponsePort::hitCallback(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), SimpleCache::insert(), BaseTags::insertBlock(), UncoalescedTable::insertPacket(), Sequencer::insertRequest(), I2CBus::isClockSet(), System::isDeviceMemAddr(), I2CBus::isEnd(), RubyPort::MemResponsePort::isPhysMemAddress(), I2CBus::isStart(), VIPERCoalescer::issueRequest(), Sequencer::issueRequest(), DMASequencer::makeRequest(), Sequencer::makeRequest(), GPUCoalescer::makeRequest(), matchAddr(), BaseCPU::mwait(), Prefetcher::BOP::notifyFill(), Prefetcher::SBOOE::notifyFill(), sc_gem5::packet2payload(), Prefetcher::Base::PrefetchInfo::PrefetchInfo(), print(), Prefetcher::Base::probeNotify(), QoS::MemSinkCtrl::processNextReqEvent(), SimpleUart::read(), PciVirtIO::read(), MmioVirtIO::read(), X86ISA::I8237::read(), MmDisk::read(), DumbTOD::read(), Sp805::read(), NoMaliGpu::read(), Pl011::read(), AmbaFake::read(), X86ISA::Speaker::read(), A9SCU::read(), IsaFake::read(), Uart8250::read(), X86ISA::Cmos::read(), X86ISA::I8254::read(), FVPBasePwrCtrl::read(), X86ISA::I82094AA::read(), HDLcd::read(), X86ISA::I8259::read(), Gicv2m::read(), PL031::read(), Gicv3::read(), EnergyCtrl::read(), Pl050::read(), Iob::read(), X86ISA::I8042::read(), I2CBus::read(), Gicv3Its::read(), Sp804::read(), A9GlobalTimer::read(), CopyEngine::read(), RealViewCtrl::read(), CpuLocalTimer::read(), VGic::read(), X86ISA::Interrupts::read(), Sinic::Device::read(), GenericPciHost::read(), NSGigE::read(), Pl111::read(), GenericTimerFrame::read(), IGbE::read(), GicV2::read(), GenericTimerMem::read(), LSQUnit< Impl >::read(), UFSHostDevice::read(), IdeController::readConfig(), PciDevice::readConfig(), SMMUv3::readControl(), GicV2::readCpu(), VGic::readCtrl(), GicV2::readDistributor(), AmbaDevice::readId(), Iob::readIob(), Iob::readJBus(), VGic::readVCpu(), Sequencer::recordMissLatency(), StubSlavePort::recvAtomic(), RubyPort::MemResponsePort::recvAtomic(), SMMUv3DeviceInterface::recvAtomic(), SMMUControlPort::recvAtomic(), RubyPort::PioResponsePort::recvAtomic(), AddrMapper::recvAtomic(), MemCtrl::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), Cache::recvAtomicSnoop(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), AddrMapper::recvAtomicSnoop(), RubyPort::MemResponsePort::recvFunctional(), NoncoherentXBar::recvFunctional(), MemCheckerMonitor::recvFunctional(), AddrMapper::recvFunctional(), MemCtrl::recvFunctional(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), MemCheckerMonitor::recvFunctionalSnoop(), AddrMapper::recvFunctionalSnoop(), X86ISA::Interrupts::recvMessage(), HMCController::recvTimingReq(), RubyPort::MemResponsePort::recvTimingReq(), SMMUv3DeviceInterface::recvTimingReq(), RubyPort::PioResponsePort::recvTimingReq(), NoncoherentXBar::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), Bridge::BridgeResponsePort::recvTimingReq(), DRAMSim2::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), DRAMsim3::recvTimingReq(), AddrMapper::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCtrl::recvTimingReq(), RubyDirectedTester::CpuPort::recvTimingResp(), RubyPort::MemRequestPort::recvTimingResp(), RubyPort::PioRequestPort::recvTimingResp(), AbstractController::recvTimingResp(), NoncoherentXBar::recvTimingResp(), SMMUv3::recvTimingResp(), TimingSimpleCPU::IcachePort::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), TimingSimpleCPU::DcachePort::recvTimingResp(), SerialLink::SerialLinkRequestPort::recvTimingResp(), Bridge::BridgeRequestPort::recvTimingResp(), BaseCache::recvTimingResp(), Minor::LSQ::recvTimingResp(), LSQ< Impl >::recvTimingResp(), Cache::recvTimingSnoopReq(), LSQ< Impl >::recvTimingSnoopReq(), Cache::recvTimingSnoopResp(), RubyPort::ruby_hit_callback(), HTMSequencer::rubyHtmCallback(), SMMUv3::runProcessTiming(), BaseCache::satisfyRequest(), PacketQueue::schedSendTiming(), TimingSimpleCPU::sendFetch(), Cache::sendMSHRQueuePacket(), NonCachingSimpleCPU::sendPacket(), ComputeUnit::sendRequest(), SimpleCache::sendResponse(), RiscvISA::Walker::WalkerState::stepWalk(), SMMUv3::tableWalkRecvTimingResp(), testAndRead(), testAndReadMask(), testAndWrite(), AtomicSimpleCPU::threadSnoop(), trySatisfyFunctional(), SerialLink::SerialLinkResponsePort::trySendTiming(), Bridge::BridgeResponsePort::trySendTiming(), SerialLink::SerialLinkRequestPort::trySendTiming(), Bridge::BridgeRequestPort::trySendTiming(), DmaPort::trySendTimingReq(), BaseTrafficGen::update(), I2CBus::updateSignals(), SimpleUart::write(), PciVirtIO::write(), MmioVirtIO::write(), X86ISA::I8237::write(), MmDisk::write(), Sp805::write(), NoMaliGpu::write(), Pl011::write(), AmbaFake::write(), X86ISA::Speaker::write(), A9SCU::write(), IsaFake::write(), Uart8250::write(), X86ISA::Cmos::write(), FVPBasePwrCtrl::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), HDLcd::write(), X86ISA::I8259::write(), Gicv2m::write(), PL031::write(), Gicv3::write(), EnergyCtrl::write(), Pl050::write(), Iob::write(), X86ISA::I8042::write(), I2CBus::write(), Gicv3Its::write(), Sp804::write(), CopyEngine::write(), A9GlobalTimer::write(), RealViewCtrl::write(), CpuLocalTimer::write(), VGic::write(), X86ISA::Interrupts::write(), Sinic::Device::write(), GenericPciHost::write(), HSAPacketProcessor::write(), NSGigE::write(), Pl111::write(), GenericTimerFrame::write(), IGbE::write(), GicV2::write(), GenericTimerMem::write(), UFSHostDevice::write(), IdeController::writeConfig(), PciDevice::writeConfig(), NSGigE::writeConfig(), IGbE::writeConfig(), SMMUv3::writeControl(), GicV2::writeCpu(), VGic::writeCtrl(), GicV2::writeDistributor(), Iob::writeIob(), Iob::writeJBus(), and VGic::writeVCpu().

◆ getAddrRange()

AddrRange Packet::getAddrRange ( ) const

Get address range to which this packet belongs.

Returns: Address range of this packet.

Definition at line 241 of file packet.cc.

References getAddr(), getSize(), and RangeSize().

Referenced by PhysicalMemory::access(), AbstractMemory::access(), PhysicalMemory::functionalAccess(), AbstractMemory::functionalAccess(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), NoncoherentXBar::recvFunctional(), CoherentXBar::recvFunctional(), NoncoherentXBar::recvTimingReq(), CoherentXBar::recvTimingReq(), and CoherentXBar::recvTimingSnoopReq().

◆ getAtomicOp()

AtomicOpFunctor* Packet::getAtomicOp ( ) const

inline

Accessor function to atomic op.

Definition at line 792 of file packet.hh.

References req.

Referenced by AbstractMemory::access(), VIPERCoalescer::issueRequest(), and BaseCache::satisfyRequest().

◆ getBE()

template<typename T >

T Packet::getBE

inline

Get the data in the packet byte swapped from big endian to host endian.

Definition at line 68 of file packet_access.hh.

References betoh().

Referenced by SparcISA::TLB::doMmuRegWrite(), Iob::writeIob(), and Iob::writeJBus().

◆ getBlockAddr()

Addr Packet::getBlockAddr ( unsigned int blk_size ) const

inline

◆ getConstPtr()

template<typename T >

const T* Packet::getConstPtr ( ) const

inline

◆ getHtmTransactionFailedInCacheRC()

HtmCacheFailure Packet::getHtmTransactionFailedInCacheRC ( ) const

If a packet/request has returned from the cache hierarchy in a failed transaction, this function returns the failure reason.

Definition at line 530 of file packet.cc.

References htmReturnReason, and htmTransactionFailedInCache().

Referenced by LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), and Packet().

◆ getHtmTransactionUid()

uint64_t Packet::getHtmTransactionUid ( ) const

If a packet/request originates in a CPU executing in transactional mode, i.e.

within a transaction, this function returns the unique ID of the transaction. This is used for verifying correctness and debugging.

Definition at line 550 of file packet.cc.

References flags, FROM_TRANSACTION, htmTransactionUid, and Flags< T >::isSet().

Referenced by LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), HTMSequencer::htmCallback(), Sequencer::issueRequest(), and Packet().

◆ getLE()

template<typename T >

T Packet::getLE

inline

Get the data in the packet byte swapped from little endian to host endian.

Definition at line 75 of file packet_access.hh.

References letoh().

Referenced by CopyEngine::CopyEngineChannel::channelWrite(), IdeController::dispatchAccess(), X86ISA::getMem(), X86ISA::getPackedMem(), ItsTranslation::main(), Sp804::Timer::read(), A9GlobalTimer::Timer::read(), IdeController::readConfig(), PciDevice::readConfig(), RiscvISA::Walker::WalkerState::stepWalk(), X86ISA::Walker::WalkerState::stepWalk(), PciVirtIO::write(), MmioVirtIO::write(), X86ISA::I8237::write(), NoMaliGpu::write(), Pl011::write(), X86ISA::Speaker::write(), IsaFake::write(), X86ISA::Cmos::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), HDLcd::write(), X86ISA::I8259::write(), Gicv2m::write(), Sp804::Timer::write(), PL031::write(), EnergyCtrl::write(), A9GlobalTimer::Timer::write(), X86ISA::I8042::write(), CpuLocalTimer::Timer::write(), Gicv3Its::write(), CopyEngine::write(), RealViewCtrl::write(), Sinic::Device::write(), HSAPacketProcessor::write(), NSGigE::write(), Pl111::write(), IGbE::write(), UFSHostDevice::write(), IdeController::writeConfig(), PciDevice::writeConfig(), SMMUv3::writeControl(), GicV2::writeCpu(), VGic::writeCtrl(), GicV2::writeDistributor(), and VGic::writeVCpu().

◆ getOffset()

Addr Packet::getOffset ( unsigned int blk_size ) const

inline

Definition at line 773 of file packet.hh.

References getAddr().

Referenced by BaseCache::cmpAndSwap(), isWholeLineWrite(), Cache::promoteWholeLineWrites(), BaseCache::satisfyRequest(), NoncoherentCache::serviceMSHRTargets(), Cache::serviceMSHRTargets(), setDataFromBlock(), MSHR::TargetList::updateWriteFlags(), and writeDataToBlock().

◆ getPtr()

template<typename T >

T* Packet::getPtr ( )

inline

◆ getRaw()

template<typename T >

T Packet::getRaw

inline

Get the data in the packet without byte swapping.

Definition at line 49 of file packet_access.hh.

References data, DYNAMIC_DATA, flags, Flags< T >::isSet(), size, and STATIC_DATA.

Referenced by I2CBus::isClockSet(), I2CBus::isEnd(), I2CBus::isStart(), X86ISA::Interrupts::recvMessage(), I2CBus::updateSignals(), MmDisk::write(), and Uart8250::write().

◆ getSize()

unsigned Packet::getSize ( ) const

inline

Definition at line 764 of file packet.hh.

References flags, Flags< T >::isSet(), size, and VALID_SIZE.

Referenced by AbstractMemory::access(), BaseCache::access(), SimpleCache::accessTiming(), MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), allocate(), SMMUv3DeviceInterface::atsRecvAtomic(), SMMUv3DeviceInterface::atsRecvTimingReq(), SMMUv3DeviceInterface::atsRecvTimingResp(), BaseXBar::calcPacketTiming(), BaseCache::cmpAndSwap(), IdeController::dispatchAccess(), SMMUProcess::doRead(), ItsProcess::doRead(), ItsProcess::doWrite(), SMMUTranslRequest::fromPacket(), RubyRequest::functionalWrite(), getAddrRange(), getUintX(), BaseCache::handleFill(), Minor::Execute::handleMemResponse(), Cache::handleTimingReqMiss(), BaseCache::handleTimingReqMiss(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), HTMSequencer::htmCallback(), VIPERCoalescer::issueRequest(), Sequencer::issueRequest(), isWholeLineWrite(), DMASequencer::makeRequest(), sc_gem5::packet2payload(), print(), QoS::MemSinkCtrl::processNextReqEvent(), Cache::promoteWholeLineWrites(), MmioVirtIO::read(), PciVirtIO::read(), X86ISA::I8237::read(), MmDisk::read(), Sp805::read(), DumbTOD::read(), NoMaliGpu::read(), Pl011::read(), A9SCU::read(), X86ISA::Speaker::read(), IsaFake::read(), Uart8250::read(), X86ISA::Cmos::read(), FVPBasePwrCtrl::read(), X86ISA::I8254::read(), X86ISA::I82094AA::read(), HDLcd::read(), X86ISA::I8259::read(), PL031::read(), Gicv3::read(), EnergyCtrl::read(), X86ISA::I8042::read(), Sp804::read(), A9GlobalTimer::read(), CopyEngine::read(), RealViewCtrl::read(), CpuLocalTimer::read(), X86ISA::Interrupts::read(), Sinic::Device::read(), GenericPciHost::read(), NSGigE::read(), Pl111::read(), GenericTimerFrame::read(), IGbE::read(), GenericTimerMem::read(), IdeController::readConfig(), PciDevice::readConfig(), VirtIODeviceBase::readConfigBlob(), SMMUv3::readControl(), GicV2::readDistributor(), StubSlavePort::recvAtomic(), RubyPort::MemResponsePort::recvAtomic(), SMMUv3DeviceInterface::recvAtomic(), SMMUControlPort::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), RubyPort::MemResponsePort::recvFunctional(), MemCheckerMonitor::recvFunctional(), MemCheckerMonitor::recvFunctionalSnoop(), HMCController::recvTimingReq(), SMMUv3DeviceInterface::recvTimingReq(), NoncoherentXBar::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCtrl::recvTimingReq(), NoncoherentXBar::recvTimingResp(), SMMUv3::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), SerialLink::SerialLinkRequestPort::recvTimingResp(), CoherentXBar::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopResp(), Minor::LSQ::SplitDataRequest::retireResponse(), SMMUv3::runProcessTiming(), Cache::satisfyRequest(), BaseCache::satisfyRequest(), PacketQueue::schedSendTiming(), QoS::Policy::schedule(), QoS::MemCtrl::schedule(), BaseCache::sendMSHRQueuePacket(), ComputeUnit::sendRequest(), Cache::serviceMSHRTargets(), setData(), setUintX(), RiscvISA::Walker::WalkerState::stepWalk(), X86ISA::Walker::WalkerState::stepWalk(), SMMUv3::tableWalkRecvTimingResp(), testAndRead(), testAndReadMask(), testAndWrite(), trySatisfyFunctional(), SerialLink::SerialLinkResponsePort::trySendTiming(), SerialLink::SerialLinkRequestPort::trySendTiming(), MSHR::TargetList::updateWriteFlags(), MmioVirtIO::write(), PciVirtIO::write(), X86ISA::I8237::write(), MmDisk::write(), Sp805::write(), NoMaliGpu::write(), Pl011::write(), X86ISA::Speaker::write(), IsaFake::write(), Uart8250::write(), X86ISA::Cmos::write(), FVPBasePwrCtrl::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), HDLcd::write(), X86ISA::I8259::write(), PL031::write(), Gicv3::write(), EnergyCtrl::write(), Pl050::write(), X86ISA::I8042::write(), Gicv3Its::write(), Sp804::write(), CopyEngine::write(), A9GlobalTimer::write(), CpuLocalTimer::write(), X86ISA::Interrupts::write(), Sinic::Device::write(), GenericPciHost::write(), HSAPacketProcessor::write(), NSGigE::write(), Pl111::write(), GenericTimerFrame::write(), IGbE::write(), GenericTimerMem::write(), UFSHostDevice::write(), IdeController::writeConfig(), PciDevice::writeConfig(), VirtIODeviceBase::writeConfigBlob(), SMMUv3::writeControl(), writeData(), and GicV2::writeDistributor().

◆ getUintX()

uint64_t Packet::getUintX ( ByteOrder endian ) const

Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.

Definition at line 350 of file packet.cc.

References getSize(), and panic.

Referenced by Sp805::read(), Pl011::read(), PL031::read(), Pl050::read(), Pl111::read(), SimpleUart::write(), Sp805::write(), FVPBasePwrCtrl::write(), Gicv3::write(), Pl050::write(), Pl111::write(), GenericTimerFrame::write(), and GenericTimerMem::write().

◆ hasData()

bool Packet::hasData ( ) const

inline

◆ hasRespData()

bool Packet::hasRespData ( ) const

inline

Definition at line 577 of file packet.hh.

References cmd, MemCmd::hasData(), and MemCmd::responseCommand().

Referenced by allocate(), replaceUpgrade(), BaseCache::satisfyRequest(), and Cache::serviceMSHRTargets().

◆ hasSharers()

bool Packet::hasSharers ( ) const

inline

◆ htmTransactionFailedInCache()

bool Packet::htmTransactionFailedInCache ( ) const

Returns whether or not this packet/request has returned from the cache hierarchy in a failed transaction.

The core is notified liked this.

Definition at line 524 of file packet.cc.

References FAILS_TRANSACTION, flags, and Flags< T >::isSet().

Referenced by LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), getHtmTransactionFailedInCacheRC(), Packet(), RubyPort::MemRequestPort::recvTimingResp(), TimingSimpleCPU::IcachePort::recvTimingResp(), and LSQUnit< Impl >::writeback().

◆ isAtomicOp()

bool Packet::isAtomicOp ( ) const

inline

Definition at line 793 of file packet.hh.

References req.

Referenced by AbstractMemory::access(), VIPERCoalescer::issueRequest(), VIPERCoalescer::makeRequest(), and BaseCache::satisfyRequest().

◆ isBlockCached()

bool Packet::isBlockCached ( ) const

inline

Definition at line 720 of file packet.hh.

References BLOCK_CACHED, flags, and Flags< T >::isSet().

Referenced by Cache::handleSnoop(), Cache::isCachedAbove(), SnoopFilter::lookupRequest(), Cache::sendMSHRQueuePacket(), and CoherentXBar::sinkPacket().

◆ isClean()

bool Packet::isClean ( ) const

inline

Definition at line 573 of file packet.hh.

References cmd, and MemCmd::isClean().

Referenced by AbstractMemory::access(), Cache::createMissPacket(), CoherentXBar::forwardPacket(), Cache::handleSnoop(), MSHR::handleSnoop(), MSHR::isCleaning(), BaseCache::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvTimingReq(), BaseCache::recvTimingResp(), BaseCache::satisfyRequest(), and BaseCache::sendMSHRQueuePacket().

◆ isCleanEviction()

bool Packet::isCleanEviction ( ) const

inline

Is this packet a clean eviction, including both actual clean evict packets, but also clean writebacks.

Definition at line 1367 of file packet.hh.

References MemCmd::CleanEvict, cmd, and MemCmd::WritebackClean.

Referenced by BaseCache::access(), and CoherentXBar::sinkPacket().

◆ isError()

bool Packet::isError ( ) const

inline

◆ isEviction()

bool Packet::isEviction ( ) const

inline

Definition at line 572 of file packet.hh.

References cmd, and MemCmd::isEviction().

Referenced by BaseCache::access(), WriteQueueEntry::allocate(), Cache::createMissPacket(), Cache::handleAtomicReqMiss(), BaseCache::handleTimingReqMiss(), Cache::isCachedAbove(), SnoopFilter::lookupRequest(), mustCheckAbove(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvTimingReq(), and Cache::recvTimingSnoopReq().

◆ isExpressSnoop()

bool Packet::isExpressSnoop ( ) const

inline

Definition at line 662 of file packet.hh.

References EXPRESS_SNOOP, flags, and Flags< T >::isSet().

Referenced by MSHR::handleSnoop(), print(), HMCController::recvTimingReq(), NoncoherentXBar::recvTimingReq(), CoherentXBar::recvTimingReq(), CoherentXBar::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopResp(), PacketQueue::schedSendTiming(), and BaseCache::CpuSidePort::tryTiming().

◆ isFlush()

bool Packet::isFlush ( ) const

inline

Definition at line 585 of file packet.hh.

References cmd, and MemCmd::isFlush().

Referenced by GPUCoalescer::getRequestType(), RubyPort::MemResponsePort::hitCallback(), Sequencer::hitCallback(), Sequencer::issueRequest(), and Sequencer::makeRequest().

◆ isHtmTransactional()

bool Packet::isHtmTransactional ( ) const

Returns whether or not this packet/request originates in the CPU executing in transactional mode, i.e.

within a transaction.

Definition at line 544 of file packet.cc.

References flags, FROM_TRANSACTION, and Flags< T >::isSet().

Referenced by LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), Sequencer::issueRequest(), and Packet().

◆ isInvalidate()

bool Packet::isInvalidate ( ) const

inline

Definition at line 571 of file packet.hh.

References cmd, and MemCmd::isInvalidate().

Referenced by AbstractMemory::access(), LSQUnit< Impl >::checkSnoop(), Cache::doTimingSupplyResponse(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), ArmISA::handleLockedSnoop(), Cache::handleSnoop(), MSHR::handleSnoop(), SnoopFilter::lookupSnoop(), Prefetcher::Base::observeAccess(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), NoncoherentCache::recvTimingResp(), BaseCache::recvTimingResp(), LSQ< Impl >::recvTimingResp(), Cache::recvTimingSnoopReq(), TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), Minor::LSQ::recvTimingSnoopReq(), LSQ< Impl >::recvTimingSnoopReq(), BaseCache::satisfyRequest(), Cache::serviceMSHRTargets(), Minor::LSQ::threadSnoop(), and SnoopFilter::updateResponse().

◆ isLLSC()

bool Packet::isLLSC ( ) const

inline

Definition at line 582 of file packet.hh.

References cmd, and MemCmd::isLLSC().

Referenced by AbstractMemory::access(), BaseCache::access(), AbstractMemory::checkLockedAddrList(), CacheBlk::checkWrite(), convertLlToRead(), convertScToWrite(), Cache::createMissPacket(), RubyPort::MemResponsePort::hitCallback(), Sequencer::makeRequest(), MemCheckerMonitor::recvTimingResp(), BaseCache::satisfyRequest(), CacheBlk::trackLoadLocked(), and AbstractMemory::writeOK().

◆ isMaskedWrite()

bool Packet::isMaskedWrite ( ) const

inline

Definition at line 1373 of file packet.hh.

References cmd, req, and MemCmd::WriteReq.

Referenced by getPtr(), Cache::promoteWholeLineWrites(), trySatisfyFunctional(), and writeData().

◆ isPrint()

bool Packet::isPrint ( ) const

inline

Definition at line 584 of file packet.hh.

References cmd, and MemCmd::isPrint().

Referenced by AbstractMemory::functionalAccess(), popLabel(), pushLabel(), NoncoherentXBar::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), WriteQueueEntry::trySatisfyFunctional(), MSHR::trySatisfyFunctional(), and trySatisfyFunctional().

◆ isRead()

bool Packet::isRead ( ) const

inline

Definition at line 556 of file packet.hh.

References cmd, and MemCmd::isRead().

Referenced by AbstractMemory::access(), BaseCache::access(), SimpleCache::accessFunctional(), SimpleCache::accessTiming(), MemTest::completeRequest(), convertLlToRead(), SimpleMemDelay::delayReq(), SimpleMemDelay::delayResp(), Cache::doTimingSupplyResponse(), CoherentXBar::forwardPacket(), AbstractMemory::functionalAccess(), GPUCoalescer::getRequestType(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), BaseCache::handleFill(), TimingSimpleCPU::handleReadPacket(), Cache::handleSnoop(), Cache::handleTimingReqMiss(), Sequencer::makeRequest(), GPUCoalescer::makeRequest(), Prefetcher::Base::observeAccess(), sc_gem5::packet2payload(), ComputeUnit::DataPort::processMemRespEvent(), QoS::MemSinkCtrl::processNextReqEvent(), PioPort< X86ISA::Interrupts >::recvAtomic(), NoncoherentCache::recvAtomic(), SMMUControlPort::recvAtomic(), RubyPort::MemResponsePort::recvFunctional(), RiscvISA::Walker::WalkerState::recvPacket(), X86ISA::Walker::WalkerState::recvPacket(), TimingSimpleCPU::DcachePort::recvReqRetry(), NoncoherentCache::recvTimingReq(), SimpleMemory::recvTimingReq(), DRAMSim2::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), DRAMsim3::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CommMonitor::recvTimingReq(), MemCtrl::recvTimingReq(), NoncoherentCache::recvTimingResp(), AbstractController::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), BaseCache::recvTimingResp(), ComputeUnit::ScalarDataPort::recvTimingResp(), Cache::recvTimingSnoopReq(), NoncoherentCache::satisfyRequest(), Cache::satisfyRequest(), BaseCache::satisfyRequest(), ComputeUnit::sendRequest(), ComputeUnit::sendScalarRequest(), Cache::serviceMSHRTargets(), CoherentXBar::sinkPacket(), and trySatisfyFunctional().

◆ isRequest()

bool Packet::isRequest ( ) const

inline

Definition at line 559 of file packet.hh.

References cmd, and MemCmd::isRequest().

Referenced by Cache::access(), PhysicalMemory::access(), BaseCache::access(), BaseCache::cmpAndSwap(), copyResponderFlags(), Cache::doTimingSupplyResponse(), PhysicalMemory::functionalAccess(), Cache::handleSnoop(), X86ISA::GpuTLB::handleTranslationReturn(), SnoopFilter::lookupSnoop(), makeHtmTransactionalReqResponse(), makeResponse(), needsWritable(), MemCheckerMonitor::recvTimingReq(), CommMonitor::recvTimingReq(), BaseCache::CpuSidePort::recvTimingReq(), RubyPort::ruby_hit_callback(), HTMSequencer::rubyHtmCallback(), BaseCache::satisfyRequest(), FunctionalRequestProtocol::send(), AtomicRequestProtocol::send(), AtomicRequestProtocol::sendBackdoor(), TimingRequestProtocol::sendReq(), FunctionalResponseProtocol::sendSnoop(), AtomicResponseProtocol::sendSnoop(), TimingResponseProtocol::sendSnoopReq(), setCacheResponding(), TimingRequestProtocol::trySend(), and TLBCoalescer::updatePhysAddresses().

◆ isResponse()

bool Packet::isResponse ( ) const

inline

Definition at line 560 of file packet.hh.

References cmd, and MemCmd::isResponse().

Referenced by DRAMSim2::accessAndRespond(), DRAMsim3::accessAndRespond(), MemCtrl::accessAndRespond(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::b_transport(), GarnetSyntheticTraffic::completeRequest(), CoherentXBar::forwardAtomic(), CoherentXBar::forwardFunctional(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), BaseCache::handleFill(), DmaPort::handleResp(), Cache::handleSnoop(), RubyPort::MemResponsePort::hitCallback(), SimpleCache::insert(), PioPort< X86ISA::Interrupts >::recvAtomic(), CommMonitor::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), RubyPort::MemResponsePort::recvFunctional(), CoherentXBar::recvFunctional(), RiscvISA::Walker::WalkerState::recvPacket(), X86ISA::Walker::WalkerState::recvPacket(), SimpleTimingPort::recvTimingReq(), SimpleMemory::recvTimingReq(), RubyPort::MemRequestPort::recvTimingResp(), NoncoherentCache::recvTimingResp(), X86ISA::IntRequestPort< X86ISA::I82094AA >::recvTimingResp(), AbstractController::recvTimingResp(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), BaseCache::recvTimingResp(), BaseCache::CpuSidePort::recvTimingSnoopResp(), TimingResponseProtocol::sendResp(), TimingRequestProtocol::sendSnoopResp(), setBadAddress(), SnoopFilter::updateResponse(), SnoopFilter::updateSnoopForward(), and SnoopFilter::updateSnoopResponse().

◆ isSecure()

bool Packet::isSecure ( ) const

inline

Definition at line 783 of file packet.hh.

References _isSecure, flags, Flags< T >::isSet(), and VALID_ADDR.

Referenced by Cache::access(), BaseCache::access(), WriteQueueEntry::allocate(), MSHR::allocate(), BaseCache::allocateBlock(), BaseCache::allocateWriteBuffer(), BaseCache::functionalAccess(), BaseCache::getNextQueueEntry(), BaseCache::handleFill(), NoncoherentCache::handleTimingReqMiss(), Cache::handleTimingReqMiss(), BaseTags::insertBlock(), SnoopFilter::lookupRequest(), SnoopFilter::lookupSnoop(), matchAddr(), matchBlockAddr(), Prefetcher::Base::probeNotify(), Gicv3::read(), GenericTimerFrame::read(), GenericTimerMem::read(), CoherentXBar::recvAtomicBackdoor(), Cache::recvAtomicSnoop(), CoherentXBar::recvTimingReq(), BaseCache::recvTimingResp(), Cache::recvTimingSnoopReq(), Cache::recvTimingSnoopResp(), Cache::sendMSHRQueuePacket(), trySatisfyFunctional(), SnoopFilter::updateResponse(), SnoopFilter::updateSnoopForward(), SnoopFilter::updateSnoopResponse(), Gicv3::write(), GenericTimerFrame::write(), and GenericTimerMem::write().

◆ isUpgrade()

bool Packet::isUpgrade ( ) const

inline

Definition at line 558 of file packet.hh.

References cmd, and MemCmd::isUpgrade().

Referenced by Cache::createMissPacket(), BaseCache::satisfyRequest(), and MSHR::TargetList::updateFlags().

◆ isWholeLineWrite()

bool Packet::isWholeLineWrite ( unsigned blk_size )

inline

Definition at line 587 of file packet.hh.

References cmd, getOffset(), getSize(), MemCmd::WriteLineReq, and MemCmd::WriteReq.

Referenced by NoncoherentCache::handleAtomicReqMiss(), and Cache::handleAtomicReqMiss().

◆ isWrite()

bool Packet::isWrite ( ) const

inline

Definition at line 557 of file packet.hh.

References cmd, and MemCmd::isWrite().

Referenced by Cache::access(), AbstractMemory::access(), BaseCache::access(), SimpleCache::accessFunctional(), SimpleCache::accessTiming(), MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), WriteQueueEntry::allocate(), BaseCache::allocateWriteBuffer(), CacheBlk::checkWrite(), LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), TraceCPU::ElasticDataGen::completeMemAccess(), GarnetSyntheticTraffic::completeRequest(), MemTest::completeRequest(), convertScToWrite(), SimpleMemDelay::delayReq(), SimpleMemDelay::delayResp(), CoherentXBar::forwardPacket(), SMMUTranslRequest::fromPacket(), AbstractMemory::functionalAccess(), SequencerRequest::functionalWrite(), GPUCoalescer::getRequestType(), Cache::handleAtomicReqMiss(), ArmISA::handleLockedSnoop(), Cache::handleTimingReqMiss(), BaseCache::handleTimingReqMiss(), RubyPort::MemResponsePort::hitCallback(), VIPERCoalescer::issueRequest(), DMASequencer::makeRequest(), Sequencer::makeRequest(), GPUCoalescer::makeRequest(), sc_gem5::packet2payload(), Prefetcher::Base::probeNotify(), NoncoherentCache::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), RubyPort::MemResponsePort::recvFunctional(), TimingSimpleCPU::DcachePort::recvReqRetry(), NoncoherentCache::recvTimingReq(), SMMUv3DeviceInterface::recvTimingReq(), SimpleMemory::recvTimingReq(), DRAMSim2::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), DRAMsim3::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CommMonitor::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCtrl::recvTimingReq(), BaseTrafficGen::recvTimingResp(), AbstractController::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), BaseCache::recvTimingResp(), ComputeUnit::ScalarDataPort::recvTimingResp(), TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), Minor::LSQ::recvTimingSnoopReq(), NoncoherentCache::satisfyRequest(), BaseCache::satisfyRequest(), BaseCache::sendMSHRQueuePacket(), ComputeUnit::sendRequest(), ComputeUnit::sendScalarRequest(), setFunctionalResponseStatus(), CoherentXBar::sinkPacket(), Minor::LSQ::threadSnoop(), trySatisfyFunctional(), and MSHR::TargetList::updateWriteFlags().

◆ isWriteback()

bool Packet::isWriteback ( ) const

inline

Definition at line 575 of file packet.hh.

References cmd, and MemCmd::isWriteback().

Referenced by NoncoherentCache::access(), BaseCache::access(), NoncoherentCache::handleAtomicReqMiss(), BaseCache::handleTimingReqMiss(), SnoopFilter::lookupSnoop(), and SnoopFilter::updateSnoopResponse().

◆ makeAtomicResponse()

void Packet::makeAtomicResponse ( )

inline

Definition at line 1016 of file packet.hh.

References makeResponse().

Referenced by SMMUTranslationProcess::completeTransaction(), IdeController::dispatchAccess(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), Cache::handleSnoop(), SimpleUart::read(), X86ISA::I8237::read(), MmDisk::read(), DumbTOD::read(), Pl011::read(), AmbaFake::read(), A9SCU::read(), X86ISA::Speaker::read(), IsaFake::read(), Uart8250::read(), X86ISA::Cmos::read(), X86ISA::I8254::read(), X86ISA::I82094AA::read(), HDLcd::read(), X86ISA::I8259::read(), Gicv2m::read(), PL031::read(), Gicv3::read(), EnergyCtrl::read(), Pl050::read(), Iob::read(), X86ISA::I8042::read(), I2CBus::read(), Gicv3Its::read(), Sp804::read(), A9GlobalTimer::read(), CopyEngine::read(), RealViewCtrl::read(), CpuLocalTimer::read(), X86ISA::Interrupts::read(), GenericPciHost::read(), HSAPacketProcessor::read(), NSGigE::read(), Pl111::read(), IGbE::read(), IdeController::readConfig(), PciDevice::readConfig(), SMMUv3::readControl(), GicV2::readCpu(), VGic::readCtrl(), GicV2::readDistributor(), VGic::readVCpu(), BaseCache::recvAtomic(), X86ISA::Interrupts::recvMessage(), SimpleUart::write(), X86ISA::I8237::write(), MmDisk::write(), NoMaliGpu::write(), Pl011::write(), AmbaFake::write(), X86ISA::Speaker::write(), A9SCU::write(), IsaFake::write(), Uart8250::write(), X86ISA::Cmos::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), HDLcd::write(), X86ISA::I8259::write(), Gicv2m::write(), PL031::write(), Gicv3::write(), EnergyCtrl::write(), Pl050::write(), Iob::write(), X86ISA::I8042::write(), Gicv3Its::write(), Sp804::write(), CopyEngine::write(), A9GlobalTimer::write(), RealViewCtrl::write(), CpuLocalTimer::write(), X86ISA::Interrupts::write(), HSAPacketProcessor::write(), NSGigE::write(), Pl111::write(), IGbE::write(), IdeController::writeConfig(), PciDevice::writeConfig(), SMMUv3::writeControl(), GicV2::writeCpu(), VGic::writeCtrl(), GicV2::writeDistributor(), and VGic::writeVCpu().

◆ makeHtmTransactionalReqResponse()

void Packet::makeHtmTransactionalReqResponse ( const HtmCacheFailure ret_code )

Communicates to the core that a packet was processed by the memory subsystem while running in transactional mode.

It may happen that the transaction has failed at the memory subsystem and this needs to be communicated to the core somehow. This function decorates the response packet with flags to indicate such a situation has occurred.

Definition at line 498 of file packet.cc.

References Flags< T >::clear(), cmd, EXPRESS_SNOOP, flags, isRequest(), needsResponse(), MemCmd::responseCommand(), and setHtmTransactionFailedInCache().

Referenced by HTMSequencer::rubyHtmCallback().

◆ makeReadCmd()

static MemCmd Packet::makeReadCmd ( const RequestPtr & req )

inlinestatic

Generate the appropriate read MemCmd based on the Request flags.

Definition at line 939 of file packet.hh.

References MemCmd::HTMAbort, MemCmd::HTMReq, MemCmd::LoadLockedReq, MemCmd::ReadReq, req, MemCmd::SoftPFExReq, and MemCmd::SoftPFReq.

Referenced by createRead(), and AtomicSimpleCPU::readMem().

◆ makeResponse()

void Packet::makeResponse ( )

inline

Take a request packet and modify it in place to be suitable for returning as a response to that request.

Definition at line 1004 of file packet.hh.

References Flags< T >::clear(), cmd, EXPRESS_SNOOP, flags, isRequest(), needsResponse(), and MemCmd::responseCommand().

Referenced by AbstractMemory::access(), SimpleCache::accessTiming(), AbstractMemory::functionalAccess(), BaseCache::functionalAccess(), SimpleCache::handleFunctional(), SimpleCache::handleResponse(), RubyPort::MemResponsePort::hitCallback(), makeAtomicResponse(), makeTimingResponse(), StubSlavePort::processResponseEvent(), MmioVirtIO::read(), PciVirtIO::read(), Sp805::read(), NoMaliGpu::read(), FVPBasePwrCtrl::read(), GenericTimerFrame::read(), GenericTimerMem::read(), LSQUnit< Impl >::read(), UFSHostDevice::read(), VirtIODeviceBase::readConfigBlob(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomic(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), RubyPort::MemResponsePort::recvFunctional(), MemDelay::ResponsePort::recvFunctional(), NoncoherentXBar::recvFunctional(), SerialLink::SerialLinkResponsePort::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), CoherentXBar::recvFunctional(), MemDelay::RequestPort::recvFunctionalSnoop(), CoherentXBar::recvFunctionalSnoop(), RubyPort::MemResponsePort::recvTimingReq(), CoherentXBar::recvTimingReq(), TimingSimpleCPU::sendData(), TimingSimpleCPU::sendSplitData(), SerialLink::SerialLinkRequestPort::trySatisfyFunctional(), Bridge::BridgeRequestPort::trySatisfyFunctional(), Minor::LSQ::tryToSendToTransfers(), PciVirtIO::write(), MmioVirtIO::write(), Sp805::write(), FVPBasePwrCtrl::write(), GenericTimerFrame::write(), GenericTimerMem::write(), UFSHostDevice::write(), and VirtIODeviceBase::writeConfigBlob().

◆ makeTimingResponse()

void Packet::makeTimingResponse ( )

inline

Definition at line 1022 of file packet.hh.

References makeResponse().

Referenced by SMMUTranslationProcess::completeTransaction(), Cache::doTimingSupplyResponse(), BaseCache::handleTimingReqHit(), Cache::handleTimingReqMiss(), X86ISA::GpuTLB::handleTranslationReturn(), LdsState::process(), NoncoherentCache::serviceMSHRTargets(), Cache::serviceMSHRTargets(), and TLBCoalescer::updatePhysAddresses().

◆ makeWriteCmd()

static MemCmd Packet::makeWriteCmd ( const RequestPtr & req )

inlinestatic

Generate the appropriate write MemCmd based on the Request flags.

Definition at line 960 of file packet.hh.

References MemCmd::CleanInvalidReq, MemCmd::CleanSharedReq, MemCmd::InvalidateReq, req, MemCmd::StoreCondReq, MemCmd::SwapReq, and MemCmd::WriteReq.

Referenced by AtomicSimpleCPU::amoMem(), createWrite(), and AtomicSimpleCPU::writeMem().

◆ matchAddr() [1/2]

bool Packet::matchAddr	(	const Addr	addr,
		const bool	is_secure
	)		const

Check if packet corresponds to a given address and address space.

Parameters

addr	The address to compare against.
is_secure	Whether addr belongs to the secure address space.

Returns: Whether packet matches description.

Definition at line 424 of file packet.cc.

References addr, getAddr(), and isSecure().

Referenced by matchAddr(), and Cache::serviceMSHRTargets().

◆ matchAddr() [2/2]

bool Packet::matchAddr ( const PacketPtr pkt ) const

Check if this packet refers to the same address and address space as another packet.

Parameters

pkt	The packet to compare against.

Returns: Whether packet matches description.

Definition at line 430 of file packet.cc.

References getAddr(), isSecure(), and matchAddr().

◆ matchBlockAddr() [1/2]

bool Packet::matchBlockAddr	(	const Addr	addr,
		const bool	is_secure,
		const int	blk_size
	)		const

Check if packet corresponds to a given block-aligned address and address space.

Parameters

addr	The address to compare against.
is_secure	Whether addr belongs to the secure address space.
blk_size	Block size in bytes.

Returns: Whether packet matches description.

Definition at line 410 of file packet.cc.

References addr, getBlockAddr(), and isSecure().

Referenced by WriteQueueEntry::allocate(), MSHR::allocate(), WriteQueueEntry::matchBlockAddr(), MSHR::matchBlockAddr(), and matchBlockAddr().

◆ matchBlockAddr() [2/2]

bool Packet::matchBlockAddr	(	const PacketPtr	pkt,
		const int	blk_size
	)		const

Check if this packet refers to the same block-aligned address and address space as another packet.

Parameters

pkt	The packet to compare against.
blk_size	Block size in bytes.

Returns: Whether packet matches description.

Definition at line 417 of file packet.cc.

References getBlockAddr(), isSecure(), and matchBlockAddr().

◆ mustCheckAbove()

bool Packet::mustCheckAbove ( ) const

inline

Does the request need to check for cached copies of the same block in the memory hierarchy above.

Definition at line 1357 of file packet.hh.

References cmd, MemCmd::HardPFReq, and isEviction().

Referenced by Cache::handleSnoop(), and Cache::recvTimingSnoopReq().

◆ needsResponse()

bool Packet::needsResponse ( ) const

inline

Definition at line 570 of file packet.hh.

References cmd, and MemCmd::needsResponse().

Referenced by AbstractMemory::access(), BaseCache::access(), DRAMSim2::accessAndRespond(), DRAMsim3::accessAndRespond(), MemCtrl::accessAndRespond(), SimpleCache::accessTiming(), BaseTrafficGen::allocateWaitingRespSlot(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::b_transport(), NoncoherentCache::createMissPacket(), Cache::createMissPacket(), Cache::doTimingSupplyResponse(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::handleBeginReq(), Cache::handleSnoop(), MSHR::handleSnoop(), BaseCache::handleTimingReqHit(), Cache::handleTimingReqMiss(), RubyPort::MemResponsePort::hitCallback(), SnoopFilter::lookupRequest(), makeHtmTransactionalReqResponse(), makeResponse(), QoS::MemSinkCtrl::processNextReqEvent(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomic(), CommMonitor::recvAtomic(), BaseCache::recvAtomic(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), RubyPort::MemResponsePort::recvFunctional(), NoncoherentXBar::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), SimpleTimingPort::recvTimingReq(), HMCController::recvTimingReq(), NoncoherentXBar::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), Bridge::BridgeResponsePort::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), AddrMapper::recvTimingReq(), CommMonitor::recvTimingReq(), CoherentXBar::recvTimingReq(), Cache::recvTimingSnoopReq(), HTMSequencer::rubyHtmCallback(), CoherentXBar::sinkPacket(), and Minor::Fetch1::tryToSendToTransfers().

◆ needsWritable()

bool Packet::needsWritable ( ) const

inline

Definition at line 561 of file packet.hh.

References cmd, isRequest(), and MemCmd::needsWritable().

Referenced by BaseCache::access(), MSHR::allocateTarget(), Cache::handleAtomicReqMiss(), Cache::handleSnoop(), MSHR::handleSnoop(), BaseCache::handleTimingReqMiss(), SnoopFilter::lookupSnoop(), Cache::recvAtomic(), Cache::recvTimingReq(), Cache::recvTimingSnoopReq(), Cache::satisfyRequest(), Cache::serviceMSHRTargets(), CoherentXBar::sinkPacket(), and MSHR::TargetList::updateFlags().

◆ popLabel()

void Packet::popLabel ( )

inline

Pop label for PrintReq (safe to call unconditionally).

Definition at line 1403 of file packet.hh.

References isPrint(), and senderState.

Referenced by BaseCache::functionalAccess(), QoS::MemSinkCtrl::MemoryPort::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkResponsePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), DRAMsim3::recvFunctional(), QoS::MemSinkCtrl::recvFunctional(), MemCtrl::MemoryPort::recvFunctional(), Queue< WriteQueueEntry >::trySatisfyFunctional(), and PacketQueue::trySatisfyFunctional().

◆ popSenderState()

Packet::SenderState * Packet::popSenderState ( )

Pop the top of the state stack and return a pointer to it.

This assumes the current sender state is not NULL. This should be preferred over direct manipulation of the senderState member variable.

Returns: The current top of the stack

Definition at line 340 of file packet.cc.

References Packet::SenderState::predecessor, and senderState.

◆ print() [1/2]

std::string Packet::print ( ) const

A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overheads in fast mode.

Returns: string with the request's type and start<->end addresses

Definition at line 403 of file packet.cc.

◆ print() [2/2]

void Packet::print	(	std::ostream &	o,
		int	verbosity = `0`,
		const std::string &	prefix = `""`
	)		const

virtual

Implements Printable.

Definition at line 389 of file packet.cc.

References ccprintf(), cmdString(), getAddr(), getSize(), isExpressSnoop(), and req.

Referenced by Cache::access(), AbstractMemory::access(), BaseCache::access(), MemCtrl::accessAndRespond(), SimpleCache::accessTiming(), BaseCache::allocateWriteBuffer(), Cache::cleanEvictBlk(), NoncoherentCache::createMissPacket(), Cache::createMissPacket(), Cache::doTimingSupplyResponse(), CoherentXBar::forwardTiming(), BaseCache::functionalAccess(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), Cache::handleSnoop(), MSHR::handleSnoop(), BaseCache::handleTimingReqHit(), BaseCache::handleTimingReqMiss(), SimpleCache::insert(), SnoopFilter::lookupRequest(), SnoopFilter::lookupSnoop(), Cache::recvAtomic(), BaseCache::recvAtomic(), MemCtrl::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), NoncoherentCache::recvAtomicSnoop(), CoherentXBar::recvAtomicSnoop(), CoherentXBar::recvFunctional(), MemCtrl::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), SimpleCache::CPUSidePort::recvRespRetry(), Cache::recvTimingReq(), SimpleCache::CPUSidePort::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCtrl::recvTimingReq(), BaseTrafficGen::recvTimingResp(), CoherentXBar::recvTimingResp(), BaseCache::recvTimingResp(), NoncoherentCache::recvTimingSnoopReq(), Cache::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopReq(), NoncoherentCache::recvTimingSnoopResp(), Cache::recvTimingSnoopResp(), CoherentXBar::recvTimingSnoopResp(), BaseCache::satisfyRequest(), Cache::sendMSHRQueuePacket(), BaseCache::sendMSHRQueuePacket(), SimpleCache::CPUSidePort::sendPacket(), BaseCache::sendWriteQueuePacket(), Cache::serviceMSHRTargets(), SnoopFilter::updateResponse(), SnoopFilter::updateSnoopForward(), SnoopFilter::updateSnoopResponse(), BaseCache::writebackBlk(), and BaseCache::writecleanBlk().

◆ pushLabel()

void Packet::pushLabel ( const std::string & lbl )

inline

Push label for PrintReq (safe to call unconditionally).

Definition at line 1393 of file packet.hh.

References isPrint(), and senderState.

Referenced by BaseCache::functionalAccess(), QoS::MemSinkCtrl::MemoryPort::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkResponsePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), DRAMsim3::recvFunctional(), QoS::MemSinkCtrl::recvFunctional(), MemCtrl::MemoryPort::recvFunctional(), Queue< WriteQueueEntry >::trySatisfyFunctional(), and PacketQueue::trySatisfyFunctional().

◆ pushSenderState()

void Packet::pushSenderState ( Packet::SenderState * sender_state )

Push a new sender state to the packet and make the current sender state the predecessor of the new one.

This should be prefered over direct manipulation of the senderState member variable.

Parameters

sender_state SenderState to push at the top of the stack

Definition at line 332 of file packet.cc.

References Packet::SenderState::predecessor, and senderState.

Referenced by sc_gem5::TlmToGem5Bridge< BITWIDTH >::handleBeginReq(), ComputeUnit::injectGlobalMemFence(), Minor::Fetch1::FetchRequest::makePacket(), Minor::makePacketForRequest(), RubyPort::MemResponsePort::recvAtomic(), RubyPort::MemResponsePort::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), AddrMapper::recvTimingReq(), CommMonitor::recvTimingReq(), SMMUv3::runProcessTiming(), Gicv3Its::runProcessTiming(), X86ISA::IntRequestPort< X86ISA::I82094AA >::sendMessage(), BaseCache::sendMSHRQueuePacket(), RiscvISA::Walker::sendTiming(), X86ISA::Walker::sendTiming(), and AbstractController::serviceMemoryQueue().

◆ qosValue() [1/2]

uint8_t Packet::qosValue ( ) const

inline

QoS Value getter Returns 0 if QoS value was never set (constructor default).

Returns: QoS priority value of the packet

Definition at line 729 of file packet.hh.

References _qosValue.

Referenced by MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), QoS::MemSinkCtrl::processNextReqEvent(), QoS::MemCtrl::qosSchedule(), QoS::MemSinkCtrl::recvTimingReq(), and QoS::MemCtrl::schedule().

◆ qosValue() [2/2]

void Packet::qosValue ( const uint8_t qos_value )

inline

QoS Value setter Interface for setting QoS priority value of the packet.

Parameters

qos_value QoS priority value

Definition at line 737 of file packet.hh.

References _qosValue.

◆ requestorId()

RequestorID Packet::requestorId ( ) const

inline

Definition at line 740 of file packet.hh.

References req.

Referenced by MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), QoS::LrgQueuePolicy::enqueuePacket(), RubySystem::functionalRead(), RubySystem::functionalWrite(), RubyPort::MemResponsePort::hitCallback(), System::isDeviceMemAddr(), and QoS::MemCtrl::qosSchedule().

◆ responderHadWritable()

bool Packet::responderHadWritable ( ) const

inline

Definition at line 679 of file packet.hh.

References flags, Flags< T >::isSet(), and RESPONDER_HAD_WRITABLE.

Referenced by Cache::recvAtomic(), Cache::recvTimingReq(), setResponderHadWritable(), and CoherentXBar::sinkPacket().

◆ satisfied()

bool Packet::satisfied ( ) const

inline

Definition at line 715 of file packet.hh.

References flags, Flags< T >::isSet(), and SATISFIED.

Referenced by Cache::handleSnoop(), CoherentXBar::recvAtomicBackdoor(), and CoherentXBar::recvTimingReq().

◆ set()

template<typename T >

void Packet::set	(	T	v,
		ByteOrder	endian
	)

inline

Set the value in the data pointer to v using the specified endianness.

Definition at line 112 of file packet_access.hh.

References panic, and ArmISA::v.

◆ setAddr()

void Packet::setAddr ( Addr _addr )

inline

Update the address of this packet mid-transaction.

This is used by the address mapper to change an already set address to a new one based on the system configuration. It is intended to remap an existing address, so it asserts that the current address is valid.

Definition at line 762 of file packet.hh.

References addr, flags, Flags< T >::isSet(), and VALID_ADDR.

Referenced by SMMUTranslationProcess::completeTransaction(), VIPERCoalescer::makeWriteCompletePkts(), AddrMapper::recvAtomic(), AddrMapper::recvAtomicSnoop(), AddrMapper::recvFunctional(), AddrMapper::recvFunctionalSnoop(), AddrMapper::recvTimingReq(), and AddrMapper::recvTimingResp().

◆ setBadAddress()

void Packet::setBadAddress ( )

inline

Definition at line 746 of file packet.hh.

References MemCmd::BadAddressError, cmd, and isResponse().

Referenced by IsaFake::read(), HSAPacketProcessor::read(), and IsaFake::write().

◆ setBE()

template<typename T >

void Packet::setBE ( T v )

inline

Set the value in the data pointer to v as big endian.

Definition at line 98 of file packet_access.hh.

References htobe(), setRaw(), and ArmISA::v.

Referenced by SparcISA::TLB::doMmuRegRead(), DumbTOD::read(), Iob::readIob(), and Iob::readJBus().

◆ setBlockCached()

void Packet::setBlockCached ( )

inline

Definition at line 719 of file packet.hh.

References BLOCK_CACHED, flags, and Flags< T >::set().

Referenced by Cache::doWritebacks(), Cache::handleSnoop(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvTimingReq(), and Cache::recvTimingSnoopReq().

◆ setCacheResponding()

void Packet::setCacheResponding ( )

inline

Snoop flags.

Set the cacheResponding flag. This is used by the caches to signal another cache that they are responding to a request. A cache will only respond to snoops if it has the line in either Modified or Owned state. Note that on snoop hits we always pass the line as Modified and never Owned. In the case of an Owned line we proceed to invalidate all other copies.

On a cache fill (see Cache::handleFill), we check hasSharers first, ignoring the cacheResponding flag if hasSharers is set. A line is consequently allocated as:

hasSharers cacheResponding state true false Shared true true Shared false false Exclusive false true Modified

Definition at line 613 of file packet.hh.

References CACHE_RESPONDING, flags, isRequest(), Flags< T >::isSet(), and Flags< T >::set().

Referenced by Cache::handleSnoop(), MSHR::handleSnoop(), Cache::recvTimingReq(), Cache::recvTimingSnoopReq(), Cache::satisfyRequest(), and BaseCache::satisfyRequest().

◆ setData()

void Packet::setData ( const uint8_t * p )

inline

Copy data into the packet from the provided pointer.

Definition at line 1225 of file packet.hh.

References flags, getSize(), Flags< T >::isSet(), MipsISA::p, and STATIC_DATA.

Referenced by AbstractMemory::access(), BaseCache::cmpAndSwap(), AbstractMemory::functionalAccess(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), X86ISA::Interrupts::read(), VirtIODeviceBase::readConfigBlob(), BaseCache::satisfyRequest(), AbstractController::serviceMemoryQueue(), Cache::serviceMSHRTargets(), and setDataFromBlock().

◆ setDataFromBlock()

void Packet::setDataFromBlock	(	const uint8_t *	blk_data,
		int	blkSize
	)

inline

Copy data into the packet from the provided block pointer, which is aligned to the given block size.

Definition at line 1244 of file packet.hh.

References getOffset(), and setData().

Referenced by SimpleCache::accessFunctional(), Cache::doTimingSupplyResponse(), Cache::handleSnoop(), BaseCache::satisfyRequest(), BaseCache::writebackBlk(), and BaseCache::writecleanBlk().

◆ setExpressSnoop()

void Packet::setExpressSnoop ( )

inline

The express snoop flag is used for two purposes.

Firstly, it is used to bypass flow control for normal (non-snoop) requests going downstream in the memory system. In cases where a cache is responding to a snoop from another cache (it had a dirty line), but the line is not writable (and there are possibly other copies), the express snoop flag is set by the downstream cache to invalidate all other copies in zero time. Secondly, the express snoop flag is also set to be able to distinguish snoop packets that came from a downstream cache, rather than snoop packets from neighbouring caches.

Definition at line 661 of file packet.hh.

References EXPRESS_SNOOP, flags, and Flags< T >::set().

Referenced by Cache::handleSnoop(), Cache::isCachedAbove(), Cache::recvTimingReq(), CoherentXBar::recvTimingReq(), and Cache::sendMSHRQueuePacket().

◆ setFunctionalResponseStatus()

void Packet::setFunctionalResponseStatus ( bool success )

inline

Definition at line 1028 of file packet.hh.

References cmd, MemCmd::FunctionalReadError, MemCmd::FunctionalWriteError, and isWrite().

Referenced by RubyPort::MemResponsePort::recvFunctional().

◆ setHasSharers()

void Packet::setHasSharers ( )

inline

On fills, the hasSharers flag is used by the caches in combination with the cacheResponding flag, as clarified above.

If the hasSharers flag is not set, the packet is passing writable. Thus, a response from a memory passes the line as writable by default.

The hasSharers flag is also used by upstream caches to inform a downstream cache that they have the block (by calling setHasSharers on snoop request packets that hit in upstream cachs tags or MSHRs). If the snoop packet has sharers, a downstream cache is prevented from passing a dirty line upwards if it was not explicitly asked for a writable copy. See Cache::satisfyCpuSideRequest.

The hasSharers flag is also used on writebacks, in combination with the WritbackClean or WritebackDirty commands, to allocate the block downstream either as:

command hasSharers state WritebackDirty false Modified WritebackDirty true Owned WritebackClean false Exclusive WritebackClean true Shared

Definition at line 645 of file packet.hh.

References flags, HAS_SHARERS, and Flags< T >::set().

Referenced by Cache::createMissPacket(), Cache::handleSnoop(), MSHR::handleSnoop(), Cache::recvTimingSnoopReq(), Cache::satisfyRequest(), BaseCache::writebackBlk(), and BaseCache::writecleanBlk().

◆ setHtmTransactional()

void Packet::setHtmTransactional ( uint64_t val )

Stipulates that this packet/request originates in the CPU executing in transactional mode, i.e.

within a transaction.

Definition at line 537 of file packet.cc.

References flags, FROM_TRANSACTION, htmTransactionUid, and Flags< T >::set().

Referenced by TimingSimpleCPU::completeDataAccess(), FullO3CPU< O3CPUImpl >::htmSendAbortSignal(), Packet(), LSQUnit< Impl >::read(), TimingSimpleCPU::sendData(), and TimingSimpleCPU::sendSplitData().

◆ setHtmTransactionFailedInCache()

void Packet::setHtmTransactionFailedInCache ( const HtmCacheFailure ret_code )

Stipulates that this packet/request has returned from the cache hierarchy in a failed transaction.

The core is notified like this.

Definition at line 514 of file packet.cc.

References FAILS_TRANSACTION, flags, htmReturnReason, NO_FAIL, and Flags< T >::set().

Referenced by TimingSimpleCPU::completeDataAccess(), makeHtmTransactionalReqResponse(), and Packet().

◆ setLE()

template<typename T >

void Packet::setLE ( T v )

inline

Set the value in the data pointer to v as little endian.

Definition at line 105 of file packet_access.hh.

References htole(), setRaw(), and ArmISA::v.

Referenced by CopyEngine::CopyEngineChannel::channelRead(), X86ISA::TLB::finalizePhysical(), ArmISA::TLB::finalizePhysical(), PciVirtIO::read(), MmioVirtIO::read(), NoMaliGpu::read(), Pl011::read(), AmbaFake::read(), X86ISA::Speaker::read(), A9SCU::read(), IsaFake::read(), X86ISA::Cmos::read(), X86ISA::I8254::read(), X86ISA::I82094AA::read(), HDLcd::read(), X86ISA::I8259::read(), Gicv2m::read(), PL031::read(), Sp804::Timer::read(), EnergyCtrl::read(), A9GlobalTimer::Timer::read(), CpuLocalTimer::Timer::read(), X86ISA::I8042::read(), CopyEngine::read(), RealViewCtrl::read(), Sinic::Device::read(), NSGigE::read(), IGbE::read(), UFSHostDevice::read(), IdeController::readConfig(), PciDevice::readConfig(), SMMUv3::readControl(), GicV2::readCpu(), VGic::readCtrl(), GicV2::readDistributor(), VGic::readVCpu(), RiscvISA::Walker::WalkerState::stepWalk(), and X86ISA::Walker::WalkerState::stepWalk().

◆ setRaw()

template<typename T >

void Packet::setRaw ( T v )

inline

Set the value in the data pointer to v without byte swapping.

Definition at line 58 of file packet_access.hh.

References data, DYNAMIC_DATA, flags, Flags< T >::isSet(), size, STATIC_DATA, and ArmISA::v.

Referenced by X86ISA::buildIntPacket(), MmDisk::read(), Uart8250::read(), I2CBus::read(), setBE(), and setLE().

◆ setResponderHadWritable()

void Packet::setResponderHadWritable ( )

inline

On responding to a snoop request (which only happens for Modified or Owned lines), make sure that we can transform an Owned response to a Modified one.

If this flag is not set, the responding cache had the line in the Owned state, and there are possibly other Shared copies in the memory system. A downstream cache helps in orchestrating the invalidation of these copies by sending out the appropriate express snoops.

Definition at line 673 of file packet.hh.

References cacheResponding(), flags, RESPONDER_HAD_WRITABLE, responderHadWritable(), and Flags< T >::set().

Referenced by Cache::handleSnoop(), MSHR::handleSnoop(), and Cache::recvTimingSnoopReq().

◆ setSatisfied()

void Packet::setSatisfied ( )

inline

Set when a request hits in a cache and the cache is not going to respond.

This is used by the crossbar to coordinate responses for cache maintenance operations.

Definition at line 709 of file packet.hh.

References cmd, flags, MemCmd::isClean(), Flags< T >::isSet(), SATISFIED, and Flags< T >::set().

Referenced by Cache::handleSnoop(), MSHR::handleSnoop(), BaseCache::recvAtomic(), and BaseCache::sendMSHRQueuePacket().

◆ setSize()

void Packet::setSize ( unsigned size )

inline

Definition at line 1040 of file packet.hh.

References flags, Flags< T >::isSet(), Flags< T >::set(), size, and VALID_SIZE.

◆ setSuppressFuncError()

void Packet::setSuppressFuncError ( )

inline

Definition at line 717 of file packet.hh.

References flags, Flags< T >::set(), and SUPPRESS_FUNC_ERROR.

Referenced by Shader::doFunctionalAccess(), and MemTest::tick().

◆ setUintX()

void Packet::setUintX	(	uint64_t	w,
		ByteOrder	endian
	)

Set the value in the word w after truncating it to the length of the packet and then byteswapping it to the desired endianness.

Definition at line 367 of file packet.cc.

References getSize(), panic, and MipsISA::w.

Referenced by SimpleUart::read(), Sp805::read(), FVPBasePwrCtrl::read(), Gicv3::read(), Pl050::read(), Gicv3Its::read(), Pl111::read(), GenericTimerFrame::read(), GenericTimerMem::read(), and AmbaDevice::readId().

◆ setWriteThrough()

void Packet::setWriteThrough ( )

inline

A writeback/writeclean cmd gets propagated further downstream by the receiver when the flag is set.

Definition at line 695 of file packet.hh.

References cmd, flags, MemCmd::isEviction(), MemCmd::isWrite(), Flags< T >::set(), WRITE_THROUGH, and MemCmd::WriteClean.

Referenced by BaseCache::writecleanBlk().

◆ suppressFuncError()

bool Packet::suppressFuncError ( ) const

inline

Definition at line 718 of file packet.hh.

References flags, Flags< T >::isSet(), and SUPPRESS_FUNC_ERROR.

Referenced by RubyPort::MemResponsePort::recvFunctional().

◆ trySatisfyFunctional() [1/2]

bool Packet::trySatisfyFunctional ( PacketPtr other )

inline

Check a functional request against a memory value stored in another packet (i.e.

an in-transit request or response). Returns true if the current packet is a read, and the other packet provides the data, which is then copied to the current packet. If the current packet is a write, and the other packet intersects this one, then we update the data accordingly.

Definition at line 1331 of file packet.hh.

References _isSecure, getAddr(), getPtr(), getSize(), hasData(), isMaskedWrite(), isSecure(), and warn.

Referenced by BaseCache::functionalAccess(), SequencerRequest::functionalWrite(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkResponsePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), DRAMsim3::recvFunctional(), WriteQueueEntry::TargetList::trySatisfyFunctional(), WriteQueueEntry::trySatisfyFunctional(), PacketQueue::trySatisfyFunctional(), MSHR::TargetList::trySatisfyFunctional(), SerialLink::SerialLinkRequestPort::trySatisfyFunctional(), Bridge::BridgeRequestPort::trySatisfyFunctional(), and MSHR::trySatisfyFunctional().

◆ trySatisfyFunctional() [2/2]

bool Packet::trySatisfyFunctional	(	Printable *	obj,
		Addr	base,
		bool	is_secure,
		int	size,
		uint8_t *	_data
	)

Check a functional request against a memory value represented by a base/size pair and an associated data array.

If the current packet is a read, it may be satisfied by the memory value. If the current packet is a write, it may update the memory value.

Definition at line 247 of file packet.cc.

References _isSecure, addr, bytesValid, cmdString(), getAddr(), getSize(), ArmISA::i, isPrint(), isRead(), isWrite(), panic, senderState, and size.

◆ writeData()

void Packet::writeData ( uint8_t * p ) const

inline

Copy data from the packet to the memory at the provided pointer.

Parameters

p	Pointer to which data will be copied.

Definition at line 1254 of file packet.hh.

References X86ISA::base, getSize(), ArmISA::i, isMaskedWrite(), MipsISA::p, and req.

Referenced by AbstractMemory::access(), BaseCache::cmpAndSwap(), AbstractMemory::functionalAccess(), Sequencer::hitCallback(), MemCheckerMonitor::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), X86ISA::Interrupts::write(), VirtIODeviceBase::writeConfigBlob(), and writeDataToBlock().

◆ writeDataToBlock()

void Packet::writeDataToBlock	(	uint8_t *	blk_data,
		int	blkSize
	)		const

inline

Copy data from the packet to the provided block pointer, which is aligned to the given block size.

Parameters

blk_data	Pointer to block to which data will be copied.
blkSize	Block size in bytes.

Definition at line 1278 of file packet.hh.

References getOffset(), and writeData().

Referenced by BaseCache::access(), SimpleCache::accessFunctional(), BaseCache::handleFill(), SimpleCache::insert(), and BaseCache::satisfyRequest().

◆ writeThrough()

bool Packet::writeThrough ( ) const

inline

Definition at line 702 of file packet.hh.

References flags, Flags< T >::isSet(), and WRITE_THROUGH.

Referenced by BaseCache::access().

Member Data Documentation

◆ _isSecure

bool Packet::_isSecure

private

True if the request targets the secure memory space.

Definition at line 357 of file packet.hh.

Referenced by isSecure(), Packet(), and trySatisfyFunctional().

◆ _qosValue

uint8_t Packet::_qosValue

private

Definition at line 368 of file packet.hh.

Referenced by qosValue().

◆ addr

Addr Packet::addr

private

The address of the request.

This address could be virtual or physical, depending on the system configuration.

Definition at line 354 of file packet.hh.

Referenced by getAddr(), matchAddr(), matchBlockAddr(), Packet(), setAddr(), and trySatisfyFunctional().

◆ bytesValid

std::vector<bool> Packet::bytesValid

private

Track the bytes found that satisfy a functional read.

Definition at line 365 of file packet.hh.

Referenced by trySatisfyFunctional().

◆ cmd

MemCmd Packet::cmd

The command field of the packet.

Definition at line 335 of file packet.hh.

Referenced by NoncoherentCache::access(), AbstractMemory::access(), BaseCache::access(), WriteQueueEntry::allocate(), MSHR::allocate(), BaseCache::allocateMissBuffer(), MSHR::allocateTarget(), BaseCache::allocateWriteBuffer(), TimingSimpleCPU::buildSplitPacket(), cmdString(), cmdToIndex(), GPUCoalescer::coalescePacket(), convertLlToRead(), convertScToWrite(), copyError(), Cache::createMissPacket(), Cache::doTimingSupplyResponse(), Cache::doWritebacks(), Cache::doWritebacksAtomic(), MSHR::extractServiceableTargets(), FetchUnit::fetch(), CoherentXBar::forwardAtomic(), fromCache(), NoncoherentCache::handleAtomicReqMiss(), Cache::handleAtomicReqMiss(), BaseCache::handleFill(), MSHR::handleSnoop(), Cache::handleTimingReqMiss(), BaseCache::handleTimingReqMiss(), hasData(), hasRespData(), RubyPort::MemResponsePort::hitCallback(), Cache::isCachedAbove(), isClean(), isCleanEviction(), isError(), isEviction(), isFlush(), isInvalidate(), isLLSC(), isMaskedWrite(), isPrint(), isRead(), isRequest(), isResponse(), VIPERCoalescer::issueRequest(), isUpgrade(), isWholeLineWrite(), isWrite(), isWriteback(), makeHtmTransactionalReqResponse(), VIPERCoalescer::makeRequest(), GPUCoalescer::makeRequest(), makeResponse(), mustCheckAbove(), needsResponse(), needsWritable(), Prefetcher::BOP::notifyFill(), Prefetcher::Base::observeAccess(), Prefetcher::Base::probeNotify(), ComputeUnit::DataPort::processMemRespEvent(), Cache::promoteWholeLineWrites(), X86ISA::IntResponsePort< X86ISA::Interrupts >::recvAtomic(), RubyPort::MemResponsePort::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), X86ISA::Interrupts::recvMessage(), RubyPort::MemResponsePort::recvTimingReq(), CoherentXBar::recvTimingReq(), NoncoherentCache::recvTimingResp(), BaseCache::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), Minor::LSQ::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), ComputeUnit::ScalarDTLBPort::recvTimingResp(), ComputeUnit::ITLBPort::recvTimingResp(), Cache::recvTimingSnoopReq(), Cache::recvTimingSnoopResp(), replaceUpgrade(), Cache::satisfyRequest(), BaseCache::satisfyRequest(), Cache::sendMSHRQueuePacket(), ComputeUnit::sendRequest(), NoncoherentCache::serviceMSHRTargets(), Cache::serviceMSHRTargets(), setBadAddress(), setFunctionalResponseStatus(), setSatisfied(), setWriteThrough(), RiscvISA::Walker::WalkerState::stepWalk(), X86ISA::Walker::WalkerState::stepWalk(), and MSHR::TargetList::updateFlags().

◆ data

PacketDataPtr Packet::data

private

A pointer to the data being transferred.

It can be different sizes at each level of the hierarchy so it belongs to the packet, not request. This may or may not be populated when a responder receives the packet. If not populated memory should be allocated.

Definition at line 350 of file packet.hh.

Referenced by allocate(), dataDynamic(), dataStatic(), dataStaticConst(), deleteData(), getConstPtr(), getPtr(), getRaw(), Packet(), and setRaw().

◆ flags

Flags Packet::flags

private

◆ headerDelay

uint32_t Packet::headerDelay

The extra delay from seeing the packet until the header is transmitted.

This delay is used to communicate the crossbar forwarding latency to the neighbouring object (e.g. a cache) that actually makes the packet wait. As the delay is relative, a 32-bit unsigned should be sufficient.

Definition at line 394 of file packet.hh.

Referenced by BaseCache::access(), DRAMSim2::accessAndRespond(), DRAMsim3::accessAndRespond(), MemCtrl::accessAndRespond(), SMMUv3DeviceInterface::atsRecvTimingReq(), SMMUv3DeviceInterface::atsRecvTimingResp(), BaseXBar::calcPacketTiming(), Cache::doTimingSupplyResponse(), BaseCache::handleFill(), Cache::handleSnoop(), BaseCache::handleTimingReqHit(), BaseCache::handleUncacheableWriteResp(), StubSlavePort::processResponseEvent(), GenericPciHost::read(), PioPort< X86ISA::Interrupts >::recvAtomic(), X86ISA::IntResponsePort< X86ISA::Interrupts >::recvAtomic(), SMMUControlPort::recvAtomic(), RiscvISA::Walker::WalkerState::recvPacket(), X86ISA::Walker::WalkerState::recvPacket(), HMCController::recvTimingReq(), Cache::recvTimingReq(), SMMUv3DeviceInterface::recvTimingReq(), MemDelay::ResponsePort::recvTimingReq(), NoncoherentXBar::recvTimingReq(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SimpleMemory::recvTimingReq(), Bridge::BridgeResponsePort::recvTimingReq(), CoherentXBar::recvTimingReq(), BaseCache::recvTimingReq(), MemDelay::RequestPort::recvTimingResp(), Gicv3Its::recvTimingResp(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::recvTimingResp(), NoncoherentXBar::recvTimingResp(), SMMUv3::recvTimingResp(), SerialLink::SerialLinkRequestPort::recvTimingResp(), CoherentXBar::recvTimingResp(), Bridge::BridgeRequestPort::recvTimingResp(), BaseCache::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), Cache::recvTimingSnoopResp(), CoherentXBar::recvTimingSnoopResp(), SMMUv3::runProcessTiming(), NoncoherentCache::serviceMSHRTargets(), Cache::serviceMSHRTargets(), SMMUv3::tableWalkRecvTimingResp(), and GenericPciHost::write().

◆ htmReturnReason

HtmCacheFailure Packet::htmReturnReason

private

Holds the return status of the transaction.

The default case will be NO_FAIL, otherwise this will specify the reason for the transaction's failure in the memory subsystem.

Definition at line 377 of file packet.hh.

Referenced by getHtmTransactionFailedInCacheRC(), and setHtmTransactionFailedInCache().

◆ htmTransactionUid

uint64_t Packet::htmTransactionUid

private

A global unique identifier of the transaction.

This is used for correctness/debugging only.

Definition at line 383 of file packet.hh.

Referenced by getHtmTransactionUid(), and setHtmTransactional().

◆ id

const PacketId Packet::id

Definition at line 337 of file packet.hh.

Referenced by Cache::handleSnoop(), MSHR::handleSnoop(), BaseCache::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvTimingReq(), and BaseCache::sendMSHRQueuePacket().

◆ payloadDelay

uint32_t Packet::payloadDelay

The extra pipelining delay from seeing the packet until the end of payload is transmitted by the component that provided it (if any).

This includes the header delay. Similar to the header delay, this is used to make up for the fact that the crossbar does not make the packet wait. As the delay is relative, a 32-bit unsigned should be sufficient.

Definition at line 412 of file packet.hh.

◆ req

RequestPtr Packet::req

A pointer to the original request.

Definition at line 340 of file packet.hh.

◆ senderState

SenderState* Packet::senderState

This packet's sender state.

Devices should use dynamic_cast<> to cast to the state appropriate to the sender. The intent of this variable is to allow a device to attach extra information to a request. A response packet must return the sender state that was attached to the original request (even if a new packet is created).

Definition at line 508 of file packet.hh.

Referenced by PendingWriteInst::ackWriteCompletion(), LSQ< Impl >::SplitDataRequest::buildPackets(), TimingSimpleCPU::buildSplitPacket(), TLBCoalescer::canCoalesce(), TimingSimpleCPU::SplitFragmentSenderState::clearFromParent(), GPUCoalescer::coalescePacket(), LSQUnit< Impl >::completeDataAccess(), TimingSimpleCPU::completeDataAccess(), LSQ< Impl >::completeDataAccess(), LdsState::countBankConflicts(), DmaPort::dmaAction(), FetchUnit::fetch(), findNextSenderState(), AbstractMemory::functionalAccess(), Shader::functionalTLBAccess(), GarnetSyntheticTraffic::generatePkt(), LdsState::getDynInstr(), X86ISA::GpuTLB::handleFuncTranslationReturn(), DmaPort::handleResp(), X86ISA::GpuTLB::handleTranslationReturn(), Check::initiateAction(), Check::initiateCheck(), FetchUnit::initiateFetch(), Check::initiateFlush(), Check::initiatePrefetch(), Cache::isCachedAbove(), X86ISA::GpuTLB::issueTLBLookup(), VIPERCoalescer::makeWriteCompletePkts(), popLabel(), popSenderState(), RequestPort::printAddr(), LdsState::process(), FetchStage::processFetchReturn(), FetchUnit::processFetchReturn(), ComputeUnit::DataPort::processMemReqEvent(), ComputeUnit::DataPort::processMemRespEvent(), TLBCoalescer::processProbeTLBEvent(), pushLabel(), pushSenderState(), TLBCoalescer::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), TimingSimpleCPU::DcachePort::recvReqRetry(), TLBCoalescer::CpuSidePort::recvTimingReq(), RubyTester::CpuPort::recvTimingResp(), AbstractController::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), CommMonitor::recvTimingResp(), LSQUnit< Impl >::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::ScalarDataPort::recvTimingResp(), LSQ< Impl >::SingleDataRequest::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), LSQ< Impl >::SplitDataRequest::recvTimingResp(), ComputeUnit::ScalarDTLBPort::recvTimingResp(), ComputeUnit::ITLBPort::recvTimingResp(), ComputeUnit::LDSPort::recvTimingResp(), LSQ< Impl >::recvTimingResp(), Cache::sendMSHRQueuePacket(), ComputeUnit::sendRequest(), ComputeUnit::sendScalarRequest(), TimingSimpleCPU::sendSplitData(), ComputeUnit::LDSPort::sendTimingReq(), ComputeUnit::sendToLds(), X86ISA::GpuTLB::translationReturn(), trySatisfyFunctional(), LSQUnit< Impl >::trySendPacket(), and TLBCoalescer::updatePhysAddresses().

◆ size

unsigned Packet::size

private

The size of the request or transfer.

Definition at line 360 of file packet.hh.

Referenced by getRaw(), getSize(), Packet(), setRaw(), setSize(), and trySatisfyFunctional().

◆ snoopDelay

uint32_t Packet::snoopDelay

Keep track of the extra delay incurred by snooping upwards before sending a request down the memory system.

This is used by the coherent crossbar to account for the additional request delay.

Definition at line 402 of file packet.hh.

Referenced by CoherentXBar::recvTimingReq(), Cache::recvTimingSnoopReq(), and CoherentXBar::recvTimingSnoopReq().

The documentation for this class was generated from the following files:

Classes

Public Types

Public Member Functions

Static Public Member Functions

Public Attributes

Private Types

Private Attributes

Detailed Description

Member Typedef Documentation

◆ Command

◆ Flags

◆ FlagsType

Member Enumeration Documentation

◆ anonymous enum

Constructor & Destructor Documentation

◆ Packet() [1/3]

◆ Packet() [2/3]

◆ Packet() [3/3]

◆ ~Packet()

Member Function Documentation

◆ allocate()

◆ cacheResponding()

◆ clearBlockCached()

◆ clearWriteThrough()

◆ cmdString()

◆ cmdToIndex()

◆ convertLlToRead()

◆ convertScToWrite()

◆ copyError()

◆ copyResponderFlags()

◆ createRead()

◆ createWrite()

◆ dataDynamic()

◆ dataStatic()

◆ dataStaticConst()

◆ deleteData()

◆ findNextSenderState()

◆ fromCache()

◆ get()

◆ getAddr()

◆ getAddrRange()

◆ getAtomicOp()

◆ getBE()

◆ getBlockAddr()

◆ getConstPtr()

◆ getHtmTransactionFailedInCacheRC()

◆ getHtmTransactionUid()

◆ getLE()

◆ getOffset()

◆ getPtr()

◆ getRaw()

◆ getSize()

◆ getUintX()

◆ hasData()

◆ hasRespData()

◆ hasSharers()

◆ htmTransactionFailedInCache()

◆ isAtomicOp()

◆ isBlockCached()

◆ isClean()

◆ isCleanEviction()

◆ isError()

◆ isEviction()

◆ isExpressSnoop()

◆ isFlush()

◆ isHtmTransactional()

◆ isInvalidate()

◆ isLLSC()

◆ isMaskedWrite()

◆ isPrint()

◆ isRead()

◆ isRequest()

◆ isResponse()

◆ isSecure()

◆ isUpgrade()

◆ isWholeLineWrite()

◆ isWrite()

◆ isWriteback()

◆ makeAtomicResponse()

◆ makeHtmTransactionalReqResponse()