gem5  v20.1.0.0
InvalidateGenerator.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3  * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
31 
32 #include "base/trace.hh"
35 #include "debug/DirectedTest.hh"
36 
39 {
40  //
41  // First, issue loads to bring the block into S state
42  //
43  m_status = InvalidateGeneratorStatus_Load_Waiting;
46  m_address = 0x0;
47  m_addr_increment_size = p->addr_increment_size;
48 }
49 
51 {
52 }
53 
54 bool
56 {
57  RequestPort* port;
58  Request::Flags flags;
59  PacketPtr pkt;
60  Packet::Command cmd;
61 
62  // For simplicity, requests are assumed to be 1 byte-sized
63  RequestPtr req = std::make_shared<Request>(m_address, 1, flags,
64  requestorId);
65 
66  //
67  // Based on the current state, issue a load or a store
68  //
69  if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
70  DPRINTF(DirectedTest, "initiating read\n");
71  cmd = MemCmd::ReadReq;
73  pkt = new Packet(req, cmd);
74  } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
75  DPRINTF(DirectedTest, "initiating invalidating write\n");
76  cmd = MemCmd::WriteReq;
78  pkt = new Packet(req, cmd);
79  } else {
80  panic("initiate was unexpectedly called\n");
81  }
82  pkt->allocate();
83 
84  if (port->sendTimingReq(pkt)) {
85  DPRINTF(DirectedTest, "initiating request - successful\n");
86  if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
87  m_status = InvalidateGeneratorStatus_Load_Pending;
88  } else {
89  m_status = InvalidateGeneratorStatus_Inv_Pending;
90  }
91  return true;
92  } else {
93  // If the packet did not issue, must delete
94  // Note: No need to delete the data, the packet destructor
95  // will delete it
96  delete pkt;
97 
98  DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
99  return false;
100  }
101 }
102 
103 void
105 {
106  assert(m_address == address);
107 
108  if (m_status == InvalidateGeneratorStatus_Load_Pending) {
109  assert(m_active_read_node == proc);
111  //
112  // Once all cpus have the block in S state, issue the invalidate
113  //
115  m_status = InvalidateGeneratorStatus_Inv_Waiting;
116  m_active_read_node = 0;
117  } else {
118  m_status = InvalidateGeneratorStatus_Load_Waiting;
119  }
120  } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
121  assert(m_active_inv_node == proc);
123  if (m_active_inv_node == m_num_cpus) {
125  m_active_inv_node = 0;
126  }
127  //
128  // Invalidate completed, send that info to the tester and restart
129  // the cycle
130  //
132  m_status = InvalidateGeneratorStatus_Load_Waiting;
133  }
134 
135 }
136 
138 InvalidateGeneratorParams::create()
139 {
140  return new InvalidateGenerator(this);
141 }
InvalidateGenerator::~InvalidateGenerator
~InvalidateGenerator()
Definition: InvalidateGenerator.cc:50
InvalidateGenerator::m_status
InvalidateGeneratorStatus m_status
Definition: InvalidateGenerator.hh:55
Flags< FlagsType >
InvalidateGenerator::InvalidateGenerator
InvalidateGenerator(const Params *p)
Definition: InvalidateGenerator.cc:37
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:82
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
DirectedGenerator
Definition: DirectedGenerator.hh:37
MemCmd::Command
Command
List of all commands associated with a packet.
Definition: packet.hh:79
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
RubyDirectedTester.hh
RequestPort::sendTimingReq
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
Definition: port.hh:492
InvalidateGenerator::m_active_read_node
uint32_t m_active_read_node
Definition: InvalidateGenerator.hh:57
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
InvalidateGenerator::m_address
Addr m_address
Definition: InvalidateGenerator.hh:56
InvalidateGenerator::initiate
bool initiate()
Definition: InvalidateGenerator.cc:55
InvalidateGenerator
Definition: InvalidateGenerator.hh:43
InvalidateGenerator::m_addr_increment_size
uint32_t m_addr_increment_size
Definition: InvalidateGenerator.hh:59
RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:74
DirectedGenerator::Params
DirectedGeneratorParams Params
Definition: DirectedGenerator.hh:40
ProbePoints::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:103
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RubyDirectedTester::getCpuPort
RequestPort * getCpuPort(int idx)
Definition: RubyDirectedTester.cc:109
DirectedGenerator::m_directed_tester
RubyDirectedTester * m_directed_tester
Definition: DirectedGenerator.hh:53
DirectedGenerator::requestorId
RequestorID requestorId
Definition: DirectedGenerator.hh:52
DirectedGenerator::m_num_cpus
int m_num_cpus
Definition: DirectedGenerator.hh:51
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
DirectedGenerator.hh
InvalidateGenerator::m_active_inv_node
uint32_t m_active_inv_node
Definition: InvalidateGenerator.hh:58
trace.hh
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1299
InvalidateGenerator::performCallback
void performCallback(uint32_t proc, Addr address)
Definition: InvalidateGenerator.cc:104
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
InvalidateGenerator.hh
RubyDirectedTester::incrementCycleCompletions
void incrementCycleCompletions()
Definition: RubyDirectedTester.hh:80

Generated on Wed Sep 30 2020 14:02:09 for gem5 by doxygen 1.8.17