gem5  v20.1.0.0
RubyDirectedTester.cc
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41 
43 
44 #include "base/trace.hh"
46 #include "debug/DirectedTest.hh"
47 #include "sim/sim_exit.hh"
48 
50  : ClockedObject(p),
51  directedStartEvent([this]{ wakeup(); }, "Directed tick",
52  false, Event::CPU_Tick_Pri),
53  m_requests_to_complete(p->requests_to_complete),
54  generator(p->generator)
55 {
56  m_requests_completed = 0;
57 
58  // create the ports
59  for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
60  ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
61  this, i));
62  }
63 
64  // add the check start event to the event queue
65  schedule(directedStartEvent, 1);
66 }
67 
69 {
70  for (int i = 0; i < ports.size(); i++)
71  delete ports[i];
72 }
73 
74 void
76 {
77  assert(ports.size() > 0);
79 }
80 
81 Port &
82 RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
83 {
84  if (if_name != "cpuPort") {
85  // pass it along to our super class
86  return ClockedObject::getPort(if_name, idx);
87  } else {
88  if (idx >= static_cast<int>(ports.size())) {
89  panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
90  }
91 
92  return *ports[idx];
93  }
94 }
95 
96 bool
98 {
99  tester->hitCallback(id, pkt->getAddr());
100 
101  //
102  // Now that the tester has completed, delete the packet, then return
103  //
104  delete pkt;
105  return true;
106 }
107 
110 {
111  assert(idx >= 0 && idx < ports.size());
112 
113  return ports[idx];
114 }
115 
116 void
118 {
119  DPRINTF(DirectedTest,
120  "completed request for proc: %d addr: 0x%x\n",
121  proc,
122  addr);
123 
126 }
127 
128 void
130 {
132  if (!generator->initiate()) {
134  }
135  } else {
136  exitSimLoop("Ruby DirectedTester completed");
137  }
138 }
139 
141 RubyDirectedTesterParams::create()
142 {
143  return new RubyDirectedTester(this);
144 }
RubyDirectedTester::~RubyDirectedTester
~RubyDirectedTester()
Definition: RubyDirectedTester.cc:68
DirectedGenerator::setDirectedTester
void setDirectedTester(RubyDirectedTester *directed_tester)
Definition: DirectedGenerator.cc:43
RubyDirectedTester::m_requests_to_complete
uint64_t m_requests_to_complete
Definition: RubyDirectedTester.hh:102
RubyDirectedTester::generator
DirectedGenerator * generator
Definition: RubyDirectedTester.hh:103
EventBase::CPU_Tick_Pri
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
Definition: eventq.hh:199
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
RubyDirectedTester::m_requests_completed
uint64_t m_requests_completed
Definition: RubyDirectedTester.hh:100
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
RubyDirectedTester::ports
std::vector< RequestPort * > ports
Definition: RubyDirectedTester.hh:101
DirectedGenerator::performCallback
virtual void performCallback(uint32_t proc, Addr address)=0
sim_exit.hh
RubyDirectedTester::RubyDirectedTester
RubyDirectedTester(const Params *p)
Definition: RubyDirectedTester.cc:49
ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:231
RubyDirectedTester::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: RubyDirectedTester.cc:75
EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1005
RubyDirectedTester.hh
RubyDirectedTester::Params
RubyDirectedTesterParams Params
Definition: RubyDirectedTester.hh:67
RubyDirectedTester::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: RubyDirectedTester.cc:82
SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
RubyDirectedTester::directedStartEvent
EventFunctionWrapper directedStartEvent
Definition: RubyDirectedTester.hh:89
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
DirectedGenerator::initiate
virtual bool initiate()=0
RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:74
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
name
const std::string & name()
Definition: trace.cc:50
RubyDirectedTester::getCpuPort
RequestPort * getCpuPort(int idx)
Definition: RubyDirectedTester.cc:109
RubyDirectedTester::wakeup
void wakeup()
Definition: RubyDirectedTester.cc:129
RubyDirectedTester
Definition: RubyDirectedTester.hh:47
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
RubyDirectedTester::hitCallback
void hitCallback(NodeID proc, Addr addr)
Definition: RubyDirectedTester.cc:117
addr
ip6_addr_t addr
Definition: inet.hh:423
DirectedGenerator.hh
NodeID
unsigned int NodeID
Definition: TypeDefines.hh:34
trace.hh
RubyDirectedTester::CpuPort::tester
RubyDirectedTester * tester
Definition: RubyDirectedTester.hh:53
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
RubyDirectedTester::CpuPort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: RubyDirectedTester.cc:97
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
curTick
Tick curTick()
The current simulated tick.
Definition: core.hh:45

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