gem5  v20.1.0.0
OutputUnit.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Inria
3  * Copyright (c) 2016 Georgia Institute of Technology
4  * Copyright (c) 2008 Princeton University
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are
9  * met: redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer;
11  * redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution;
14  * neither the name of the copyright holders nor the names of its
15  * contributors may be used to endorse or promote products derived from
16  * this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 
33 
34 #include "debug/RubyNetwork.hh"
39 
40 OutputUnit::OutputUnit(int id, PortDirection direction, Router *router,
41  uint32_t consumerVcs)
42  : Consumer(router), m_router(router), m_id(id), m_direction(direction),
43  m_vc_per_vnet(consumerVcs)
44 {
45  const int m_num_vcs = consumerVcs * m_router->get_num_vnets();
46  outVcState.reserve(m_num_vcs);
47  for (int i = 0; i < m_num_vcs; i++) {
48  outVcState.emplace_back(i, m_router->get_net_ptr(), consumerVcs);
49  }
50 }
51 
52 void
54 {
55  DPRINTF(RubyNetwork, "Router %d OutputUnit %s decrementing credit:%d for "
56  "outvc %d at time: %lld for %s\n", m_router->get_id(),
58  outVcState[out_vc].get_credit_count(),
59  out_vc, m_router->curCycle(), m_credit_link->name());
60 
61  outVcState[out_vc].decrement_credit();
62 }
63 
64 void
66 {
67  DPRINTF(RubyNetwork, "Router %d OutputUnit %s incrementing credit:%d for "
68  "outvc %d at time: %lld from:%s\n", m_router->get_id(),
70  outVcState[out_vc].get_credit_count(),
71  out_vc, m_router->curCycle(), m_credit_link->name());
72 
73  outVcState[out_vc].increment_credit();
74 }
75 
76 // Check if the output VC (i.e., input VC at next router)
77 // has free credits (i..e, buffer slots).
78 // This is tracked by OutVcState
79 bool
81 {
82  assert(outVcState[out_vc].isInState(ACTIVE_, curTick()));
83  return outVcState[out_vc].has_credit();
84 }
85 
86 
87 // Check if the output port (i.e., input port at next router) has free VCs.
88 bool
90 {
91  int vc_base = vnet*m_vc_per_vnet;
92  for (int vc = vc_base; vc < vc_base + m_vc_per_vnet; vc++) {
93  if (is_vc_idle(vc, curTick()))
94  return true;
95  }
96 
97  return false;
98 }
99 
100 // Assign a free output VC to the winner of Switch Allocation
101 int
103 {
104  int vc_base = vnet*m_vc_per_vnet;
105  for (int vc = vc_base; vc < vc_base + m_vc_per_vnet; vc++) {
106  if (is_vc_idle(vc, curTick())) {
107  outVcState[vc].setState(ACTIVE_, curTick());
108  return vc;
109  }
110  }
111 
112  return -1;
113 }
114 
115 /*
116  * The wakeup function of the OutputUnit reads the credit signal from the
117  * downstream router for the output VC (i.e., input VC at downstream router).
118  * It increments the credit count in the appropriate output VC state.
119  * If the credit carries is_free_signal as true,
120  * the output VC is marked IDLE.
121  */
122 
123 void
125 {
126  if (m_credit_link->isReady(curTick())) {
127  Credit *t_credit = (Credit*) m_credit_link->consumeLink();
128  increment_credit(t_credit->get_vc());
129 
130  if (t_credit->is_free_signal())
131  set_vc_state(IDLE_, t_credit->get_vc(), curTick());
132 
133  delete t_credit;
134 
135  if (m_credit_link->isReady(curTick())) {
136  scheduleEvent(Cycles(1));
137  }
138  }
139 }
140 
141 flitBuffer*
143 {
144  return &outBuffer;
145 }
146 
147 void
149 {
150  m_out_link = link;
151 }
152 
153 void
155 {
156  m_credit_link = credit_link;
157 }
158 
159 void
161 {
162  outBuffer.insert(t_flit);
164 }
165 
166 uint32_t
168 {
169  return outBuffer.functionalWrite(pkt);
170 }
OutputUnit::m_credit_link
CreditLink * m_credit_link
Definition: OutputUnit.hh:106
OutputUnit::has_free_vc
bool has_free_vc(int vnet)
Definition: OutputUnit.cc:89
flitBuffer
Definition: flitBuffer.hh:41
Router::get_id
int get_id()
Definition: Router.hh:81
OutputUnit::getOutQueue
flitBuffer * getOutQueue()
Definition: OutputUnit.cc:142
flit
Definition: flit.hh:41
OutputUnit::m_out_link
NetworkLink * m_out_link
Definition: OutputUnit.hh:105
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
OutputUnit::functionalWrite
uint32_t functionalWrite(Packet *pkt)
Definition: OutputUnit.cc:167
Router::get_num_vnets
uint32_t get_num_vnets()
Definition: Router.hh:77
OutputUnit::has_credit
bool has_credit(int out_vc)
Definition: OutputUnit.cc:80
OutputUnit::increment_credit
void increment_credit(int out_vc)
Definition: OutputUnit.cc:65
OutputUnit::outVcState
std::vector< OutVcState > outVcState
Definition: OutputUnit.hh:111
OutputUnit::m_router
Router * m_router
Definition: OutputUnit.hh:101
Credit::is_free_signal
bool is_free_signal()
Definition: Credit.hh:58
OutputUnit::is_vc_idle
bool is_vc_idle(int vc, Tick curTime)
Definition: OutputUnit.hh:85
flitBuffer.hh
flitBuffer::functionalWrite
uint32_t functionalWrite(Packet *pkt)
Definition: flitBuffer.cc:80
IDLE_
@ IDLE_
Definition: CommonTypes.hh:40
Credit
Definition: Credit.hh:45
OutputUnit::set_credit_link
void set_credit_link(CreditLink *credit_link)
Definition: OutputUnit.cc:154
OutputUnit::set_out_link
void set_out_link(NetworkLink *link)
Definition: OutputUnit.cc:148
OutputUnit::m_vc_per_vnet
int m_vc_per_vnet
Definition: OutputUnit.hh:104
Router
Definition: Router.hh:56
OutputUnit::decrement_credit
void decrement_credit(int out_vc)
Definition: OutputUnit.cc:53
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
Consumer
Definition: Consumer.hh:43
Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:192
Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:174
ACTIVE_
@ ACTIVE_
Definition: CommonTypes.hh:40
OutputUnit::outBuffer
flitBuffer outBuffer
Definition: OutputUnit.hh:109
OutputUnit::select_free_vc
int select_free_vc(int vnet)
Definition: OutputUnit.cc:102
OutputUnit::insert_flit
void insert_flit(flit *t_flit)
Definition: OutputUnit.cc:160
OutputUnit::set_vc_state
void set_vc_state(VC_state_type state, int vc, Tick curTime)
Definition: OutputUnit.hh:79
Router::getPortDirectionName
std::string getPortDirectionName(PortDirection direction)
Definition: Router.cc:174
SimObject::name
virtual const std::string name() const
Definition: sim_object.hh:133
OutputUnit.hh
OutputUnit::wakeup
void wakeup()
Definition: OutputUnit.cc:124
flitBuffer::insert
void insert(flit *flt)
Definition: flitBuffer.hh:70
flit::get_vc
int get_vc()
Definition: flit.hh:57
Consumer::scheduleEventAbsolute
void scheduleEventAbsolute(Tick timeAbs)
Definition: Consumer.cc:40
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
Credit.hh
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
PortDirection
std::string PortDirection
Definition: Topology.hh:62
OutputUnit::get_direction
PortDirection get_direction()
Definition: OutputUnit.hh:64
Router::get_net_ptr
GarnetNetwork * get_net_ptr()
Definition: Router.hh:88
ArmISA::id
Bitfield< 33 > id
Definition: miscregs_types.hh:247
Consumer::scheduleEvent
void scheduleEvent(Cycles timeDelta)
Definition: Consumer.cc:34
OutputUnit::get_credit_count
int get_credit_count(int vc)
Definition: OutputUnit.hh:67
curTick
Tick curTick()
The current simulated tick.
Definition: core.hh:45
OutputUnit::OutputUnit
OutputUnit(int id, PortDirection direction, Router *router, uint32_t consumerVcs)
Definition: OutputUnit.cc:40
Router.hh

Generated on Wed Sep 30 2020 14:02:13 for gem5 by doxygen 1.8.17