gem5
v20.1.0.0
systemc
tests
systemc
misc
examples
a2901
a2901.h
Go to the documentation of this file.
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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a2901.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#ifndef A2901_H
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#define A2901_H
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#include "
a2901_alu.h
"
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#include "
a2901_alu_inputs.h
"
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#include "
a2901_output_and_shifter.h
"
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#include "
a2901_edge.h
"
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SC_MODULE
( a2901 )
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{
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// shared state
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long
RAM[15];
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// signals
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sig4
RE
, S, F, Q, A;
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sig5
R_ext, S_ext;
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// constructor
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a2901( sc_module_name,
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const
sc_clock& CLK_,
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const
sig9
&
I_
,
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const
sig4
& Aadd_,
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const
sig4
& Badd_,
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const
sig4
& D_,
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const
sig1
& RAM0_,
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const
sig1
& RAM3_,
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const
sig1
& Q0_,
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const
sig1
& Q3_,
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const
sig1
& C0_,
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const
sig1
& OEbar_,
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sig4
& Y_,
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sig1
& t_RAM0_,
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sig1
& t_RAM3_,
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sig1
& t_Q0_,
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sig1
& t_Q3_,
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sig1
& C4_,
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sig1
& Gbar_,
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sig1
& Pbar_,
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sig1
& OVR_,
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sig1
& F3_,
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sig1
& F30_ )
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{
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SC_NEW
( a2901_alu(
"alu"
,
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I_
,
RE
, S, C0_,
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R_ext, S_ext, F, OVR_, C4_, Pbar_, Gbar_,
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F3_, F30_ ) );
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SC_NEW
( a2901_alu_inputs(
"alu_inputs"
,
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RAM,
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I_
, Aadd_, Badd_, D_, Q,
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RE
, S, A ) );
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SC_NEW
( a2901_output_and_shifter(
"o_and_s"
,
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I_
, OEbar_, A, F, Q,
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Y_, t_RAM0_, t_RAM3_,
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t_Q0_, t_Q3_ ) );
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SC_NEW
( a2901_edge(
"edge"
,
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CLK_,
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RAM,
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I_
, Badd_, F, Q3_, Q0_, RAM3_, RAM0_,
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Q ) );
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// initialize the RAM (to get rid of UMRs)
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for
(
int
i
= 0;
i
< 15; ++
i
) {
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RAM[0] = 0;
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}
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}
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};
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#endif
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sig4
sc_signal< int4 > sig4
Definition:
common.h:49
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
SC_NEW
#define SC_NEW(x)
Definition:
sc_module.hh:355
I_
@ I_
Definition:
CommonTypes.hh:42
sig1
sc_signal< int1 > sig1
Definition:
common.h:48
sig5
sc_signal< int5 > sig5
Definition:
common.h:50
X86ISA::RE
const uint8_t RE
Definition:
decoder_tables.cc:53
a2901_edge.h
a2901_alu_inputs.h
sig9
sc_signal< int9 > sig9
Definition:
common.h:51
a2901_output_and_shifter.h
SC_MODULE
SC_MODULE(a2901)
Definition:
a2901.h:46
a2901_alu.h
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