gem5  v20.1.0.0
Namespaces | Functions
utility.hh File Reference
#include "arch/arm/isa_traits.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"

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PCState ArmISA::buildRetPC (const PCState &curPC, const PCState &callPC)
bool ArmISA::testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
void ArmISA::copyRegs (ThreadContext *src, ThreadContext *dest)
static void ArmISA::copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void ArmISA::sendEvent (ThreadContext *tc)
 Send an event (SEV) to a specific PE if there isn't already a pending event. More...
static bool ArmISA::inUserMode (CPSR cpsr)
static bool ArmISA::inUserMode (ThreadContext *tc)
static bool ArmISA::inPrivilegedMode (CPSR cpsr)
static bool ArmISA::inPrivilegedMode (ThreadContext *tc)
bool ArmISA::isSecure (ThreadContext *tc)
bool ArmISA::inAArch64 (ThreadContext *tc)
static OperatingMode ArmISA::currOpMode (const ThreadContext *tc)
static ExceptionLevel ArmISA::currEL (const ThreadContext *tc)
ExceptionLevel ArmISA::currEL (CPSR cpsr)
bool ArmISA::HavePACExt (ThreadContext *tc)
bool ArmISA::HaveVirtHostExt (ThreadContext *tc)
bool ArmISA::HaveSecureEL2Ext (ThreadContext *tc)
bool ArmISA::IsSecureEL2Enabled (ThreadContext *tc)
bool ArmISA::EL2Enabled (ThreadContext *tc)
std::pair< bool, bool > ArmISA::ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
 This function checks whether selected EL provided as an argument is using the AArch32 ISA. More...
std::pair< bool, bool > ArmISA::ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
bool ArmISA::ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
bool ArmISA::ELIs32 (ThreadContext *tc, ExceptionLevel el)
bool ArmISA::ELIs64 (ThreadContext *tc, ExceptionLevel el)
bool ArmISA::ELIsInHost (ThreadContext *tc, ExceptionLevel el)
 Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions). More...
ExceptionLevel ArmISA::debugTargetFrom (ThreadContext *tc, bool secure)
bool ArmISA::isBigEndian64 (const ThreadContext *tc)
bool ArmISA::badMode32 (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32 More...
bool ArmISA::badMode (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented. More...
static uint8_t ArmISA::itState (CPSR psr)
ExceptionLevel ArmISA::s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
Addr ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
 Removes the tag from tagged addresses if that mode is enabled. More...
Addr ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool isInstr)
int ArmISA::computeAddrTop (ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
static bool ArmISA::inSecureState (SCR scr, CPSR cpsr)
bool ArmISA::isSecureBelowEL3 (ThreadContext *tc)
bool ArmISA::longDescFormatInUse (ThreadContext *tc)
RegVal ArmISA::readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems) More...
RegVal ArmISA::getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is returning the value of MPIDR_EL1. More...
RegVal ArmISA::getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
 Retrieves MPIDR_EL1. More...
static uint32_t ArmISA::mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
static void ArmISA::mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
static uint32_t ArmISA::mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
static uint32_t ArmISA::msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
Fault ArmISA::mcrMrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
bool ArmISA::mcrMrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
bool ArmISA::mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
Fault ArmISA::mcrrMrrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
bool ArmISA::mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Fault ArmISA::AArch64AArch32SystemAccessTrap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
bool ArmISA::isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool ArmISA::condGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerCommonEL0HypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool ArmISA::isGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool ArmISA::isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex miscReg, ThreadContext *tc)
bool ArmISA::SPAlignmentCheckEnabled (ThreadContext *tc)
uint64_t ArmISA::getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void ArmISA::advancePC (PCState &pc, const StaticInstPtr &inst)
Addr ArmISA::truncPage (Addr addr)
Addr ArmISA::roundPage (Addr addr)
uint64_t ArmISA::getExecutingAsid (ThreadContext *tc)
bool ArmISA::decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
static int ArmISA::decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
int ArmISA::decodePhysAddrRange64 (uint8_t pa_enc)
 Returns the n. More...
uint8_t ArmISA::encodePhysAddrRange64 (int pa_size)
 Returns the encoding corresponding to the specified n. More...
ByteOrder ArmISA::byteOrder (const ThreadContext *tc)
bool ArmISA::isUnpriviledgeAccess (ThreadContext *tc)

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