gem5  v20.1.0.0
static_inst.hh
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41 
42 #ifndef __CPU_STATIC_INST_HH__
43 #define __CPU_STATIC_INST_HH__
44 
45 #include <bitset>
46 #include <memory>
47 #include <string>
48 
49 #include "arch/registers.hh"
50 #include "arch/types.hh"
51 #include "base/logging.hh"
52 #include "base/refcnt.hh"
53 #include "base/types.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/op_class.hh"
56 #include "cpu/reg_class.hh"
57 #include "cpu/static_inst_fwd.hh"
58 #include "cpu/thread_context.hh"
59 #include "enums/StaticInstFlags.hh"
60 #include "sim/byteswap.hh"
61 
62 // forward declarations
63 class Packet;
64 
65 class ExecContext;
66 
67 namespace Loader
68 {
69 class SymbolTable;
70 } // namespace Loader
71 
72 namespace Trace
73 {
74 class InstRecord;
75 } // namespace Trace
76 
85 class StaticInst : public RefCounted, public StaticInstFlags
86 {
87  public:
90 
91  enum {
92  MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
93  MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
94  };
95 
96  protected:
97 
99  std::bitset<Num_Flags> flags;
100 
102  OpClass _opClass;
103 
105  int8_t _numSrcRegs;
106 
108  int8_t _numDestRegs;
109 
112 
117 
125  public:
126 
133 
134  int8_t numSrcRegs() const { return _numSrcRegs; }
137  int8_t numDestRegs() const { return _numDestRegs; }
139  int8_t numFPDestRegs() const { return _numFPDestRegs; }
141  int8_t numIntDestRegs() const { return _numIntDestRegs; }
143  int8_t numVecDestRegs() const { return _numVecDestRegs; }
145  int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
147  int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
149  int8_t numCCDestRegs() const { return _numCCDestRegs; }
151 
156 
157 
158  bool isNop() const { return flags[IsNop]; }
159 
160  bool isMemRef() const { return flags[IsMemRef]; }
161  bool isLoad() const { return flags[IsLoad]; }
162  bool isStore() const { return flags[IsStore]; }
163  bool isAtomic() const { return flags[IsAtomic]; }
164  bool isStoreConditional() const { return flags[IsStoreConditional]; }
165  bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
166  bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
167  bool isPrefetch() const { return isInstPrefetch() ||
168  isDataPrefetch(); }
169 
170  bool isInteger() const { return flags[IsInteger]; }
171  bool isFloating() const { return flags[IsFloating]; }
172  bool isVector() const { return flags[IsVector]; }
173  bool isCC() const { return flags[IsCC]; }
174 
175  bool isControl() const { return flags[IsControl]; }
176  bool isCall() const { return flags[IsCall]; }
177  bool isReturn() const { return flags[IsReturn]; }
178  bool isDirectCtrl() const { return flags[IsDirectControl]; }
179  bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
180  bool isCondCtrl() const { return flags[IsCondControl]; }
181  bool isUncondCtrl() const { return flags[IsUncondControl]; }
182  bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
183 
184  bool isThreadSync() const { return flags[IsThreadSync]; }
185  bool isSerializing() const { return flags[IsSerializing] ||
186  flags[IsSerializeBefore] ||
187  flags[IsSerializeAfter]; }
188  bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
189  bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
190  bool isSquashAfter() const { return flags[IsSquashAfter]; }
191  bool isMemBarrier() const { return flags[IsMemBarrier]; }
192  bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
193  bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
194  bool isQuiesce() const { return flags[IsQuiesce]; }
195  bool isIprAccess() const { return flags[IsIprAccess]; }
196  bool isUnverifiable() const { return flags[IsUnverifiable]; }
197  bool isSyscall() const { return flags[IsSyscall]; }
198  bool isMacroop() const { return flags[IsMacroop]; }
199  bool isMicroop() const { return flags[IsMicroop]; }
200  bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
201  bool isLastMicroop() const { return flags[IsLastMicroop]; }
202  bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
203  //This flag doesn't do anything yet
204  bool isMicroBranch() const { return flags[IsMicroBranch]; }
205  // hardware transactional memory
206  // HtmCmds must be identified as such in order
207  // to provide them with necessary memory ordering semantics.
208  bool isHtmStart() const { return flags[IsHtmStart]; }
209  bool isHtmStop() const { return flags[IsHtmStop]; }
210  bool isHtmCancel() const { return flags[IsHtmCancel]; }
211 
212  bool
213  isHtmCmd() const
214  {
215  return isHtmStart() || isHtmStop() || isHtmCancel();
216  }
218 
219  void setFirstMicroop() { flags[IsFirstMicroop] = true; }
220  void setLastMicroop() { flags[IsLastMicroop] = true; }
221  void setDelayedCommit() { flags[IsDelayedCommit] = true; }
222  void setFlag(Flags f) { flags[f] = true; }
223 
225  OpClass opClass() const { return _opClass; }
226 
227 
230  const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
231 
234  const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
235 
238 
241 
244 
245  protected:
246 
251 
258  const char *mnemonic;
259 
264  mutable std::string *cachedDisassembly;
265 
269  virtual std::string
270  generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const = 0;
271 
277  StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
278  : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
281  machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
282  { }
283 
284  public:
285  virtual ~StaticInst();
286 
287  virtual Fault execute(ExecContext *xc,
288  Trace::InstRecord *traceData) const = 0;
289 
291  Trace::InstRecord *traceData) const
292  {
293  panic("initiateAcc not defined!");
294  }
295 
296  virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
297  Trace::InstRecord *traceData) const
298  {
299  panic("completeAcc not defined!");
300  }
301 
302  virtual void advancePC(TheISA::PCState &pcState) const = 0;
303 
308  virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
309 
315  virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
316 
324  virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
325 
331  TheISA::PCState &tgt) const;
332 
340  virtual const std::string &disassemble(Addr pc,
341  const Loader::SymbolTable *symtab=nullptr) const;
342 
347  void printFlags(std::ostream &outs, const std::string &separator) const;
348 
350  std::string getName() { return mnemonic; }
351 
352  protected:
353  template<typename T>
354  size_t
355  simpleAsBytes(void *buf, size_t max_size, const T &t)
356  {
357  size_t size = sizeof(T);
358  if (size <= max_size)
359  *reinterpret_cast<T *>(buf) = htole<T>(t);
360  return size;
361  }
362 
363  public:
375  virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
376 };
377 
378 #endif // __CPU_STATIC_INST_HH__
StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:197
refcnt.hh
StaticInst::_numIntDestRegs
int8_t _numIntDestRegs
Definition: static_inst.hh:114
StaticInst::numCCDestRegs
int8_t numCCDestRegs() const
Number of coprocesor destination regs.
Definition: static_inst.hh:149
StaticInst::_numVecDestRegs
int8_t _numVecDestRegs
To use in architectures with vector register file.
Definition: static_inst.hh:120
StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:99
StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:178
StaticInst::isMicroBranch
bool isMicroBranch() const
Definition: static_inst.hh:204
StaticInst::initiateAcc
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:290
op_class.hh
StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:230
StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:160
StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pcState) const =0
StaticInst::isCC
bool isCC() const
Definition: static_inst.hh:173
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
StaticInst::isSerializing
bool isSerializing() const
Definition: static_inst.hh:185
Flags
Definition: flags.hh:33
Trace
Definition: nativetrace.cc:52
StaticInst::hasBranchTarget
bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
Return true if the instruction is a control transfer, and if so, return the target address as well.
Definition: static_inst.cc:81
StaticInst::numIntDestRegs
int8_t numIntDestRegs() const
Number of integer destination regs.
Definition: static_inst.hh:141
Loader::SymbolTable
Definition: symtab.hh:59
Trace::InstRecord
Definition: insttracer.hh:55
StaticInst::isIprAccess
bool isIprAccess() const
Definition: static_inst.hh:195
StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:225
StaticInst::isSerializeAfter
bool isSerializeAfter() const
Definition: static_inst.hh:189
ArmISA::MaxInstSrcRegs
const int MaxInstSrcRegs
Definition: registers.hh:57
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:170
StaticInst::_numVecElemDestRegs
int8_t _numVecElemDestRegs
Definition: static_inst.hh:121
StaticInst::setDelayedCommit
void setDelayedCommit()
Definition: static_inst.hh:221
Loader
Definition: process.hh:39
StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:162
StaticInst::isHtmCmd
bool isHtmCmd() const
Definition: static_inst.hh:213
StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:202
StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:161
StaticInst::cachedDisassembly
std::string * cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:264
StaticInst::isHtmStart
bool isHtmStart() const
Definition: static_inst.hh:208
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:200
StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:105
StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:130
StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:137
StaticInst::isHtmCancel
bool isHtmCancel() const
Definition: static_inst.hh:210
StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:163
StaticInst::StaticInst
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: static_inst.hh:277
StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:175
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
StaticInst::isSerializeBefore
bool isSerializeBefore() const
Definition: static_inst.hh:188
StaticInst::_numCCDestRegs
int8_t _numCCDestRegs
Definition: static_inst.hh:115
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition: static_inst.hh:250
StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:198
StaticInst::isSquashAfter
bool isSquashAfter() const
Definition: static_inst.hh:190
StaticInst::getName
std::string getName()
Return name of machine instruction.
Definition: static_inst.hh:350
StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:166
StaticInst::_destRegIdx
RegId _destRegIdx[MaxInstDestRegs]
See destRegIdx().
Definition: static_inst.hh:248
StaticInst::setFlag
void setFlag(Flags f)
Definition: static_inst.hh:222
ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:70
StaticInst::isNonSpeculative
bool isNonSpeculative() const
Definition: static_inst.hh:193
StaticInst::~StaticInst
virtual ~StaticInst()
Definition: static_inst.cc:74
StaticInst::_opClass
OpClass _opClass
See opClass().
Definition: static_inst.hh:102
StaticInst::MaxInstSrcRegs
@ MaxInstSrcRegs
Definition: static_inst.hh:92
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition: static_inst.hh:89
StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:179
StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:234
StaticInst::asBytes
virtual size_t asBytes(void *buf, size_t max_size)
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:375
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
StaticInst::nullStaticInstPtr
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
Definition: static_inst.hh:237
StaticInst::_numVecPredDestRegs
int8_t _numVecPredDestRegs
Definition: static_inst.hh:122
StaticInst::isPrefetch
bool isPrefetch() const
Definition: static_inst.hh:167
StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:199
StaticInst::isWriteBarrier
bool isWriteBarrier() const
Definition: static_inst.hh:192
StaticInst::numSrcRegs
int8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:135
StaticInst::isThreadSync
bool isThreadSync() const
Definition: static_inst.hh:184
StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:355
StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:165
StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:201
StaticInst::isNop
bool isNop() const
Definition: static_inst.hh:158
RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:57
StaticInst::numVecDestRegs
int8_t numVecDestRegs() const
Number of vector destination regs.
Definition: static_inst.hh:143
StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:98
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
StaticInst::isHtmStop
bool isHtmStop() const
Definition: static_inst.hh:209
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
types.hh
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:121
StaticInst::isCondDelaySlot
bool isCondDelaySlot() const
Definition: static_inst.hh:182
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
static_inst_fwd.hh
StaticInst::completeAcc
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:296
reg_class.hh
StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:176
logging.hh
StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:105
StaticInst::setFirstMicroop
void setFirstMicroop()
Definition: static_inst.hh:219
StaticInst::isUnverifiable
bool isUnverifiable() const
Definition: static_inst.hh:196
StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:171
RefCountingPtr
If you want a reference counting pointer to a mutable object, create it like this:
Definition: refcnt.hh:118
StaticInst::_numFPDestRegs
int8_t _numFPDestRegs
The following are used to track physical register usage for machines with separate int & FP reg files...
Definition: static_inst.hh:113
StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:180
StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
StaticInst::isQuiesce
bool isQuiesce() const
Definition: static_inst.hh:194
MicroPC
uint16_t MicroPC
Definition: types.hh:144
StaticInst::nopStaticInstPtr
static StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
Definition: static_inst.hh:240
StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:177
StaticInst::MaxInstDestRegs
@ MaxInstDestRegs
Definition: static_inst.hh:93
StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:172
StaticInst::numFPDestRegs
int8_t numFPDestRegs() const
Number of floating-point destination regs.
Definition: static_inst.hh:139
StaticInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Number of vector element destination regs.
Definition: static_inst.hh:145
StaticInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Number of predicate destination regs.
Definition: static_inst.hh:147
StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
StaticInst::setLastMicroop
void setLastMicroop()
Definition: static_inst.hh:220
thread_context.hh
StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:181
StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:108
StaticInst::isMemBarrier
bool isMemBarrier() const
Definition: static_inst.hh:191
byteswap.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::f
Bitfield< 6 > f
Definition: miscregs_types.hh:64
StaticInst::isStoreConditional
bool isStoreConditional() const
Definition: static_inst.hh:164
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39

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