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43 #ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__
44 #define __CPU_TRAFFIC_GEN_BASE_GEN_HH__
105 virtual void enter() = 0;
138 Addr _blocksize,
Addr cacheline_size,
140 uint8_t read_percent,
Addr data_limit);
Base class for all generators, with the shared functionality and virtual functions for entering,...
uint64_t Tick
Tick count type.
std::string name() const
Get the name, useful for DPRINTFs.
virtual PacketPtr getNextPacket()=0
Get the next generated packet.
const uint8_t readPercent
Percent of generated transactions that should be reads.
virtual void exit()
Exit this generator state.
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
const Tick duration
Time to spend in this state.
StochasticGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)
const Tick minPeriod
Request generation period.
virtual Tick nextPacketTick(bool elastic, Tick delay) const =0
Determine the tick when the next packet is available.
BaseGen(SimObject &obj, RequestorID requestor_id, Tick _duration)
Create a base generator.
virtual void enter()=0
Enter this generator state.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
const Addr blocksize
Blocksize and address increment.
const Addr cacheLineSize
Cache line size in the simulated system.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
const std::string _name
Name to use for status and debug printing.
const Addr endAddr
End of address range.
const RequestorID requestorId
The RequestorID used for generating requests.
const Addr startAddr
Start of address range.
const Addr dataLimit
Maximum amount of data to manipulate.
Abstract superclass for simulation objects.
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