gem5  v20.1.0.0
ArmISA::SveBinDestrPredOp Member List

This is the complete list of members for ArmISA::SveBinDestrPredOp, including all inherited members.

_destRegIdxStaticInstprotected
_numCCDestRegsStaticInstprotected
_numDestRegsStaticInstprotected
_numFPDestRegsStaticInstprotected
_numIntDestRegsStaticInstprotected
_numSrcRegsStaticInstprotected
_numVecDestRegsStaticInstprotected
_numVecElemDestRegsStaticInstprotected
_numVecPredDestRegsStaticInstprotected
_opClassStaticInstprotected
_srcRegIdxStaticInstprotected
aarch64ArmISA::ArmStaticInstprotected
activateBreakpoint(ThreadContext *tc)ArmISA::ArmStaticInstinlineprotectedstatic
advancePC(PCState &pcState) const overrideArmISA::ArmStaticInstinlineprotected
StaticInst::advancePC(TheISA::PCState &pcState) const =0StaticInstpure virtual
advSIMDFPAccessTrap64(ExceptionLevel el) constArmISA::ArmStaticInstprotected
annotateFault(ArmFault *fault)ArmISA::ArmStaticInstinlinevirtual
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)ArmISA::ArmStaticInstinlineprotected
asBytes(void *buf, size_t max_size) overrideArmISA::ArmStaticInstinlinevirtual
branchTarget(const TheISA::PCState &pc) constStaticInstvirtual
branchTarget(ThreadContext *tc) constStaticInstvirtual
cachedDisassemblyStaticInstmutableprotected
checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) constArmISA::ArmStaticInstprotected
checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) constArmISA::ArmStaticInstprotected
checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) constArmISA::ArmStaticInstprotected
checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) constArmISA::ArmStaticInstprotected
checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) constArmISA::ArmStaticInstprotected
checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) constArmISA::ArmStaticInstprotected
checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) constArmISA::ArmStaticInstprotected
completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) constStaticInstinlinevirtual
countRefCountedmutableprivate
cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)ArmISA::ArmStaticInstinlineprotectedstatic
decref() constRefCountedinline
destArmISA::SveBinDestrPredOpprotected
destRegIdx(int i) constStaticInstinline
disabledFault() constArmISA::ArmStaticInstinlineprotected
disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) constStaticInstvirtual
encoding() constArmISA::ArmStaticInstinline
execute(ExecContext *xc, Trace::InstRecord *traceData) const =0StaticInstpure virtual
extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) constArmISA::ArmStaticInstprotected
ExtMachInst typedefStaticInst
fetchMicroop(MicroPC upc) constStaticInstvirtual
flagsStaticInstprotected
generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) constArmISA::ArmStaticInstprotected
generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const overrideArmISA::SveBinDestrPredOpprotectedvirtual
getCurSveVecLen(ThreadContext *tc)ArmISA::ArmStaticInstinlinestatic
getCurSveVecLenInBits(ThreadContext *tc)ArmISA::ArmStaticInststatic
getCurSveVecLenInQWords(ThreadContext *tc)ArmISA::ArmStaticInstinlinestatic
getIntWidth() constArmISA::ArmStaticInstinline
getName()StaticInstinline
getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) constArmISA::ArmStaticInstprotected
gpArmISA::SveBinDestrPredOpprotected
hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) constStaticInst
incref() constRefCountedinline
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) constStaticInstinlinevirtual
instSize() constArmISA::ArmStaticInstinline
intWidthArmISA::ArmStaticInstprotected
isAtomic() constStaticInstinline
isCall() constStaticInstinline
isCC() constStaticInstinline
isCondCtrl() constStaticInstinline
isCondDelaySlot() constStaticInstinline
isControl() constStaticInstinline
isDataPrefetch() constStaticInstinline
isDelayedCommit() constStaticInstinline
isDirectCtrl() constStaticInstinline
isFirstMicroop() constStaticInstinline
isFloating() constStaticInstinline
isHtmCancel() constStaticInstinline
isHtmCmd() constStaticInstinline
isHtmStart() constStaticInstinline
isHtmStop() constStaticInstinline
isIndirectCtrl() constStaticInstinline
isInstPrefetch() constStaticInstinline
isInteger() constStaticInstinline
isIprAccess() constStaticInstinline
isLastMicroop() constStaticInstinline
isLoad() constStaticInstinline
isMacroop() constStaticInstinline
isMemBarrier() constStaticInstinline
isMemRef() constStaticInstinline
isMicroBranch() constStaticInstinline
isMicroop() constStaticInstinline
isNonSpeculative() constStaticInstinline
isNop() constStaticInstinline
isPrefetch() constStaticInstinline
isQuiesce() constStaticInstinline
isReturn() constStaticInstinline
isSerializeAfter() constStaticInstinline
isSerializeBefore() constStaticInstinline
isSerializing() constStaticInstinline
isSquashAfter() constStaticInstinline
isStore() constStaticInstinline
isStoreConditional() constStaticInstinline
isSyscall() constStaticInstinline
isThreadSync() constStaticInstinline
isUncondCtrl() constStaticInstinline
isUnverifiable() constStaticInstinline
isVector() constStaticInstinline
isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) constArmISA::ArmStaticInstinlineprotected
isWriteBarrier() constStaticInstinline
machInstStaticInst
MaxInstDestRegs enum valueStaticInst
MaxInstSrcRegs enum valueStaticInst
mnemonicStaticInstprotected
nopStaticInstPtrStaticInststatic
nullStaticInstPtrStaticInststatic
numCCDestRegs() constStaticInstinline
numDestRegs() constStaticInstinline
numFPDestRegs() constStaticInstinline
numIntDestRegs() constStaticInstinline
numSrcRegs() constStaticInstinline
numVecDestRegs() constStaticInstinline
numVecElemDestRegs() constStaticInstinline
numVecPredDestRegs() constStaticInstinline
op2ArmISA::SveBinDestrPredOpprotected
opClass() constStaticInstinline
operator=(const RefCounted &)RefCountedprivate
printCCReg(std::ostream &os, RegIndex reg_idx) constArmISA::ArmStaticInstprotected
printCondition(std::ostream &os, unsigned code, bool noImplicit=false) constArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm) constArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) constArmISA::ArmStaticInstprotected
printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) constArmISA::ArmStaticInstprotected
printFlags(std::ostream &outs, const std::string &separator) constStaticInst
printFloatReg(std::ostream &os, RegIndex reg_idx) constArmISA::ArmStaticInstprotected
printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) constArmISA::ArmStaticInstprotected
printMemSymbol(std::ostream &os, const Loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) constArmISA::ArmStaticInstprotected
printMiscReg(std::ostream &os, RegIndex reg_idx) constArmISA::ArmStaticInstprotected
printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) constArmISA::ArmStaticInstprotected
printPFflags(std::ostream &os, int flag) constArmISA::ArmStaticInstprotected
printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) constArmISA::ArmStaticInstprotected
printTarget(std::ostream &os, Addr target, const Loader::SymbolTable *symtab) constArmISA::ArmStaticInstprotected
printVecPredReg(std::ostream &os, RegIndex reg_idx) constArmISA::ArmStaticInstprotected
printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) constArmISA::ArmStaticInstprotected
readPC(ExecContext *xc)ArmISA::ArmStaticInstinlineprotectedstatic
RefCounted(const RefCounted &)RefCountedprivate
RefCounted()RefCountedinline
satInt(int32_t &res, int64_t op, int width)ArmISA::ArmStaticInstinlineprotectedstatic
saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)ArmISA::ArmStaticInstinlineprotectedstatic
setAIWNextPC(ExecContext *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
setDelayedCommit()StaticInstinline
setFirstMicroop()StaticInstinline
setFlag(Flags f)StaticInstinline
setIWNextPC(ExecContext *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
setLastMicroop()StaticInstinline
setNextPC(ExecContext *xc, Addr val)ArmISA::ArmStaticInstinlineprotectedstatic
shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constArmISA::ArmStaticInstprotected
shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constArmISA::ArmStaticInstprotected
shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constArmISA::ArmStaticInstprotected
shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constArmISA::ArmStaticInstprotected
shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) constArmISA::ArmStaticInstprotected
simpleAsBytes(void *buf, size_t max_size, const T &t)StaticInstinlineprotected
softwareBreakpoint32(ExecContext *xc, uint16_t imm) constArmISA::ArmStaticInstprotected
spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)ArmISA::ArmStaticInstinlineprotectedstatic
srcRegIdx(int i) constStaticInstinline
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)StaticInstinlineprotected
sveAccessTrap(ExceptionLevel el) constArmISA::ArmStaticInstprotected
SveBinDestrPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2, IntRegIndex _gp)ArmISA::SveBinDestrPredOpinlineprotected
trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) constArmISA::ArmStaticInstprotected
undefinedFault32(ThreadContext *tc, ExceptionLevel el) constArmISA::ArmStaticInstprotected
undefinedFault64(ThreadContext *tc, ExceptionLevel el) constArmISA::ArmStaticInstprotected
uSatInt(int32_t &res, int64_t op, int width)ArmISA::ArmStaticInstinlineprotectedstatic
uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)ArmISA::ArmStaticInstinlineprotectedstatic
~RefCounted()RefCountedinlinevirtual
~StaticInst()StaticInstvirtual

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