gem5  v20.1.0.0
Public Types | Protected Attributes | List of all members
StaticInst Class Referenceabstract

Base, ISA-independent static instruction class. More...

#include <static_inst.hh>

Inheritance diagram for StaticInst:
RefCounted ArmISA::ArmStaticInst PowerISA::PowerStaticInst RiscvISA::RiscvStaticInst SparcISA::SparcStaticInst X86ISA::X86StaticInst ArmISA::BranchEret64 ArmISA::BranchEretA64 ArmISA::BranchImm64 ArmISA::BranchImmImmReg64 ArmISA::BranchImmReg64 ArmISA::BranchReg64 ArmISA::BranchRegReg64 ArmISA::DataX1Reg2ImmOp ArmISA::DataX1RegImmOp ArmISA::DataX1RegOp ArmISA::DataX2RegImmOp ArmISA::DataX2RegOp ArmISA::DataX3RegOp ArmISA::DataXCondCompImmOp ArmISA::DataXCondCompRegOp ArmISA::DataXCondSelOp ArmISA::DataXERegOp ArmISA::DataXImmOnlyOp ArmISA::DataXImmOp ArmISA::DataXSRegOp ArmISA::MicroOpX ArmISA::MightBeMicro64 ArmISA::PredOp ArmISA::SveAdrOp ArmISA::SveBinConstrPredOp ArmISA::SveBinDestrPredOp ArmISA::SveBinIdxUnpredOp ArmISA::SveBinImmIdxUnpredOp ArmISA::SveBinImmPredOp ArmISA::SveBinImmUnpredConstrOp ArmISA::SveBinImmUnpredDestrOp ArmISA::SveBinUnpredOp ArmISA::SveBinWideImmUnpredOp ArmISA::SveCmpImmOp ArmISA::SveCmpOp ArmISA::SveComplexIdxOp ArmISA::SveComplexOp ArmISA::SveCompTermOp ArmISA::SveContigMemSI ArmISA::SveContigMemSS ArmISA::SveDotProdIdxOp ArmISA::SveDotProdOp ArmISA::SveElemCountOp ArmISA::SveIndexIIOp ArmISA::SveIndexIROp ArmISA::SveIndexRIOp ArmISA::SveIndexRROp ArmISA::SveIntCmpImmOp ArmISA::SveIntCmpOp ArmISA::SveMemPredFillSpill ArmISA::SveMemVecFillSpill ArmISA::SveOrdReducOp ArmISA::SvePartBrkOp ArmISA::SvePartBrkPropOp ArmISA::SvePredBinPermOp ArmISA::SvePredCountOp ArmISA::SvePredCountPredOp ArmISA::SvePredLogicalOp ArmISA::SvePredTestOp ArmISA::SvePredUnaryWImplicitDstOp ArmISA::SvePredUnaryWImplicitSrcOp ArmISA::SvePredUnaryWImplicitSrcPredOp ArmISA::SvePtrueOp ArmISA::SveReducOp ArmISA::SveSelectOp ArmISA::SveTblOp ArmISA::SveTerImmUnpredOp ArmISA::SveTerPredOp ArmISA::SveUnaryPredOp ArmISA::SveUnaryPredPredOp ArmISA::SveUnarySca2VecUnpredOp ArmISA::SveUnaryUnpredOp ArmISA::SveUnaryWideImmPredOp ArmISA::SveUnaryWideImmUnpredOp ArmISA::SveUnpackOp ArmISA::SveWhileOp ArmISA::SveWImplicitSrcDstOp ArmISAInst::TmeImmOp64 ArmISAInst::TmeRegNone64 DebugStep DecoderFaultInst FailUnimplemented IllegalExecInst ImmOp64 McrMrcMiscInst MiscRegOp64 RegNone RegRegImmImmOp64 RegRegRegImmOp64 UnknownOp64 WarnUnimplemented PowerISA::CondLogicOp PowerISA::CondMoveOp PowerISA::FloatOp PowerISA::IntOp PowerISA::MemOp PowerISA::MiscOp PowerISA::PCDependentDisassembly RiscvISA::CompRegOp RiscvISA::CSROp RiscvISA::ImmOp< I > RiscvISA::MemInst RiscvISA::PseudoOp RiscvISA::RegOp RiscvISA::RiscvMacroInst RiscvISA::RiscvMicroInst RiscvISA::SystemOp RiscvISA::Unknown SparcISA::Branch SparcISA::FailUnimplemented SparcISA::FpUnimpl SparcISA::IntOp SparcISA::Mem SparcISA::Nop SparcISA::Priv SparcISA::SparcMacroInst SparcISA::SparcMicroInst SparcISA::Trap SparcISA::Unknown SparcISA::WarnUnimplemented X86ISA::MacroopBase X86ISA::X86MicroopBase

Public Types

enum  { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }
 
typedef TheISA::ExtMachInst ExtMachInst
 Binary extended machine instruction type. More...
 

Public Member Functions

Register information.

The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(), numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().

The former two functions are used to track physical register usage for machines with separate int & FP reg files, the next three are for machines with vector and predicate register files.

int8_t numSrcRegs () const
 Number of source registers. More...
 
int8_t numDestRegs () const
 Number of destination registers. More...
 
int8_t numFPDestRegs () const
 Number of floating-point destination regs. More...
 
int8_t numIntDestRegs () const
 Number of integer destination regs. More...
 
int8_t numVecDestRegs () const
 Number of vector destination regs. More...
 
int8_t numVecElemDestRegs () const
 Number of vector element destination regs. More...
 
int8_t numVecPredDestRegs () const
 Number of predicate destination regs. More...
 
int8_t numCCDestRegs () const
 Number of coprocesor destination regs. More...
 
- Public Member Functions inherited from RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
 
void incref () const
 Increment the reference count. More...
 
void decref () const
 Decrement the reference count and destroy the object if all references are gone. More...
 

Protected Attributes

std::bitset< Num_Flags > flags
 Flag values for this instruction. More...
 
OpClass _opClass
 See opClass(). More...
 
int8_t _numSrcRegs
 See numSrcRegs(). More...
 
int8_t _numDestRegs
 See numDestRegs(). More...
 
int8_t _numFPDestRegs
 The following are used to track physical register usage for machines with separate int & FP reg files. More...
 
int8_t _numIntDestRegs
 
int8_t _numCCDestRegs
 
int8_t _numVecDestRegs
 To use in architectures with vector register file. More...
 
int8_t _numVecElemDestRegs
 
int8_t _numVecPredDestRegs
 

Flag accessors.

These functions are used to access the values of the various instruction property flags.

See StaticInst::Flags for descriptions of the individual flags.

RegId _destRegIdx [MaxInstDestRegs]
 See destRegIdx(). More...
 
RegId _srcRegIdx [MaxInstSrcRegs]
 See srcRegIdx(). More...
 
const char * mnemonic
 Base mnemonic (e.g., "add"). More...
 
std::string * cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()). More...
 
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object. More...
 
static StaticInstPtr nopStaticInstPtr = new NopStaticInst
 Pointer to a statically allocated generic "nop" instruction object. More...
 
const ExtMachInst machInst
 The binary machine instruction. More...
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isVector () const
 
bool isCC () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isCondDelaySlot () const
 
bool isThreadSync () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isMemBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isIprAccess () const
 
bool isUnverifiable () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isMicroBranch () const
 
bool isHtmStart () const
 
bool isHtmStop () const
 
bool isHtmCancel () const
 
bool isHtmCmd () const
 
void setFirstMicroop ()
 
void setLastMicroop ()
 
void setDelayedCommit ()
 
void setFlag (Flags f)
 
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue. More...
 
const RegIddestRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg. More...
 
const RegIdsrcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg. More...
 
virtual ~StaticInst ()
 
virtual Fault execute (ExecContext *xc, Trace::InstRecord *traceData) const =0
 
virtual Fault initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual void advancePC (TheISA::PCState &pcState) const =0
 
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc. More...
 
virtual TheISA::PCState branchTarget (const TheISA::PCState &pc) const
 Return the target address for a PC-relative branch. More...
 
virtual TheISA::PCState branchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump). More...
 
bool hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
 Return true if the instruction is a control transfer, and if so, return the target address as well. More...
 
virtual const std::string & disassemble (Addr pc, const Loader::SymbolTable *symtab=nullptr) const
 Return string representation of disassembled instruction. More...
 
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream. More...
 
std::string getName ()
 Return name of machine instruction. More...
 
virtual size_t asBytes (void *buf, size_t max_size)
 Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...
 
virtual std::string generateDisassembly (Addr pc, const Loader::SymbolTable *symtab) const =0
 Internal function to generate disassembly string. More...
 
 StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 Constructor. More...
 
template<typename T >
size_t simpleAsBytes (void *buf, size_t max_size, const T &t)
 

Detailed Description

Base, ISA-independent static instruction class.

The main component of this class is the vector of flags and the associated methods for reading them. Any object that can rely solely on these flags can process instructions without being recompiled for multiple ISAs.

Definition at line 85 of file static_inst.hh.

Member Typedef Documentation

◆ ExtMachInst

typedef TheISA::ExtMachInst StaticInst::ExtMachInst

Binary extended machine instruction type.

Definition at line 89 of file static_inst.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
Enumerator
MaxInstSrcRegs 
MaxInstDestRegs 

Definition at line 91 of file static_inst.hh.

Constructor & Destructor Documentation

◆ StaticInst()

StaticInst::StaticInst ( const char *  _mnemonic,
ExtMachInst  _machInst,
OpClass  __opClass 
)
inlineprotected

Constructor.

It's important to initialize everything here to a sane default, since the decoder generally only overrides the fields that are meaningful for the particular instruction.

Definition at line 277 of file static_inst.hh.

◆ ~StaticInst()

StaticInst::~StaticInst ( )
virtual

Definition at line 74 of file static_inst.cc.

Member Function Documentation

◆ advancePC()

virtual void StaticInst::advancePC ( TheISA::PCState &  pcState) const
pure virtual

◆ asBytes()

virtual size_t StaticInst::asBytes ( void *  buf,
size_t  max_size 
)
inlinevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented in SparcISA::SparcStaticInst, RiscvISA::RiscvStaticInst, ArmISA::ArmStaticInst, and PowerISA::PowerStaticInst.

Definition at line 375 of file static_inst.hh.

◆ branchTarget() [1/2]

TheISA::PCState StaticInst::branchTarget ( const TheISA::PCState &  pc) const
virtual

Return the target address for a PC-relative branch.

Invalid if not a PC-relative branch (i.e. isDirectCtrl() should be true).

Definition at line 105 of file static_inst.cc.

References panic.

Referenced by BaseDynInst< Impl >::branchTarget().

◆ branchTarget() [2/2]

TheISA::PCState StaticInst::branchTarget ( ThreadContext tc) const
virtual

Return the target address for an indirect branch (jump).

The register value is read from the supplied thread context, so the result is valid only if the thread context is about to execute the branch in question. Invalid if not an indirect branch (i.e. isIndirectCtrl() should be true).

Reimplemented in PowerISA::BranchRegCond.

Definition at line 113 of file static_inst.cc.

References panic.

◆ completeAcc()

virtual Fault StaticInst::completeAcc ( Packet pkt,
ExecContext xc,
Trace::InstRecord traceData 
) const
inlinevirtual

Definition at line 296 of file static_inst.hh.

References panic.

Referenced by TimingSimpleCPU::completeDataAccess().

◆ destRegIdx()

const RegId& StaticInst::destRegIdx ( int  i) const
inline

Return logical index (architectural reg num) of i'th destination reg.

Only the entries from 0 through numDestRegs()-1 are valid.

Definition at line 230 of file static_inst.hh.

References _destRegIdx, and ArmISA::i.

Referenced by Trace::TarmacTracerRecordV8::addRegEntry(), Trace::TarmacTracerRecord::addRegEntry(), BaseDynInst< Impl >::destRegIdx(), BaseO3DynInst< Impl >::forwardOldRegs(), Minor::Scoreboard::markupInstDests(), and Minor::MinorDynInst::minorTraceInst().

◆ disassemble()

const string & StaticInst::disassemble ( Addr  pc,
const Loader::SymbolTable symtab = nullptr 
) const
virtual

Return string representation of disassembled instruction.

The default version of this function will call the internal virtual generateDisassembly() function to get the string, then cache it in cachedDisassembly. If the disassembly should not be cached, this function should be overridden directly.

Reimplemented in PowerISA::PCDependentDisassembly.

Definition at line 121 of file static_inst.cc.

References MipsISA::pc.

Referenced by Minor::Scoreboard::canInstIssue(), Minor::FUPipeline::findTiming(), X86ISA::PageFault::invoke(), Minor::MinorDynInst::minorTraceInst(), Trace::TarmacParserRecord::printMismatchHeader(), and Trace::ExeTracerRecord::traceInst().

◆ execute()

virtual Fault StaticInst::execute ( ExecContext xc,
Trace::InstRecord traceData 
) const
pure virtual

◆ fetchMicroop()

StaticInstPtr StaticInst::fetchMicroop ( MicroPC  upc) const
virtual

Return the microop that goes with a particular micropc.

This should only be defined/used in macroops which will contain microops

Reimplemented in RiscvISA::RiscvMacroInst, SparcISA::SparcMacroInst, ArmISA::PredMacroOp, ArmISA::Memory, ArmISA::SrsOp, ArmISA::Memory64, ArmISA::RfeOp, and X86ISA::MacroopBase.

Definition at line 98 of file static_inst.cc.

References panic.

Referenced by Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseSimpleCPU::preExecute(), and Checker< O3CPUImpl >::verify().

◆ generateDisassembly()

virtual std::string StaticInst::generateDisassembly ( Addr  pc,
const Loader::SymbolTable symtab 
) const
protectedpure virtual

Internal function to generate disassembly string.

Implemented in ArmISA::FpRegRegRegImmOp, ArmISA::FpRegRegRegRegOp, ArmISA::FpRegRegRegCondOp, ArmISA::FpRegRegRegOp, ArmISA::FpRegRegImmOp, ArmISA::FpRegImmOp, ArmISA::FpRegRegOp, ArmISA::FpCondSelOp, ArmISA::SveComplexIdxOp, ArmISA::FpCondCompRegOp, ArmISA::SveComplexOp, ArmISA::SveDotProdOp, ArmISA::SveDotProdIdxOp, ArmISA::SveUnarySca2VecUnpredOp, ArmISA::SveBinImmIdxUnpredOp, ArmISA::SveBinImmUnpredDestrOp, ArmISA::SveWImplicitSrcDstOp, ArmISA::SvePredUnaryWImplicitDstOp, ArmISA::SvePredUnaryWImplicitSrcPredOp, ArmISA::SvePredUnaryWImplicitSrcOp, ArmISA::SvePredTestOp, ArmISA::SveUnpackOp, ArmISA::SveTblOp, ArmISA::SveUnaryPredPredOp, ArmISA::SveSelectOp, ArmISA::SvePartBrkPropOp, ArmISA::SvePartBrkOp, ArmISA::SveElemCountOp, ArmISA::SveAdrOp, ArmISA::SveIntCmpImmOp, ArmISA::SveIntCmpOp, ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::SvePtrueOp, ArmISA::SveOrdReducOp, ArmISA::SveReducOp, ArmISA::SveTerImmUnpredOp, ArmISA::SveTerPredOp, McrMrcImplDefined, ArmISA::SveCmpImmOp, ArmISA::MicroMemPairOp, McrMrcMiscInst, ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::SveCmpOp, ArmISA::MicroMemOp, ArmISA::SvePredBinPermOp, UnknownOp, ArmISA::SvePredLogicalOp, RegImmRegShiftOp, ArmISA::PredMacroOp, ArmISA::SveBinIdxUnpredOp, ArmISA::MicroIntRegXOp, RegRegImmImmOp, ArmISA::SveBinUnpredOp, ArmISA::MicroIntOp, RegImmImmOp, ArmISA::SveBinConstrPredOp, ArmISA::DataRegRegOp, RegMiscRegImmOp, ArmISA::MicroIntImmXOp, ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::SveBinDestrPredOp, ArmISA::DataRegOp, ArmISA::MicroIntImmOp, MiscRegRegImmOp, ArmISA::SveBinWideImmUnpredOp, ArmISA::DataImmOp, RegRegImmOp, ArmISA::MicroIntMov, ArmISA::SveBinImmPredOp, ArmISA::PredIntOp, RegRegRegOp, ArmISA::SveBinImmUnpredConstrOp, ArmISA::MicroSetPCCPSR, ArmISA::DataXCondSelOp, ArmISA::MemoryLiteral64, PowerISA::BranchRegCond, ArmISA::PredImmOp, RegRegRegRegOp, ArmISA::SveUnaryWideImmPredOp, ArmISA::MemoryEx64, ArmISA::DataXCondCompRegOp, ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::MemoryRaw64, MiscRegImplDefined64, PowerISA::BranchNonPCRelCond, RegRegRegImmOp, ArmISA::SveUnaryWideImmUnpredOp, ArmISA::DataXCondCompImmOp, ArmISA::MemoryReg64, ArmISA::BranchImmImmReg64, ArmISA::SveUnaryUnpredOp, RegImmRegOp, ArmISA::DataX3RegOp, RegMiscRegImmOp64, ArmISA::MemoryPostIndex64, PowerISA::BranchPCRelCond, ArmISA::ArmStaticInst, ArmISA::SveUnaryPredOp, ArmISA::DataX2RegImmOp, RegOp, ArmISA::MemoryPreIndex64, ArmISA::BranchImmReg64, MiscRegRegImmOp64, ArmISA::SveCompTermOp, RegRegOp, ArmISA::MemoryDImmEx64, ArmISA::DataX2RegOp, PowerISA::IntRotateOp, MiscRegImmOp64, ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::SveWhileOp, ArmISA::BranchEretA64, RegImmOp, ArmISA::DataX1Reg2ImmOp, ArmISA::MemoryDImm64, ArmISA::SvePredCountPredOp, ArmISA::SrsOp, ArmISA::BranchEret64, ArmISA::SveContigMemSI, X86ISA::LdStSplitOp, ImmOp, PowerISA::FloatOp, ArmISA::MemoryImm64, ArmISA::DataX1RegImmOp, ArmISA::BranchRetA64, PowerISA::IntShiftOp, ArmISA::SvePredCountOp, McrrOp, ArmISA::DataX1RegOp, X86ISA::MediaOpImm, ArmISA::BranchRet64, SparcISA::SetHi, ArmISA::SveContigMemSS, PowerISA::BranchNonPCRel, ArmISA::BranchRegReg, X86ISA::RegOpImm, ArmISA::SveIndexRROp, WarnUnimplemented, PowerISA::IntImmOp, X86ISA::LdStOp, ArmISA::DataXERegOp, MrrcOp, RiscvISA::AtomicMemOpMicro, X86ISA::X86MicroopBase, ArmISA::BranchReg64, SparcISA::BranchImm13, ArmISA::RfeOp, SparcISA::WarnUnimplemented, UnknownOp64, X86ISA::MediaOpReg, SparcISA::WrPrivImm, RiscvISA::AtomicMemOp, ArmISA::SveIndexRIOp, RiscvISA::CSROp, ArmISA::BranchRegReg64, ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::SveMemPredFillSpill, X86ISA::RegOp, ArmISA::DataXSRegOp, MsrRegOp, RegRegRegImmOp64, RiscvISA::StoreCondMicro, PowerISA::BranchPCRel, PowerISA::IntOp, SparcISA::SparcStaticInst, ArmISA::BranchReg, X86ISA::X86StaticInst, FailUnimplemented, X86ISA::MacroopBase, ArmISA::SveIndexIROp, RiscvISA::StoreCond, SparcISA::BlockMemImmMicro, MsrImmOp, PowerISA::CondMoveOp, ArmISA::BranchImmCond64, RiscvISA::SystemOp, X86ISA::FpOp, SparcISA::WrPriv, ArmISA::DataXImmOnlyOp, PowerISA::MemDispOp, RegRegImmImmOp64, RiscvISA::LoadReservedMicro, SparcISA::IntOpImm, SparcISA::FailUnimplemented, ArmISA::SveMemVecFillSpill, ArmISA::SveIndexIIOp, SparcISA::FpUnimpl, RiscvISA::Store, SparcISA::BlockMemMicro, SparcISA::MemImm, SparcISA::RdPriv, SparcISA::BranchDisp, RiscvISA::Unknown, ArmISA::BranchImm64, ArmISA::SysDC64, RiscvISA::LoadReserved, PowerISA::PowerStaticInst, SparcISA::Nop, ArmISA::BranchImm, ArmISA::DataXImmOp, DecoderFaultInst, PowerISA::CondLogicOp, RiscvISA::Load, SparcISA::SparcMacroInst, SparcISA::Trap, SparcISA::Unknown, PowerISA::MemOp, MrsOp, ImmOp64, RiscvISA::MemFenceMicro, RiscvISA::RegOp, SparcISA::Branch, SparcISA::IntOp, SparcISA::Mem, RiscvISA::CompRegOp, PowerISA::MiscOp, SparcISA::Priv, RiscvISA::PseudoOp, RegNone, ArmISAInst::TmeRegNone64, ArmISAInst::TmeImmOp64, and ArmISAInst::MicroTmeBasic64.

◆ getName()

std::string StaticInst::getName ( )
inline

Return name of machine instruction.

Definition at line 350 of file static_inst.hh.

References mnemonic.

Referenced by Minor::operator<<(), and BaseSimpleCPU::preExecute().

◆ hasBranchTarget()

bool StaticInst::hasBranchTarget ( const TheISA::PCState &  pc,
ThreadContext tc,
TheISA::PCState &  tgt 
) const

Return true if the instruction is a control transfer, and if so, return the target address as well.

Definition at line 81 of file static_inst.cc.

References MipsISA::pc.

◆ initiateAcc()

virtual Fault StaticInst::initiateAcc ( ExecContext xc,
Trace::InstRecord traceData 
) const
inlinevirtual

◆ isAtomic()

bool StaticInst::isAtomic ( ) const
inline

◆ isCall()

bool StaticInst::isCall ( ) const
inline

◆ isCC()

bool StaticInst::isCC ( ) const
inline

Definition at line 173 of file static_inst.hh.

References flags.

◆ isCondCtrl()

bool StaticInst::isCondCtrl ( ) const
inline

◆ isCondDelaySlot()

bool StaticInst::isCondDelaySlot ( ) const
inline

Definition at line 182 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isCondDelaySlot().

◆ isControl()

bool StaticInst::isControl ( ) const
inline

◆ isDataPrefetch()

bool StaticInst::isDataPrefetch ( ) const
inline

Definition at line 166 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isDataPrefetch(), and isPrefetch().

◆ isDelayedCommit()

bool StaticInst::isDelayedCommit ( ) const
inline

◆ isDirectCtrl()

bool StaticInst::isDirectCtrl ( ) const
inline

◆ isFirstMicroop()

bool StaticInst::isFirstMicroop ( ) const
inline

◆ isFloating()

bool StaticInst::isFloating ( ) const
inline

◆ isHtmCancel()

bool StaticInst::isHtmCancel ( ) const
inline

Definition at line 210 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isHtmCancel(), and isHtmCmd().

◆ isHtmCmd()

bool StaticInst::isHtmCmd ( ) const
inline

Definition at line 213 of file static_inst.hh.

References isHtmCancel(), isHtmStart(), and isHtmStop().

Referenced by BaseDynInst< Impl >::isHtmCmd().

◆ isHtmStart()

bool StaticInst::isHtmStart ( ) const
inline

Definition at line 208 of file static_inst.hh.

References flags.

Referenced by TimingSimpleCPU::completeIfetch(), isHtmCmd(), and BaseDynInst< Impl >::isHtmStart().

◆ isHtmStop()

bool StaticInst::isHtmStop ( ) const
inline

Definition at line 209 of file static_inst.hh.

References flags.

Referenced by TimingSimpleCPU::completeDataAccess(), isHtmCmd(), and BaseDynInst< Impl >::isHtmStop().

◆ isIndirectCtrl()

bool StaticInst::isIndirectCtrl ( ) const
inline

Definition at line 179 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isIndirectCtrl().

◆ isInstPrefetch()

bool StaticInst::isInstPrefetch ( ) const
inline

Definition at line 165 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isInstPrefetch(), and isPrefetch().

◆ isInteger()

bool StaticInst::isInteger ( ) const
inline

◆ isIprAccess()

bool StaticInst::isIprAccess ( ) const
inline

Definition at line 195 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isIprAccess().

◆ isLastMicroop()

bool StaticInst::isLastMicroop ( ) const
inline

◆ isLoad()

bool StaticInst::isLoad ( ) const
inline

◆ isMacroop()

bool StaticInst::isMacroop ( ) const
inline

◆ isMemBarrier()

bool StaticInst::isMemBarrier ( ) const
inline

Definition at line 191 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isMemBarrier().

◆ isMemRef()

bool StaticInst::isMemRef ( ) const
inline

◆ isMicroBranch()

bool StaticInst::isMicroBranch ( ) const
inline

Definition at line 204 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isMicroBranch().

◆ isMicroop()

bool StaticInst::isMicroop ( ) const
inline

◆ isNonSpeculative()

bool StaticInst::isNonSpeculative ( ) const
inline

Definition at line 193 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isNonSpeculative().

◆ isNop()

bool StaticInst::isNop ( ) const
inline

Definition at line 158 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isNop().

◆ isPrefetch()

bool StaticInst::isPrefetch ( ) const
inline

Definition at line 167 of file static_inst.hh.

References isDataPrefetch(), and isInstPrefetch().

◆ isQuiesce()

bool StaticInst::isQuiesce ( ) const
inline

Definition at line 194 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isQuiesce().

◆ isReturn()

bool StaticInst::isReturn ( ) const
inline

◆ isSerializeAfter()

bool StaticInst::isSerializeAfter ( ) const
inline

Definition at line 189 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializeAfter().

◆ isSerializeBefore()

bool StaticInst::isSerializeBefore ( ) const
inline

Definition at line 188 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializeBefore().

◆ isSerializing()

bool StaticInst::isSerializing ( ) const
inline

Definition at line 185 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializing().

◆ isSquashAfter()

bool StaticInst::isSquashAfter ( ) const
inline

Definition at line 190 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSquashAfter().

◆ isStore()

bool StaticInst::isStore ( ) const
inline

◆ isStoreConditional()

bool StaticInst::isStoreConditional ( ) const
inline

Definition at line 164 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isStoreConditional().

◆ isSyscall()

bool StaticInst::isSyscall ( ) const
inline

Definition at line 197 of file static_inst.hh.

References flags.

Referenced by Trace::X86NativeTrace::check(), and BaseDynInst< Impl >::isSyscall().

◆ isThreadSync()

bool StaticInst::isThreadSync ( ) const
inline

Definition at line 184 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isThreadSync().

◆ isUncondCtrl()

bool StaticInst::isUncondCtrl ( ) const
inline

◆ isUnverifiable()

bool StaticInst::isUnverifiable ( ) const
inline

Definition at line 196 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isUnverifiable().

◆ isVector()

bool StaticInst::isVector ( ) const
inline

◆ isWriteBarrier()

bool StaticInst::isWriteBarrier ( ) const
inline

Definition at line 192 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isWriteBarrier().

◆ numCCDestRegs()

int8_t StaticInst::numCCDestRegs ( ) const
inline

Number of coprocesor destination regs.

Definition at line 149 of file static_inst.hh.

References _numCCDestRegs.

Referenced by BaseDynInst< Impl >::numCCDestRegs().

◆ numDestRegs()

int8_t StaticInst::numDestRegs ( ) const
inline

◆ numFPDestRegs()

int8_t StaticInst::numFPDestRegs ( ) const
inline

Number of floating-point destination regs.

Definition at line 139 of file static_inst.hh.

References _numFPDestRegs.

Referenced by BaseDynInst< Impl >::numFPDestRegs().

◆ numIntDestRegs()

int8_t StaticInst::numIntDestRegs ( ) const
inline

Number of integer destination regs.

Definition at line 141 of file static_inst.hh.

References _numIntDestRegs.

Referenced by BaseDynInst< Impl >::numIntDestRegs().

◆ numSrcRegs()

int8_t StaticInst::numSrcRegs ( ) const
inline

◆ numVecDestRegs()

int8_t StaticInst::numVecDestRegs ( ) const
inline

Number of vector destination regs.

Definition at line 143 of file static_inst.hh.

References _numVecDestRegs.

Referenced by BaseDynInst< Impl >::numVecDestRegs().

◆ numVecElemDestRegs()

int8_t StaticInst::numVecElemDestRegs ( ) const
inline

Number of vector element destination regs.

Definition at line 145 of file static_inst.hh.

References _numVecElemDestRegs.

Referenced by BaseDynInst< Impl >::numVecElemDestRegs().

◆ numVecPredDestRegs()

int8_t StaticInst::numVecPredDestRegs ( ) const
inline

Number of predicate destination regs.

Definition at line 147 of file static_inst.hh.

References _numVecPredDestRegs.

Referenced by BaseDynInst< Impl >::numVecPredDestRegs().

◆ opClass()

OpClass StaticInst::opClass ( ) const
inline

◆ printFlags()

void StaticInst::printFlags ( std::ostream &  outs,
const std::string &  separator 
) const

Print a separator separated list of this instruction's set flag names on the given stream.

Definition at line 130 of file static_inst.cc.

Referenced by Minor::MinorDynInst::minorTraceInst(), and Trace::ExeTracerRecord::traceInst().

◆ setDelayedCommit()

void StaticInst::setDelayedCommit ( )
inline

◆ setFirstMicroop()

void StaticInst::setFirstMicroop ( )
inline

◆ setFlag()

void StaticInst::setFlag ( Flags  f)
inline

Definition at line 222 of file static_inst.hh.

References ArmISA::f, and flags.

Referenced by ArmISA::MacroMemOp::MacroMemOp().

◆ setLastMicroop()

void StaticInst::setLastMicroop ( )
inline

◆ simpleAsBytes()

template<typename T >
size_t StaticInst::simpleAsBytes ( void *  buf,
size_t  max_size,
const T &  t 
)
inlineprotected

◆ srcRegIdx()

const RegId& StaticInst::srcRegIdx ( int  i) const
inline

Return logical index (architectural reg num) of i'th source reg.

Only the entries from 0 through numSrcRegs()-1 are valid.

Definition at line 234 of file static_inst.hh.

References _srcRegIdx, and ArmISA::i.

Referenced by Minor::Scoreboard::canInstIssue(), TimingExprSrcReg::eval(), Minor::Scoreboard::execSeqNumToWaitFor(), Minor::MinorDynInst::minorTraceInst(), and BaseDynInst< Impl >::srcRegIdx().

Member Data Documentation

◆ _destRegIdx

RegId StaticInst::_destRegIdx[MaxInstDestRegs]
protected

◆ _numCCDestRegs

int8_t StaticInst::_numCCDestRegs
protected

◆ _numDestRegs

int8_t StaticInst::_numDestRegs
protected

◆ _numFPDestRegs

int8_t StaticInst::_numFPDestRegs
protected

◆ _numIntDestRegs

int8_t StaticInst::_numIntDestRegs
protected

◆ _numSrcRegs

int8_t StaticInst::_numSrcRegs
protected

◆ _numVecDestRegs

int8_t StaticInst::_numVecDestRegs
protected

◆ _numVecElemDestRegs

int8_t StaticInst::_numVecElemDestRegs
protected

◆ _numVecPredDestRegs

int8_t StaticInst::_numVecPredDestRegs
protected

Definition at line 122 of file static_inst.hh.

Referenced by numVecPredDestRegs().

◆ _opClass

OpClass StaticInst::_opClass
protected

See opClass().

Definition at line 102 of file static_inst.hh.

Referenced by opClass().

◆ _srcRegIdx

RegId StaticInst::_srcRegIdx[MaxInstSrcRegs]
protected

◆ cachedDisassembly

std::string* StaticInst::cachedDisassembly
mutableprotected

String representation of disassembly (lazily evaluated via disassemble()).

Definition at line 264 of file static_inst.hh.

Referenced by PowerISA::PCDependentDisassembly::disassemble().

◆ flags

std::bitset<Num_Flags> StaticInst::flags
protected

Flag values for this instruction.

Definition at line 99 of file static_inst.hh.

Referenced by ArmISA::MightBeMicro::advancePC(), ArmISA::MicroOp::advancePC(), ArmISA::MightBeMicro64::advancePC(), ArmISA::MicroOpX::advancePC(), SparcISA::SparcMicroInst::advancePC(), RiscvISA::RiscvMicroInst::advancePC(), X86ISA::X86MicroopBase::advancePC(), ArmISA::PredMicroop::advancePC(), ArmISA::FpOp::advancePC(), X86ISA::X86MicroopBase::checkCondition(), DecoderFaultInst::DecoderFaultInst(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), SparcISA::Mem::generateDisassembly(), SparcISA::BlockMemMicro::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), SparcISA::BlockMemImmMicro::generateDisassembly(), X86ISA::LdStOp::generateDisassembly(), X86ISA::LdStSplitOp::generateDisassembly(), X86ISA::RegOpBase::genFlags(), isAtomic(), isCall(), isCC(), isCondCtrl(), isCondDelaySlot(), isControl(), isDataPrefetch(), isDelayedCommit(), isDirectCtrl(), isFirstMicroop(), isFloating(), isHtmCancel(), isHtmStart(), isHtmStop(), isIndirectCtrl(), isInstPrefetch(), isInteger(), isIprAccess(), isLastMicroop(), isLoad(), isMacroop(), isMemBarrier(), isMemRef(), isMicroBranch(), isMicroop(), isNonSpeculative(), isNop(), isQuiesce(), isReturn(), isSerializeAfter(), isSerializeBefore(), isSerializing(), isSquashAfter(), isStore(), isStoreConditional(), isSyscall(), isThreadSync(), isUncondCtrl(), isUnverifiable(), isVector(), isWriteBarrier(), X86ISA::MacroopBase::MacroopBase(), McrMrcMiscInst::McrMrcMiscInst(), ArmISAInst::MicroTcommit64::MicroTcommit64(), ArmISAInst::MicroTfence64::MicroTfence64(), SparcISA::Nop::Nop(), ArmISA::PredMacroOp::PredMacroOp(), ArmISA::PredMicroop::PredMicroop(), RiscvISA::RiscvMacroInst::RiscvMacroInst(), RiscvISA::RiscvMicroInst::RiscvMicroInst(), setDelayedCommit(), setFirstMicroop(), setFlag(), setLastMicroop(), SparcISA::SparcDelayedMicroInst::SparcDelayedMicroInst(), SparcISA::SparcMacroInst::SparcMacroInst(), SparcISA::SparcMicroInst::SparcMicroInst(), ArmISAInst::Tcancel64::Tcancel64(), ArmISAInst::Tstart64::Tstart64(), ArmISAInst::Ttest64::Ttest64(), and X86ISA::X86MicroopBase::X86MicroopBase().

◆ machInst

const ExtMachInst StaticInst::machInst

The binary machine instruction.

Definition at line 243 of file static_inst.hh.

Referenced by ArmISA::ArmStaticInst::advSIMDFPAccessTrap64(), ArmISA::ArmStaticInst::ArmStaticInst(), RiscvISA::RiscvStaticInst::asBytes(), PowerISA::PowerStaticInst::asBytes(), SparcISA::SparcStaticInst::asBytes(), ArmISA::ArmStaticInst::asBytes(), ArmISA::BigFpMemImmOp::BigFpMemImmOp(), ArmISA::BigFpMemLitOp::BigFpMemLitOp(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), ArmISA::BigFpMemRegOp::BigFpMemRegOp(), ArmISA::BranchImmCond::BranchImmCond(), ArmISA::BranchRegCond::BranchRegCond(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::ArmStaticInst::checkForWFxTrap32(), ArmISA::ArmStaticInst::checkForWFxTrap64(), ArmISA::ArmStaticInst::disabledFault(), ArmISA::ArmStaticInst::encoding(), DecoderFaultInst::execute(), RiscvISA::Unknown::execute(), SparcISA::FailUnimplemented::execute(), FailUnimplemented::execute(), DebugStep::execute(), MiscRegImplDefined64::execute(), McrMrcMiscInst::execute(), McrMrcImplDefined::execute(), Minor::FUPipeline::findTiming(), ArmISA::PredImmOp::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), X86ISA::MacroopBase::getExtMachInst(), ArmISA::ArmStaticInst::instSize(), X86ISA::InvalidOpcode::invoke(), RiscvISA::UnknownInstFault::invokeSE(), RiscvISA::IllegalInstFault::invokeSE(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), Minor::MinorDynInst::minorTraceInst(), ArmISA::VfpMacroOp::nextIdxs(), ArmISA::PairMemOp::PairMemOp(), ArmISA::PredOp::PredOp(), BaseSimpleCPU::preExecute(), Trace::TarmacParserRecord::printMismatchHeader(), ArmISA::ArmStaticInst::printMnemonic(), ArmISA::ArmStaticInst::softwareBreakpoint32(), ArmISA::ArmStaticInst::sveAccessTrap(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), ArmISA::ArmStaticInst::undefinedFault32(), ArmISA::ArmStaticInst::undefinedFault64(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

◆ mnemonic

const char* StaticInst::mnemonic
protected

Base mnemonic (e.g., "add").

Used by generateDisassembly() methods. Also useful to readily identify instructions from within the debugger when cachedDisassembly has not been initialized.

Definition at line 258 of file static_inst.hh.

Referenced by ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::ArmStaticInst::checkForWFxTrap32(), ArmISA::ArmStaticInst::disabledFault(), SparcISA::FailUnimplemented::execute(), FailUnimplemented::execute(), SparcISA::WarnUnimplemented::execute(), WarnUnimplemented::execute(), MiscRegImplDefined64::execute(), McrMrcImplDefined::execute(), RiscvISA::PseudoOp::generateDisassembly(), PowerISA::MiscOp::generateDisassembly(), SparcISA::Priv::generateDisassembly(), RiscvISA::CompRegOp::generateDisassembly(), SparcISA::Mem::generateDisassembly(), SparcISA::IntOp::generateDisassembly(), SparcISA::Branch::generateDisassembly(), PowerISA::MemOp::generateDisassembly(), SparcISA::Trap::generateDisassembly(), PowerISA::CondLogicOp::generateDisassembly(), SparcISA::SparcMacroInst::generateDisassembly(), SparcISA::Nop::generateDisassembly(), PowerISA::PowerStaticInst::generateDisassembly(), SparcISA::BranchDisp::generateDisassembly(), SparcISA::BlockMemMicro::generateDisassembly(), SparcISA::RdPriv::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), SparcISA::FpUnimpl::generateDisassembly(), SparcISA::FailUnimplemented::generateDisassembly(), SparcISA::IntOpImm::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), SparcISA::WrPriv::generateDisassembly(), X86ISA::FpOp::generateDisassembly(), PowerISA::CondMoveOp::generateDisassembly(), SparcISA::BlockMemImmMicro::generateDisassembly(), FailUnimplemented::generateDisassembly(), X86ISA::MacroopBase::generateDisassembly(), X86ISA::X86StaticInst::generateDisassembly(), PowerISA::BranchPCRel::generateDisassembly(), SparcISA::SparcStaticInst::generateDisassembly(), X86ISA::RegOp::generateDisassembly(), SparcISA::WrPrivImm::generateDisassembly(), X86ISA::MediaOpReg::generateDisassembly(), SparcISA::WarnUnimplemented::generateDisassembly(), SparcISA::BranchImm13::generateDisassembly(), X86ISA::X86MicroopBase::generateDisassembly(), X86ISA::LdStOp::generateDisassembly(), WarnUnimplemented::generateDisassembly(), X86ISA::RegOpImm::generateDisassembly(), PowerISA::BranchNonPCRel::generateDisassembly(), SparcISA::SetHi::generateDisassembly(), X86ISA::MediaOpImm::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), X86ISA::LdStSplitOp::generateDisassembly(), PowerISA::BranchPCRelCond::generateDisassembly(), PowerISA::BranchNonPCRelCond::generateDisassembly(), PowerISA::BranchRegCond::generateDisassembly(), ArmISA::PredMacroOp::generateDisassembly(), McrMrcMiscInst::generateDisassembly(), McrMrcImplDefined::generateDisassembly(), ArmISA::SveElemCountOp::generateDisassembly(), getName(), X86ISA::X86StaticInst::printMnemonic(), SparcISA::SparcStaticInst::printMnemonic(), ArmISA::ArmStaticInst::printMnemonic(), SparcISA::IntOp::printPseudoOps(), SparcISA::IntOpImm::printPseudoOps(), and ArmISA::ArmStaticInst::undefinedFault32().

◆ nopStaticInstPtr

StaticInstPtr StaticInst::nopStaticInstPtr = new NopStaticInst
static

Pointer to a statically allocated generic "nop" instruction object.

Definition at line 240 of file static_inst.hh.

Referenced by DefaultFetch< Impl >::finishTranslation().

◆ nullStaticInstPtr

StaticInstPtr StaticInst::nullStaticInstPtr
static

The documentation for this class was generated from the following files:

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