gem5  v20.1.0.0
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ArmISA::ArmStaticInst Class Reference

#include <static_inst.hh>

Inheritance diagram for ArmISA::ArmStaticInst:
StaticInst RefCounted ArmISA::BranchEret64 ArmISA::BranchEretA64 ArmISA::BranchImm64 ArmISA::BranchImmImmReg64 ArmISA::BranchImmReg64 ArmISA::BranchReg64 ArmISA::BranchRegReg64 ArmISA::DataX1Reg2ImmOp ArmISA::DataX1RegImmOp ArmISA::DataX1RegOp ArmISA::DataX2RegImmOp ArmISA::DataX2RegOp ArmISA::DataX3RegOp ArmISA::DataXCondCompImmOp ArmISA::DataXCondCompRegOp ArmISA::DataXCondSelOp ArmISA::DataXERegOp ArmISA::DataXImmOnlyOp ArmISA::DataXImmOp ArmISA::DataXSRegOp ArmISA::MicroOpX ArmISA::MightBeMicro64 ArmISA::PredOp ArmISA::SveAdrOp ArmISA::SveBinConstrPredOp ArmISA::SveBinDestrPredOp ArmISA::SveBinIdxUnpredOp ArmISA::SveBinImmIdxUnpredOp ArmISA::SveBinImmPredOp ArmISA::SveBinImmUnpredConstrOp ArmISA::SveBinImmUnpredDestrOp ArmISA::SveBinUnpredOp ArmISA::SveBinWideImmUnpredOp ArmISA::SveCmpImmOp ArmISA::SveCmpOp ArmISA::SveComplexIdxOp ArmISA::SveComplexOp ArmISA::SveCompTermOp ArmISA::SveContigMemSI ArmISA::SveContigMemSS ArmISA::SveDotProdIdxOp ArmISA::SveDotProdOp ArmISA::SveElemCountOp ArmISA::SveIndexIIOp ArmISA::SveIndexIROp ArmISA::SveIndexRIOp ArmISA::SveIndexRROp ArmISA::SveIntCmpImmOp ArmISA::SveIntCmpOp ArmISA::SveMemPredFillSpill ArmISA::SveMemVecFillSpill ArmISA::SveOrdReducOp ArmISA::SvePartBrkOp ArmISA::SvePartBrkPropOp ArmISA::SvePredBinPermOp ArmISA::SvePredCountOp ArmISA::SvePredCountPredOp ArmISA::SvePredLogicalOp ArmISA::SvePredTestOp ArmISA::SvePredUnaryWImplicitDstOp ArmISA::SvePredUnaryWImplicitSrcOp ArmISA::SvePredUnaryWImplicitSrcPredOp ArmISA::SvePtrueOp ArmISA::SveReducOp ArmISA::SveSelectOp ArmISA::SveTblOp ArmISA::SveTerImmUnpredOp ArmISA::SveTerPredOp ArmISA::SveUnaryPredOp ArmISA::SveUnaryPredPredOp ArmISA::SveUnarySca2VecUnpredOp ArmISA::SveUnaryUnpredOp ArmISA::SveUnaryWideImmPredOp ArmISA::SveUnaryWideImmUnpredOp ArmISA::SveUnpackOp ArmISA::SveWhileOp ArmISA::SveWImplicitSrcDstOp ArmISAInst::TmeImmOp64 ArmISAInst::TmeRegNone64 DebugStep DecoderFaultInst FailUnimplemented IllegalExecInst ImmOp64 McrMrcMiscInst MiscRegOp64 RegNone RegRegImmImmOp64 RegRegRegImmOp64 UnknownOp64 WarnUnimplemented

Public Member Functions

virtual void annotateFault (ArmFault *fault)
 
uint8_t getIntWidth () const
 
ssize_t instSize () const
 Returns the byte size of current instruction. More...
 
MachInst encoding () const
 Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode. More...
 
size_t asBytes (void *buf, size_t max_size) override
 Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More...
 
- Public Member Functions inherited from StaticInst
int8_t numSrcRegs () const
 Number of source registers. More...
 
int8_t numDestRegs () const
 Number of destination registers. More...
 
int8_t numFPDestRegs () const
 Number of floating-point destination regs. More...
 
int8_t numIntDestRegs () const
 Number of integer destination regs. More...
 
int8_t numVecDestRegs () const
 Number of vector destination regs. More...
 
int8_t numVecElemDestRegs () const
 Number of vector element destination regs. More...
 
int8_t numVecPredDestRegs () const
 Number of predicate destination regs. More...
 
int8_t numCCDestRegs () const
 Number of coprocesor destination regs. More...
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isVector () const
 
bool isCC () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isCondDelaySlot () const
 
bool isThreadSync () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isMemBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isIprAccess () const
 
bool isUnverifiable () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isMicroBranch () const
 
bool isHtmStart () const
 
bool isHtmStop () const
 
bool isHtmCancel () const
 
bool isHtmCmd () const
 
void setFirstMicroop ()
 
void setLastMicroop ()
 
void setDelayedCommit ()
 
void setFlag (Flags f)
 
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue. More...
 
const RegIddestRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg. More...
 
const RegIdsrcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg. More...
 
virtual ~StaticInst ()
 
virtual Fault execute (ExecContext *xc, Trace::InstRecord *traceData) const =0
 
virtual Fault initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual void advancePC (TheISA::PCState &pcState) const =0
 
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc. More...
 
virtual TheISA::PCState branchTarget (const TheISA::PCState &pc) const
 Return the target address for a PC-relative branch. More...
 
virtual TheISA::PCState branchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump). More...
 
bool hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
 Return true if the instruction is a control transfer, and if so, return the target address as well. More...
 
virtual const std::string & disassemble (Addr pc, const Loader::SymbolTable *symtab=nullptr) const
 Return string representation of disassembled instruction. More...
 
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream. More...
 
std::string getName ()
 Return name of machine instruction. More...
 
- Public Member Functions inherited from RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
 
void incref () const
 Increment the reference count. More...
 
void decref () const
 Decrement the reference count and destroy the object if all references are gone. More...
 

Static Public Member Functions

static unsigned getCurSveVecLenInBits (ThreadContext *tc)
 
static unsigned getCurSveVecLenInQWords (ThreadContext *tc)
 
template<typename T >
static unsigned getCurSveVecLen (ThreadContext *tc)
 

Protected Member Functions

int32_t shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
int32_t shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
bool shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
bool shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
int64_t shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const
 
int64_t extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const
 
 ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 
void printIntReg (std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
 Print a register name for disassembly given the unique dependence tag number (FP or int). More...
 
void printFloatReg (std::ostream &os, RegIndex reg_idx) const
 
void printVecReg (std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
 
void printVecPredReg (std::ostream &os, RegIndex reg_idx) const
 
void printCCReg (std::ostream &os, RegIndex reg_idx) const
 
void printMiscReg (std::ostream &os, RegIndex reg_idx) const
 
void printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
 
void printTarget (std::ostream &os, Addr target, const Loader::SymbolTable *symtab) const
 
void printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const
 
void printMemSymbol (std::ostream &os, const Loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const
 
void printShiftOperand (std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const
 
void printExtendOperand (bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const
 
void printPFflags (std::ostream &os, int flag) const
 
void printDataInst (std::ostream &os, bool withImm) const
 
void printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const
 
void advancePC (PCState &pcState) const override
 
std::string generateDisassembly (Addr pc, const Loader::SymbolTable *symtab) const override
 Internal function to generate disassembly string. More...
 
Fault disabledFault () const
 
bool isWFxTrapping (ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const
 
Fault softwareBreakpoint32 (ExecContext *xc, uint16_t imm) const
 Trigger a Software Breakpoint. More...
 
Fault advSIMDFPAccessTrap64 (ExceptionLevel el) const
 Trap an access to Advanced SIMD or FP registers due to access control bits. More...
 
Fault checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const
 Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. More...
 
Fault checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
 Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...
 
Fault checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
 Check if a VFP/SIMD access from aarch32 should be allowed. More...
 
Fault checkForWFxTrap32 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
 Check if WFE/WFI instruction execution in aarch32 should be trapped. More...
 
Fault checkForWFxTrap64 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
 Check if WFE/WFI instruction execution in aarch64 should be trapped. More...
 
Fault trapWFx (ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
 WFE/WFI trapping helper function. More...
 
Fault checkSETENDEnabled (ThreadContext *tc, CPSR cpsr) const
 Check if SETEND instruction execution in aarch32 should be trapped. More...
 
Fault undefinedFault32 (ThreadContext *tc, ExceptionLevel el) const
 UNDEFINED behaviour in AArch32. More...
 
Fault undefinedFault64 (ThreadContext *tc, ExceptionLevel el) const
 UNDEFINED behaviour in AArch64. More...
 
Fault sveAccessTrap (ExceptionLevel el) const
 Trap an access to SVE registers due to access control bits. More...
 
Fault checkSveEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
 Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...
 
CPSR getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const
 Get the new PSTATE from a SPSR register in preparation for an exception return. More...
 
bool generalExceptionsToAArch64 (ThreadContext *tc, ExceptionLevel pstateEL) const
 Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64. More...
 
- Protected Member Functions inherited from StaticInst
 StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 Constructor. More...
 
template<typename T >
size_t simpleAsBytes (void *buf, size_t max_size, const T &t)
 

Static Protected Member Functions

template<int width>
static bool saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false)
 
static bool satInt (int32_t &res, int64_t op, int width)
 
template<int width>
static bool uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
 
static bool uSatInt (int32_t &res, int64_t op, int width)
 
static void activateBreakpoint (ThreadContext *tc)
 
static uint32_t cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
 
static uint32_t spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)
 
static Addr readPC (ExecContext *xc)
 
static void setNextPC (ExecContext *xc, Addr val)
 
template<class T >
static T cSwap (T val, bool big)
 
template<class T , class E >
static T cSwap (T val, bool big)
 
static void setIWNextPC (ExecContext *xc, Addr val)
 
static void setAIWNextPC (ExecContext *xc, Addr val)
 

Protected Attributes

bool aarch64
 
uint8_t intWidth
 
- Protected Attributes inherited from StaticInst
std::bitset< Num_Flags > flags
 Flag values for this instruction. More...
 
OpClass _opClass
 See opClass(). More...
 
int8_t _numSrcRegs
 See numSrcRegs(). More...
 
int8_t _numDestRegs
 See numDestRegs(). More...
 
int8_t _numFPDestRegs
 The following are used to track physical register usage for machines with separate int & FP reg files. More...
 
int8_t _numIntDestRegs
 
int8_t _numCCDestRegs
 
int8_t _numVecDestRegs
 To use in architectures with vector register file. More...
 
int8_t _numVecElemDestRegs
 
int8_t _numVecPredDestRegs
 
RegId _destRegIdx [MaxInstDestRegs]
 See destRegIdx(). More...
 
RegId _srcRegIdx [MaxInstSrcRegs]
 See srcRegIdx(). More...
 
const char * mnemonic
 Base mnemonic (e.g., "add"). More...
 
std::string * cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()). More...
 

Additional Inherited Members

- Public Types inherited from StaticInst
enum  { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }
 
typedef TheISA::ExtMachInst ExtMachInst
 Binary extended machine instruction type. More...
 
- Public Attributes inherited from StaticInst
const ExtMachInst machInst
 The binary machine instruction. More...
 
- Static Public Attributes inherited from StaticInst
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object. More...
 
static StaticInstPtr nopStaticInstPtr = new NopStaticInst
 Pointer to a statically allocated generic "nop" instruction object. More...
 

Detailed Description

Definition at line 60 of file static_inst.hh.

Constructor & Destructor Documentation

◆ ArmStaticInst()

ArmISA::ArmStaticInst::ArmStaticInst ( const char *  mnem,
ExtMachInst  _machInst,
OpClass  __opClass 
)
inlineprotected

Definition at line 147 of file static_inst.hh.

References aarch64, bits(), intWidth, and StaticInst::machInst.

Member Function Documentation

◆ activateBreakpoint()

static void ArmISA::ArmStaticInst::activateBreakpoint ( ThreadContext tc)
inlinestaticprotected

Definition at line 204 of file static_inst.hh.

References ArmISA::ISA::getSelfDebug(), and ArmISA::sd.

Referenced by cpsrWriteByInstr().

◆ advancePC()

void ArmISA::ArmStaticInst::advancePC ( PCState &  pcState) const
inlineoverrideprotected

Definition at line 195 of file static_inst.hh.

◆ advSIMDFPAccessTrap64()

Fault ArmISA::ArmStaticInst::advSIMDFPAccessTrap64 ( ExceptionLevel  el) const
protected

Trap an access to Advanced SIMD or FP registers due to access control bits.

See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the ARM ARM psueodcode library.

Parameters
elTarget EL for the trap

Definition at line 652 of file static_inst.cc.

References ArmISA::EC_TRAPPED_SIMD_FP, ArmISA::el, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, and panic.

Referenced by checkAdvSIMDOrFPEnabled32(), checkFPAdvSIMDEnabled64(), checkFPAdvSIMDTrap64(), and checkSveEnabled().

◆ annotateFault()

virtual void ArmISA::ArmStaticInst::annotateFault ( ArmFault fault)
inlinevirtual

Definition at line 516 of file static_inst.hh.

Referenced by ArmISA::ArmFault::instrAnnotate().

◆ asBytes()

size_t ArmISA::ArmStaticInst::asBytes ( void *  buf,
size_t  max_size 
)
inlineoverridevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented from StaticInst.

Definition at line 544 of file static_inst.hh.

References StaticInst::machInst, and StaticInst::simpleAsBytes().

◆ checkAdvSIMDOrFPEnabled32()

Fault ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32 ( ThreadContext tc,
CPSR  cpsr,
CPACR  cpacr,
NSACR  nsacr,
FPEXC  fpexc,
bool  fpexc_check,
bool  advsimd 
) const
protected

◆ checkForWFxTrap32()

Fault ArmISA::ArmStaticInst::checkForWFxTrap32 ( ThreadContext tc,
ExceptionLevel  tgtEl,
bool  isWfe 
) const
protected

Check if WFE/WFI instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 827 of file static_inst.cc.

References checkForWFxTrap64(), ArmISA::EC_TRAPPED_WFI_WFE, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs64(), ArmSystem::haveEL(), isWFxTrapping(), StaticInst::machInst, StaticInst::mnemonic, NoFault, and panic.

Referenced by trapWFx().

◆ checkForWFxTrap64()

Fault ArmISA::ArmStaticInst::checkForWFxTrap64 ( ThreadContext tc,
ExceptionLevel  tgtEl,
bool  isWfe 
) const
protected

Check if WFE/WFI instruction execution in aarch64 should be trapped.

See aarch64/exceptions/traps/AArch64.checkForWFxTrap in the ARM ARM psueodcode library.

Definition at line 867 of file static_inst.cc.

References ArmISA::EC_TRAPPED_WFI_WFE, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmSystem::haveEL(), isWFxTrapping(), StaticInst::machInst, NoFault, and panic.

Referenced by checkForWFxTrap32().

◆ checkFPAdvSIMDEnabled64()

Fault ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64 ( ThreadContext tc,
CPSR  cpsr,
CPACR  cpacr 
) const
protected

Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the ARM ARM psueodcode library.

Definition at line 711 of file static_inst.cc.

References advSIMDFPAccessTrap64(), checkFPAdvSIMDTrap64(), ArmISA::currEL(), ArmISA::el, ArmISA::EL0, and ArmISA::EL1.

Referenced by checkAdvSIMDOrFPEnabled32().

◆ checkFPAdvSIMDTrap64()

Fault ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64 ( ThreadContext tc,
CPSR  cpsr 
) const
protected

Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the ARM ARM psueodcode library.

Definition at line 672 of file static_inst.cc.

References advSIMDFPAccessTrap64(), ArmISA::currEL(), ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL2Enabled(), ArmISA::EL3, ArmSystem::haveSecurity(), ArmISA::HaveVirtHostExt(), ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_HCR_EL2, NoFault, and ThreadContext::readMiscReg().

Referenced by checkAdvSIMDOrFPEnabled32(), and checkFPAdvSIMDEnabled64().

◆ checkSETENDEnabled()

Fault ArmISA::ArmStaticInst::checkSETENDEnabled ( ThreadContext tc,
CPSR  cpsr 
) const
protected

Check if SETEND instruction execution in aarch32 should be trapped.

See aarch32/exceptions/traps/AArch32.CheckSETENDEnabled in the ARM ARM pseudocode library.

Definition at line 925 of file static_inst.cc.

References ArmISA::currEL(), ArmISA::EL2, ArmISA::isSecure(), ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_SCTLR, NoFault, ThreadContext::readMiscRegNoEffect(), ArmISA::sed, ArmISA::snsBankedIndex(), and undefinedFault32().

◆ checkSveEnabled()

Fault ArmISA::ArmStaticInst::checkSveEnabled ( ThreadContext tc,
CPSR  cpsr,
CPACR  cpacr 
) const
protected

◆ cpsrWriteByInstr()

static uint32_t ArmISA::ArmStaticInst::cpsrWriteByInstr ( CPSR  cpsr,
uint32_t  val,
SCR  scr,
NSACR  nsacr,
uint8_t  byteMask,
bool  affectState,
bool  nmfi,
ThreadContext tc 
)
inlinestaticprotected

◆ cSwap() [1/2]

template<class T >
static T ArmISA::ArmStaticInst::cSwap ( val,
bool  big 
)
inlinestaticprotected

Definition at line 324 of file static_inst.hh.

References letobe(), and X86ISA::val.

◆ cSwap() [2/2]

template<class T , class E >
static T ArmISA::ArmStaticInst::cSwap ( val,
bool  big 
)
inlinestaticprotected

Definition at line 335 of file static_inst.hh.

References RefCounted::count, X86ISA::E, htole(), ArmISA::i, letobe(), letoh(), and X86ISA::val.

◆ disabledFault()

Fault ArmISA::ArmStaticInst::disabledFault ( ) const
inlineprotected

Definition at line 375 of file static_inst.hh.

References StaticInst::machInst, and StaticInst::mnemonic.

Referenced by checkAdvSIMDOrFPEnabled32().

◆ encoding()

MachInst ArmISA::ArmStaticInst::encoding ( ) const
inline

Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode.

Definition at line 538 of file static_inst.hh.

References instSize(), StaticInst::machInst, and ArmISA::mask.

◆ extendReg64()

int64_t ArmISA::ArmStaticInst::extendReg64 ( uint64_t  base,
ArmExtendType  type,
uint64_t  shiftAmt,
uint8_t  width 
) const
protected

◆ generalExceptionsToAArch64()

bool ArmISA::ArmStaticInst::generalExceptionsToAArch64 ( ThreadContext tc,
ExceptionLevel  pstateEL 
) const
protected

Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64.

See aarch32/exceptions/exceptions/AArch32.GeneralExceptionsToAArch64 in the ARM ARM pseudocode library.

Definition at line 1203 of file static_inst.cc.

References ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::ELIs32(), ArmSystem::haveEL(), ArmISA::isSecure(), ArmISA::MISCREG_HCR_EL2, and ThreadContext::readMiscReg().

Referenced by undefinedFault32().

◆ generateDisassembly()

std::string ArmISA::ArmStaticInst::generateDisassembly ( Addr  pc,
const Loader::SymbolTable symtab 
) const
overrideprotectedvirtual

Internal function to generate disassembly string.

Implements StaticInst.

Reimplemented in ArmISA::FpRegRegRegImmOp, ArmISA::FpRegRegRegRegOp, ArmISA::FpRegRegRegCondOp, ArmISA::FpRegRegRegOp, ArmISA::FpRegRegImmOp, ArmISA::FpRegImmOp, ArmISA::FpRegRegOp, ArmISA::FpCondSelOp, ArmISA::SveComplexIdxOp, ArmISA::FpCondCompRegOp, ArmISA::SveComplexOp, ArmISA::SveDotProdOp, ArmISA::SveDotProdIdxOp, ArmISA::SveUnarySca2VecUnpredOp, ArmISA::SveBinImmIdxUnpredOp, ArmISA::SveBinImmUnpredDestrOp, ArmISA::SveWImplicitSrcDstOp, ArmISA::SvePredUnaryWImplicitDstOp, ArmISA::SvePredUnaryWImplicitSrcPredOp, ArmISA::SvePredUnaryWImplicitSrcOp, ArmISA::SvePredTestOp, ArmISA::SveUnpackOp, ArmISA::SveTblOp, ArmISA::SveUnaryPredPredOp, ArmISA::SveSelectOp, ArmISA::SvePartBrkPropOp, ArmISA::SvePartBrkOp, ArmISA::SveElemCountOp, ArmISA::SveAdrOp, ArmISA::SveIntCmpImmOp, ArmISA::SveIntCmpOp, ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::SvePtrueOp, ArmISA::SveOrdReducOp, ArmISA::SveReducOp, ArmISA::SveTerImmUnpredOp, ArmISA::SveTerPredOp, ArmISA::SveCmpImmOp, ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >, ArmISA::SveCmpOp, ArmISA::SvePredBinPermOp, ArmISA::SvePredLogicalOp, ArmISA::SveBinIdxUnpredOp, ArmISA::SveBinUnpredOp, ArmISA::SveBinConstrPredOp, ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::SveBinDestrPredOp, ArmISA::SveBinWideImmUnpredOp, ArmISA::SveBinImmPredOp, ArmISA::SveBinImmUnpredConstrOp, ArmISA::SveUnaryWideImmPredOp, ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::SveUnaryWideImmUnpredOp, ArmISA::SveUnaryUnpredOp, ArmISA::SveUnaryPredOp, ArmISA::SveCompTermOp, ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >, ArmISA::SveWhileOp, ArmISA::SvePredCountPredOp, ArmISA::SveContigMemSI, ArmISA::SvePredCountOp, ArmISA::SveContigMemSS, ArmISA::SveIndexRROp, ArmISA::SveIndexRIOp, ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >, ArmISA::SveMemPredFillSpill, ArmISA::SveIndexIROp, ArmISA::SveMemVecFillSpill, ArmISA::SveIndexIIOp, ArmISAInst::TmeRegNone64, ArmISAInst::TmeImmOp64, and ArmISAInst::MicroTmeBasic64.

Definition at line 623 of file static_inst.cc.

References printMnemonic(), and ArmISA::ss.

◆ getCurSveVecLen()

template<typename T >
static unsigned ArmISA::ArmStaticInst::getCurSveVecLen ( ThreadContext tc)
inlinestatic

Definition at line 559 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getCurSveVecLenInBits()

unsigned ArmISA::ArmStaticInst::getCurSveVecLenInBits ( ThreadContext tc)
static

◆ getCurSveVecLenInQWords()

static unsigned ArmISA::ArmStaticInst::getCurSveVecLenInQWords ( ThreadContext tc)
inlinestatic

Definition at line 552 of file static_inst.hh.

References getCurSveVecLenInBits().

◆ getIntWidth()

uint8_t ArmISA::ArmStaticInst::getIntWidth ( ) const
inline

Definition at line 519 of file static_inst.hh.

References intWidth.

◆ getPSTATEFromPSR()

CPSR ArmISA::ArmStaticInst::getPSTATEFromPSR ( ThreadContext tc,
CPSR  cpsr,
CPSR  spsr 
) const
protected

Get the new PSTATE from a SPSR register in preparation for an exception return.

See shared/functions/system/SetPSTATEFromPSR in the ARM ARM pseudocode library.

Definition at line 1145 of file static_inst.cc.

References ArmISA::currEL(), ArmISA::getRestoredITBits(), ArmISA::ISA::getSelfDebug(), ArmISA::illegalExceptionReturn(), ArmISA::sd, ArmISA::ss, and ArmISA::unknownMode32().

◆ instSize()

ssize_t ArmISA::ArmStaticInst::instSize ( ) const
inline

Returns the byte size of current instruction.

Definition at line 526 of file static_inst.hh.

References StaticInst::machInst.

Referenced by encoding().

◆ isWFxTrapping()

bool ArmISA::ArmStaticInst::isWFxTrapping ( ThreadContext tc,
ExceptionLevel  targetEL,
bool  isWfe 
) const
inlineprotected

◆ printCCReg()

void ArmISA::ArmStaticInst::printCCReg ( std::ostream &  os,
RegIndex  reg_idx 
) const
protected

Definition at line 361 of file static_inst.cc.

References ccprintf(), ArmISA::ccRegName, and X86ISA::os.

◆ printCondition()

void ArmISA::ArmStaticInst::printCondition ( std::ostream &  os,
unsigned  code,
bool  noImplicit = false 
) const
protected

◆ printDataInst() [1/2]

void ArmISA::ArmStaticInst::printDataInst ( std::ostream &  os,
bool  withImm 
) const
protected

◆ printDataInst() [2/2]

void ArmISA::ArmStaticInst::printDataInst ( std::ostream &  os,
bool  withImm,
bool  immShift,
bool  s,
IntRegIndex  rd,
IntRegIndex  rn,
IntRegIndex  rm,
IntRegIndex  rs,
uint32_t  shiftAmt,
ArmShiftType  type,
uint64_t  imm 
) const
protected

◆ printExtendOperand()

void ArmISA::ArmStaticInst::printExtendOperand ( bool  firstOperand,
std::ostream &  os,
IntRegIndex  rm,
ArmExtendType  type,
int64_t  shiftAmt 
) const
protected

◆ printFloatReg()

void ArmISA::ArmStaticInst::printFloatReg ( std::ostream &  os,
RegIndex  reg_idx 
) const
protected

◆ printIntReg()

void ArmISA::ArmStaticInst::printIntReg ( std::ostream &  os,
RegIndex  reg_idx,
uint8_t  opWidth = 0 
) const
protected

Print a register name for disassembly given the unique dependence tag number (FP or int).

Definition at line 296 of file static_inst.cc.

References aarch64, ccprintf(), ArmISA::FramePointerReg, ArmISA::INTREG_SPX, ArmISA::INTREG_UREG0, ArmISA::INTREG_X31, intWidth, X86ISA::os, ArmISA::PCReg, ArmISA::ReturnAddressReg, and ArmISA::StackPointerReg.

Referenced by ArmISA::SveMemVecFillSpill::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), ArmISA::SveIndexIROp::generateDisassembly(), ArmISA::BranchReg::generateDisassembly(), ArmISA::SveMemPredFillSpill::generateDisassembly(), ArmISA::BranchRegReg64::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveIndexRIOp::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), ArmISA::SveIndexRROp::generateDisassembly(), ArmISA::BranchRegReg::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), ArmISA::BranchRetA64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::SvePredCountPredOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), ArmISA::SveWhileOp::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), ArmISA::SveCompTermOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), MiscRegRegImmOp64::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), RegMiscRegImmOp64::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), RegNone::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveElemCountOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), printDataInst(), ArmISA::Memory::printDest(), ArmISA::MemoryExImm::printDest(), ArmISA::MemoryDImm::printDest(), ArmISA::MemoryExDImm::printDest(), ArmISA::MemoryDReg::printDest(), printExtendOperand(), and printShiftOperand().

◆ printMemSymbol()

void ArmISA::ArmStaticInst::printMemSymbol ( std::ostream &  os,
const Loader::SymbolTable symtab,
const std::string &  prefix,
const Addr  addr,
const std::string &  suffix 
) const
protected

◆ printMiscReg()

void ArmISA::ArmStaticInst::printMiscReg ( std::ostream &  os,
RegIndex  reg_idx 
) const
protected

◆ printMnemonic()

void ArmISA::ArmStaticInst::printMnemonic ( std::ostream &  os,
const std::string &  suffix = "",
bool  withPred = true,
bool  withCond64 = false,
ConditionCode  cond64 = COND_UC 
) const
protected

Definition at line 374 of file static_inst.cc.

References aarch64, StaticInst::machInst, StaticInst::mnemonic, X86ISA::os, and printCondition().

Referenced by ArmISA::BranchImm::generateDisassembly(), ArmISA::BranchImm64::generateDisassembly(), ArmISA::SveIndexIIOp::generateDisassembly(), ArmISA::SveMemVecFillSpill::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), ArmISA::BranchImmCond64::generateDisassembly(), ArmISA::SveIndexIROp::generateDisassembly(), ArmISA::BranchReg::generateDisassembly(), ArmISA::SveMemPredFillSpill::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::BranchRegReg64::generateDisassembly(), ArmISA::SveIndexRIOp::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), ArmISA::SveIndexRROp::generateDisassembly(), ArmISA::BranchRegReg::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), ArmISA::BranchRetA64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::BranchEret64::generateDisassembly(), ArmISA::SvePredCountPredOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), ArmISA::BranchEretA64::generateDisassembly(), ArmISA::SveWhileOp::generateDisassembly(), MiscRegImmOp64::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), ArmISA::SveCompTermOp::generateDisassembly(), MiscRegRegImmOp64::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), ArmISA::SveUnaryPredOp::generateDisassembly(), generateDisassembly(), RegMiscRegImmOp64::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), ArmISA::SveUnaryUnpredOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), RegNone::generateDisassembly(), ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), ArmISA::MicroSetPCCPSR::generateDisassembly(), ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), ArmISA::SveBinImmPredOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), ArmISA::SveBinDestrPredOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), ArmISA::SveBinConstrPredOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), ArmISA::SveBinUnpredOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::SveBinIdxUnpredOp::generateDisassembly(), ArmISA::SvePredLogicalOp::generateDisassembly(), ArmISA::SvePredBinPermOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::SveCmpOp::generateDisassembly(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::SveCmpImmOp::generateDisassembly(), ArmISA::SveTerPredOp::generateDisassembly(), ArmISA::SveTerImmUnpredOp::generateDisassembly(), ArmISA::SveReducOp::generateDisassembly(), ArmISA::SveOrdReducOp::generateDisassembly(), ArmISA::SvePtrueOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveIntCmpOp::generateDisassembly(), ArmISA::SveIntCmpImmOp::generateDisassembly(), ArmISA::SveAdrOp::generateDisassembly(), ArmISA::SvePartBrkOp::generateDisassembly(), ArmISA::SvePartBrkPropOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveUnaryPredPredOp::generateDisassembly(), ArmISA::SveTblOp::generateDisassembly(), ArmISA::SveUnpackOp::generateDisassembly(), ArmISA::SvePredTestOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly(), ArmISA::SveWImplicitSrcDstOp::generateDisassembly(), ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), ArmISA::SveDotProdIdxOp::generateDisassembly(), ArmISA::SveDotProdOp::generateDisassembly(), ArmISA::SveComplexOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::SveComplexIdxOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), and printDataInst().

◆ printPFflags()

void ArmISA::ArmStaticInst::printPFflags ( std::ostream &  os,
int  flag 
) const
protected

Definition at line 331 of file static_inst.cc.

References ccprintf(), and X86ISA::os.

◆ printShiftOperand()

void ArmISA::ArmStaticInst::printShiftOperand ( std::ostream &  os,
IntRegIndex  rm,
bool  immShift,
uint32_t  shiftAmt,
IntRegIndex  rs,
ArmShiftType  type 
) const
protected

◆ printTarget()

void ArmISA::ArmStaticInst::printTarget ( std::ostream &  os,
Addr  target,
const Loader::SymbolTable symtab 
) const
protected

◆ printVecPredReg()

void ArmISA::ArmStaticInst::printVecPredReg ( std::ostream &  os,
RegIndex  reg_idx 
) const
protected

Definition at line 355 of file static_inst.cc.

References ccprintf(), and X86ISA::os.

Referenced by ArmISA::SveMemPredFillSpill::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::SvePredCountPredOp::generateDisassembly(), ArmISA::SveWhileOp::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::SveUnaryPredOp::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), ArmISA::SveBinImmPredOp::generateDisassembly(), ArmISA::SveBinDestrPredOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::SveBinConstrPredOp::generateDisassembly(), ArmISA::SvePredLogicalOp::generateDisassembly(), ArmISA::SvePredBinPermOp::generateDisassembly(), ArmISA::SveCmpOp::generateDisassembly(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveCmpImmOp::generateDisassembly(), ArmISA::SveTerPredOp::generateDisassembly(), ArmISA::SveReducOp::generateDisassembly(), ArmISA::SveOrdReducOp::generateDisassembly(), ArmISA::SvePtrueOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveIntCmpOp::generateDisassembly(), ArmISA::SveIntCmpImmOp::generateDisassembly(), ArmISA::SvePartBrkOp::generateDisassembly(), ArmISA::SvePartBrkPropOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveUnaryPredPredOp::generateDisassembly(), ArmISA::SveUnpackOp::generateDisassembly(), ArmISA::SvePredTestOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly(), ArmISA::SveComplexOp::generateDisassembly(), and ArmISA::SveComplexIdxOp::generateDisassembly().

◆ printVecReg()

void ArmISA::ArmStaticInst::printVecReg ( std::ostream &  os,
RegIndex  reg_idx,
bool  isSveVecReg = false 
) const
protected

Definition at line 348 of file static_inst.cc.

References ccprintf(), and X86ISA::os.

Referenced by ArmISA::SveIndexIIOp::generateDisassembly(), ArmISA::SveMemVecFillSpill::generateDisassembly(), ArmISA::SveIndexIROp::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveIndexRIOp::generateDisassembly(), ArmISA::SveIndexRROp::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::SveUnaryPredOp::generateDisassembly(), ArmISA::SveUnaryUnpredOp::generateDisassembly(), ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), ArmISA::SveBinImmPredOp::generateDisassembly(), ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), ArmISA::SveBinDestrPredOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::SveBinConstrPredOp::generateDisassembly(), ArmISA::SveBinUnpredOp::generateDisassembly(), ArmISA::SveBinIdxUnpredOp::generateDisassembly(), ArmISA::SvePredLogicalOp::generateDisassembly(), ArmISA::SveCmpOp::generateDisassembly(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveCmpImmOp::generateDisassembly(), ArmISA::SveTerPredOp::generateDisassembly(), ArmISA::SveTerImmUnpredOp::generateDisassembly(), ArmISA::SveReducOp::generateDisassembly(), ArmISA::SveOrdReducOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveIntCmpOp::generateDisassembly(), ArmISA::SveIntCmpImmOp::generateDisassembly(), ArmISA::SveAdrOp::generateDisassembly(), ArmISA::SveElemCountOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveTblOp::generateDisassembly(), ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), ArmISA::SveDotProdIdxOp::generateDisassembly(), and ArmISA::SveDotProdOp::generateDisassembly().

◆ readPC()

static Addr ArmISA::ArmStaticInst::readPC ( ExecContext xc)
inlinestaticprotected

Definition at line 309 of file static_inst.hh.

References ExecContext::pcState().

Referenced by softwareBreakpoint32().

◆ satInt()

static bool ArmISA::ArmStaticInst::satInt ( int32_t &  res,
int64_t  op,
int  width 
)
inlinestaticprotected

Definition at line 99 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

◆ saturateOp()

template<int width>
static bool ArmISA::ArmStaticInst::saturateOp ( int32_t &  res,
int64_t  op1,
int64_t  op2,
bool  sub = false 
)
inlinestaticprotected

Definition at line 83 of file static_inst.hh.

References bits(), LL, and ArmISA::width.

◆ setAIWNextPC()

static void ArmISA::ArmStaticInst::setAIWNextPC ( ExecContext xc,
Addr  val 
)
inlinestaticprotected

Definition at line 367 of file static_inst.hh.

References MipsISA::pc, ExecContext::pcState(), and X86ISA::val.

◆ setIWNextPC()

static void ArmISA::ArmStaticInst::setIWNextPC ( ExecContext xc,
Addr  val 
)
inlinestaticprotected

Definition at line 357 of file static_inst.hh.

References MipsISA::pc, ExecContext::pcState(), and X86ISA::val.

◆ setNextPC()

static void ArmISA::ArmStaticInst::setNextPC ( ExecContext xc,
Addr  val 
)
inlinestaticprotected

Definition at line 315 of file static_inst.hh.

References MipsISA::pc, ExecContext::pcState(), and X86ISA::val.

◆ shift_carry_imm()

bool ArmISA::ArmStaticInst::shift_carry_imm ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

◆ shift_carry_rs()

bool ArmISA::ArmStaticInst::shift_carry_rs ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

◆ shift_rm_imm()

int32_t ArmISA::ArmStaticInst::shift_rm_imm ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

◆ shift_rm_rs()

int32_t ArmISA::ArmStaticInst::shift_rm_rs ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

◆ shiftReg64()

int64_t ArmISA::ArmStaticInst::shiftReg64 ( uint64_t  base,
uint64_t  shiftAmt,
ArmShiftType  type,
uint8_t  width 
) const
protected

◆ softwareBreakpoint32()

Fault ArmISA::ArmStaticInst::softwareBreakpoint32 ( ExecContext xc,
uint16_t  imm 
) const
protected

Trigger a Software Breakpoint.

See aarch32/exceptions/debug/AArch32.SoftwareBreakpoint in the ARM ARM psueodcode library.

Definition at line 632 of file static_inst.cc.

References ArmISA::ArmFault::BRKPOINT, ArmISA::ArmFault::DebugEvent, ArmISA::EL1, ArmISA::EL2, ArmISA::EL2Enabled(), ArmISA::ELIs32(), ArmISA::imm, StaticInst::machInst, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_MDCR_EL2, ThreadContext::readMiscReg(), readPC(), ExecContext::tcBase(), and ArmISA::ArmFault::UnknownTran.

◆ spsrWriteByInstr()

static uint32_t ArmISA::ArmStaticInst::spsrWriteByInstr ( uint32_t  spsr,
uint32_t  val,
uint8_t  byteMask,
bool  affectState 
)
inlinestaticprotected

Definition at line 291 of file static_inst.hh.

References bits(), ArmISA::mask, and X86ISA::val.

◆ sveAccessTrap()

Fault ArmISA::ArmStaticInst::sveAccessTrap ( ExceptionLevel  el) const
protected

Trap an access to SVE registers due to access control bits.

Parameters
elTarget EL for the trap.

Definition at line 996 of file static_inst.cc.

References ArmISA::EC_TRAPPED_SVE, ArmISA::el, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, and panic.

Referenced by checkSveEnabled().

◆ trapWFx()

Fault ArmISA::ArmStaticInst::trapWFx ( ThreadContext tc,
CPSR  cpsr,
SCR  scr,
bool  isWfe 
) const
protected

WFE/WFI trapping helper function.

Definition at line 899 of file static_inst.cc.

References checkForWFxTrap32(), ArmISA::currEL(), ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL2Enabled(), ArmISA::EL3, ArmSystem::haveEL(), and NoFault.

◆ undefinedFault32()

Fault ArmISA::ArmStaticInst::undefinedFault32 ( ThreadContext tc,
ExceptionLevel  el 
) const
protected

UNDEFINED behaviour in AArch32.

See aarch32/exceptions/traps/AArch32.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 957 of file static_inst.cc.

References ArmISA::EC_UNKNOWN, generalExceptionsToAArch64(), StaticInst::machInst, StaticInst::mnemonic, and undefinedFault64().

Referenced by checkSETENDEnabled().

◆ undefinedFault64()

Fault ArmISA::ArmStaticInst::undefinedFault64 ( ThreadContext tc,
ExceptionLevel  el 
) const
protected

UNDEFINED behaviour in AArch64.

See aarch64/exceptions/traps/AArch64.UndefinedFault in the ARM ARM pseudocode library.

Definition at line 976 of file static_inst.cc.

References ArmISA::EC_UNKNOWN, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, NoFault, and panic.

Referenced by undefinedFault32().

◆ uSatInt()

static bool ArmISA::ArmStaticInst::uSatInt ( int32_t &  res,
int64_t  op,
int  width 
)
inlinestaticprotected

Definition at line 132 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

◆ uSaturateOp()

template<int width>
static bool ArmISA::ArmStaticInst::uSaturateOp ( uint32_t &  res,
int64_t  op1,
int64_t  op2,
bool  sub = false 
)
inlinestaticprotected

Definition at line 116 of file static_inst.hh.

References LL, and ArmISA::width.

Member Data Documentation

◆ aarch64

bool ArmISA::ArmStaticInst::aarch64
protected

Definition at line 63 of file static_inst.hh.

Referenced by ArmStaticInst(), printIntReg(), and printMnemonic().

◆ intWidth

uint8_t ArmISA::ArmStaticInst::intWidth
protected

Definition at line 64 of file static_inst.hh.

Referenced by ArmStaticInst(), getIntWidth(), printIntReg(), and shiftReg64().


The documentation for this class was generated from the following files:

Generated on Wed Sep 30 2020 14:02:35 for gem5 by doxygen 1.8.17