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gem5
v20.1.0.0
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This is the complete list of members for ArmISA::SveBinImmPredOp, including all inherited members.
| _destRegIdx | StaticInst | protected |
| _numCCDestRegs | StaticInst | protected |
| _numDestRegs | StaticInst | protected |
| _numFPDestRegs | StaticInst | protected |
| _numIntDestRegs | StaticInst | protected |
| _numSrcRegs | StaticInst | protected |
| _numVecDestRegs | StaticInst | protected |
| _numVecElemDestRegs | StaticInst | protected |
| _numVecPredDestRegs | StaticInst | protected |
| _opClass | StaticInst | protected |
| _srcRegIdx | StaticInst | protected |
| aarch64 | ArmISA::ArmStaticInst | protected |
| activateBreakpoint(ThreadContext *tc) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| advancePC(PCState &pcState) const override | ArmISA::ArmStaticInst | inlineprotected |
| StaticInst::advancePC(TheISA::PCState &pcState) const =0 | StaticInst | pure virtual |
| advSIMDFPAccessTrap64(ExceptionLevel el) const | ArmISA::ArmStaticInst | protected |
| annotateFault(ArmFault *fault) | ArmISA::ArmStaticInst | inlinevirtual |
| ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | ArmISA::ArmStaticInst | inlineprotected |
| asBytes(void *buf, size_t max_size) override | ArmISA::ArmStaticInst | inlinevirtual |
| branchTarget(const TheISA::PCState &pc) const | StaticInst | virtual |
| branchTarget(ThreadContext *tc) const | StaticInst | virtual |
| cachedDisassembly | StaticInst | mutableprotected |
| checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const | ArmISA::ArmStaticInst | protected |
| checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | ArmISA::ArmStaticInst | protected |
| checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const | ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | ArmISA::ArmStaticInst | protected |
| checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const | ArmISA::ArmStaticInst | protected |
| checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const | ArmISA::ArmStaticInst | protected |
| checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const | ArmISA::ArmStaticInst | protected |
| completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const | StaticInst | inlinevirtual |
| count | RefCounted | mutableprivate |
| cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| cSwap(T val, bool big) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| decref() const | RefCounted | inline |
| dest | ArmISA::SveBinImmPredOp | protected |
| destRegIdx(int i) const | StaticInst | inline |
| disabledFault() const | ArmISA::ArmStaticInst | inlineprotected |
| disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const | StaticInst | virtual |
| encoding() const | ArmISA::ArmStaticInst | inline |
| execute(ExecContext *xc, Trace::InstRecord *traceData) const =0 | StaticInst | pure virtual |
| extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const | ArmISA::ArmStaticInst | protected |
| ExtMachInst typedef | StaticInst | |
| fetchMicroop(MicroPC upc) const | StaticInst | virtual |
| flags | StaticInst | protected |
| generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const | ArmISA::ArmStaticInst | protected |
| generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override | ArmISA::SveBinImmPredOp | protectedvirtual |
| getCurSveVecLen(ThreadContext *tc) | ArmISA::ArmStaticInst | inlinestatic |
| getCurSveVecLenInBits(ThreadContext *tc) | ArmISA::ArmStaticInst | static |
| getCurSveVecLenInQWords(ThreadContext *tc) | ArmISA::ArmStaticInst | inlinestatic |
| getIntWidth() const | ArmISA::ArmStaticInst | inline |
| getName() | StaticInst | inline |
| getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const | ArmISA::ArmStaticInst | protected |
| gp | ArmISA::SveBinImmPredOp | protected |
| hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const | StaticInst | |
| imm | ArmISA::SveBinImmPredOp | protected |
| incref() const | RefCounted | inline |
| initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const | StaticInst | inlinevirtual |
| instSize() const | ArmISA::ArmStaticInst | inline |
| intWidth | ArmISA::ArmStaticInst | protected |
| isAtomic() const | StaticInst | inline |
| isCall() const | StaticInst | inline |
| isCC() const | StaticInst | inline |
| isCondCtrl() const | StaticInst | inline |
| isCondDelaySlot() const | StaticInst | inline |
| isControl() const | StaticInst | inline |
| isDataPrefetch() const | StaticInst | inline |
| isDelayedCommit() const | StaticInst | inline |
| isDirectCtrl() const | StaticInst | inline |
| isFirstMicroop() const | StaticInst | inline |
| isFloating() const | StaticInst | inline |
| isHtmCancel() const | StaticInst | inline |
| isHtmCmd() const | StaticInst | inline |
| isHtmStart() const | StaticInst | inline |
| isHtmStop() const | StaticInst | inline |
| isIndirectCtrl() const | StaticInst | inline |
| isInstPrefetch() const | StaticInst | inline |
| isInteger() const | StaticInst | inline |
| isIprAccess() const | StaticInst | inline |
| isLastMicroop() const | StaticInst | inline |
| isLoad() const | StaticInst | inline |
| isMacroop() const | StaticInst | inline |
| isMemBarrier() const | StaticInst | inline |
| isMemRef() const | StaticInst | inline |
| isMicroBranch() const | StaticInst | inline |
| isMicroop() const | StaticInst | inline |
| isNonSpeculative() const | StaticInst | inline |
| isNop() const | StaticInst | inline |
| isPrefetch() const | StaticInst | inline |
| isQuiesce() const | StaticInst | inline |
| isReturn() const | StaticInst | inline |
| isSerializeAfter() const | StaticInst | inline |
| isSerializeBefore() const | StaticInst | inline |
| isSerializing() const | StaticInst | inline |
| isSquashAfter() const | StaticInst | inline |
| isStore() const | StaticInst | inline |
| isStoreConditional() const | StaticInst | inline |
| isSyscall() const | StaticInst | inline |
| isThreadSync() const | StaticInst | inline |
| isUncondCtrl() const | StaticInst | inline |
| isUnverifiable() const | StaticInst | inline |
| isVector() const | StaticInst | inline |
| isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const | ArmISA::ArmStaticInst | inlineprotected |
| isWriteBarrier() const | StaticInst | inline |
| machInst | StaticInst | |
| MaxInstDestRegs enum value | StaticInst | |
| MaxInstSrcRegs enum value | StaticInst | |
| mnemonic | StaticInst | protected |
| nopStaticInstPtr | StaticInst | static |
| nullStaticInstPtr | StaticInst | static |
| numCCDestRegs() const | StaticInst | inline |
| numDestRegs() const | StaticInst | inline |
| numFPDestRegs() const | StaticInst | inline |
| numIntDestRegs() const | StaticInst | inline |
| numSrcRegs() const | StaticInst | inline |
| numVecDestRegs() const | StaticInst | inline |
| numVecElemDestRegs() const | StaticInst | inline |
| numVecPredDestRegs() const | StaticInst | inline |
| opClass() const | StaticInst | inline |
| operator=(const RefCounted &) | RefCounted | private |
| printCCReg(std::ostream &os, RegIndex reg_idx) const | ArmISA::ArmStaticInst | protected |
| printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const | ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm) const | ArmISA::ArmStaticInst | protected |
| printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const | ArmISA::ArmStaticInst | protected |
| printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const | ArmISA::ArmStaticInst | protected |
| printFlags(std::ostream &outs, const std::string &separator) const | StaticInst | |
| printFloatReg(std::ostream &os, RegIndex reg_idx) const | ArmISA::ArmStaticInst | protected |
| printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const | ArmISA::ArmStaticInst | protected |
| printMemSymbol(std::ostream &os, const Loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const | ArmISA::ArmStaticInst | protected |
| printMiscReg(std::ostream &os, RegIndex reg_idx) const | ArmISA::ArmStaticInst | protected |
| printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const | ArmISA::ArmStaticInst | protected |
| printPFflags(std::ostream &os, int flag) const | ArmISA::ArmStaticInst | protected |
| printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const | ArmISA::ArmStaticInst | protected |
| printTarget(std::ostream &os, Addr target, const Loader::SymbolTable *symtab) const | ArmISA::ArmStaticInst | protected |
| printVecPredReg(std::ostream &os, RegIndex reg_idx) const | ArmISA::ArmStaticInst | protected |
| printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const | ArmISA::ArmStaticInst | protected |
| readPC(ExecContext *xc) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| RefCounted(const RefCounted &) | RefCounted | private |
| RefCounted() | RefCounted | inline |
| satInt(int32_t &res, int64_t op, int width) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| setAIWNextPC(ExecContext *xc, Addr val) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| setDelayedCommit() | StaticInst | inline |
| setFirstMicroop() | StaticInst | inline |
| setFlag(Flags f) | StaticInst | inline |
| setIWNextPC(ExecContext *xc, Addr val) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| setLastMicroop() | StaticInst | inline |
| setNextPC(ExecContext *xc, Addr val) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | ArmISA::ArmStaticInst | protected |
| shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | ArmISA::ArmStaticInst | protected |
| shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | ArmISA::ArmStaticInst | protected |
| shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const | ArmISA::ArmStaticInst | protected |
| shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const | ArmISA::ArmStaticInst | protected |
| simpleAsBytes(void *buf, size_t max_size, const T &t) | StaticInst | inlineprotected |
| softwareBreakpoint32(ExecContext *xc, uint16_t imm) const | ArmISA::ArmStaticInst | protected |
| spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| srcRegIdx(int i) const | StaticInst | inline |
| StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) | StaticInst | inlineprotected |
| sveAccessTrap(ExceptionLevel el) const | ArmISA::ArmStaticInst | protected |
| SveBinImmPredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp) | ArmISA::SveBinImmPredOp | inlineprotected |
| trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const | ArmISA::ArmStaticInst | protected |
| undefinedFault32(ThreadContext *tc, ExceptionLevel el) const | ArmISA::ArmStaticInst | protected |
| undefinedFault64(ThreadContext *tc, ExceptionLevel el) const | ArmISA::ArmStaticInst | protected |
| uSatInt(int32_t &res, int64_t op, int width) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) | ArmISA::ArmStaticInst | inlineprotectedstatic |
| ~RefCounted() | RefCounted | inlinevirtual |
| ~StaticInst() | StaticInst | virtual |