gem5  v20.1.0.0
AtomicSimpleCPU Member List

This is the complete list of members for AtomicSimpleCPU, including all inherited members.

_cacheLineSizeBaseCPUprotected
_cpuIdBaseCPUprotected
_dataRequestorIdBaseCPUprotected
_instRequestorIdBaseCPUprotected
_pidBaseCPUprotected
_socketIdBaseCPUprotected
_statusBaseSimpleCPUprotected
_switchedOutBaseCPUprotected
_taskIdBaseCPUprotected
activateContext(ThreadID thread_num) overrideAtomicSimpleCPUvirtual
activeThreadsBaseSimpleCPU
addressMonitorBaseCPUprivate
advancePC(const Fault &fault)BaseSimpleCPU
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) overrideAtomicSimpleCPUvirtual
armMonitor(ThreadID tid, Addr address)BaseCPU
AtomicSimpleCPU(AtomicSimpleCPUParams *params)AtomicSimpleCPU
BaseCPU(Params *params, bool is_checker=false)BaseCPU
BaseSimpleCPU(BaseSimpleCPUParams *params)BaseSimpleCPU
branchPredBaseSimpleCPUprotected
cacheLineSize() constBaseCPUinline
checkerBaseSimpleCPU
checkForInterrupts()BaseSimpleCPU
checkInterrupts(ThreadID tid) constBaseCPUinline
checkPcEventQueue()BaseSimpleCPUprotected
clearInterrupt(ThreadID tid, int int_num, int index)BaseCPUinline
clearInterrupts(ThreadID tid)BaseCPUinline
contextToThread(ContextID cid)BaseCPUinline
countInst()BaseSimpleCPU
CPU_STATE_ON enum valueBaseCPUprotected
CPU_STATE_SLEEP enum valueBaseCPUprotected
CPU_STATE_WAKEUP enum valueBaseCPUprotected
cpuId() constBaseCPUinline
cpuListBaseCPUprivatestatic
CPUState enum nameBaseCPUprotected
curMacroStaticInstBaseSimpleCPU
currentFunctionEndBaseCPUprivate
currentFunctionStartBaseCPUprivate
curStaticInstBaseSimpleCPU
curThreadBaseSimpleCPUprotected
data_amo_reqAtomicSimpleCPUprotected
data_read_reqAtomicSimpleCPUprotected
data_write_reqAtomicSimpleCPUprotected
dataRequestorId() constBaseCPUinline
dcache_accessAtomicSimpleCPUprotected
dcache_latencyAtomicSimpleCPUprotected
dcachePortAtomicSimpleCPUprotected
DcacheRetry enum valueBaseSimpleCPUprotected
DcacheWaitResponse enum valueBaseSimpleCPUprotected
DcacheWaitSwitch enum valueBaseSimpleCPUprotected
deschedulePowerGatingEvent()BaseCPU
drain() overrideAtomicSimpleCPU
drainResume() overrideAtomicSimpleCPU
DTBWaitResponse enum valueBaseSimpleCPUprotected
enableFunctionTrace()BaseCPUprivate
enterPwrGating()BaseCPUprotected
enterPwrGatingEventBaseCPUprotected
Faulting enum valueBaseSimpleCPUprotected
findContext(ThreadContext *tc)BaseCPU
flushTLBs()BaseCPU
functionEntryTickBaseCPUprivate
functionTraceStreamBaseCPUprivate
functionTracingEnabledBaseCPUprivate
genMemFragmentRequest(const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) constAtomicSimpleCPU
getContext(int tn)BaseCPUinlinevirtual
getCpuAddrMonitor(ThreadID tid)BaseCPUinline
getCurrentInstCount(ThreadID tid)BaseCPU
getDataPort() overrideAtomicSimpleCPUinlineprotectedvirtual
getInstPort() overrideAtomicSimpleCPUinlineprotectedvirtual
getInterruptController(ThreadID tid)BaseCPUinline
getPid() constBaseCPUinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overrideBaseCPU
getSendFunctional()BaseCPUinlinevirtual
getTracer()BaseCPUinline
haltContext(ThreadID thread_num) overrideBaseSimpleCPUvirtual
htmSendAbortSignal(HtmFailureFaultCause cause) overrideAtomicSimpleCPUinlinevirtual
icachePortAtomicSimpleCPUprotected
IcacheRetry enum valueBaseSimpleCPUprotected
IcacheWaitResponse enum valueBaseSimpleCPUprotected
IcacheWaitSwitch enum valueBaseSimpleCPUprotected
Idle enum valueBaseSimpleCPUprotected
ifetch_reqAtomicSimpleCPUprotected
init() overrideAtomicSimpleCPU
initiateHtmCmd(Request::Flags flags) overrideAtomicSimpleCPUinlinevirtual
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)BaseSimpleCPUinlinevirtual
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())BaseSimpleCPUinlinevirtual
instBaseSimpleCPU
instCntBaseCPUprotected
instCount()BaseCPUinline
instRequestorId() constBaseCPUinline
interruptsBaseCPUprotected
invldPidBaseCPUstatic
isCpuDrained() constAtomicSimpleCPUinlineprotected
ITBWaitResponse enum valueBaseSimpleCPUprotected
lockedAtomicSimpleCPUprotected
mwait(ThreadID tid, PacketPtr pkt)BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)BaseCPU
numContexts()BaseCPUinline
numCyclesBaseCPU
numSimulatedCPUs()BaseCPUinlinestatic
numSimulatedInsts()BaseCPUinlinestatic
numSimulatedInsts()BaseCPUinlinestatic
numSimulatedOps()BaseCPUinlinestatic
numSimulatedOps()BaseCPUinlinestatic
numThreadsBaseCPU
numWorkItemsCompletedBaseCPU
numWorkItemsStartedBaseCPU
params() constBaseCPUinline
Params typedefBaseCPU
PCMaskBaseCPUstatic
pmuProbePoint(const char *name)BaseCPUprotected
postExecute()BaseSimpleCPU
postInterrupt(ThreadID tid, int int_num, int index)BaseCPU
powerGatingOnIdleBaseCPUprotected
ppActiveCyclesBaseCPUprotected
ppAllCyclesBaseCPUprotected
ppCommitAtomicSimpleCPUprotected
ppRetiredBranchesBaseCPUprotected
ppRetiredInstsBaseCPUprotected
ppRetiredInstsPCBaseCPUprotected
ppRetiredLoadsBaseCPUprotected
ppRetiredStoresBaseCPUprotected
ppSleepingBaseCPUprotected
preExecute()BaseSimpleCPU
previousCycleBaseCPUprotected
previousStateBaseCPUprotected
printAddr(Addr a)AtomicSimpleCPU
probeInstCommit(const StaticInstPtr &inst, Addr pc)BaseCPUvirtual
pwrGatingLatencyBaseCPUprotected
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) overrideAtomicSimpleCPUvirtual
registerThreadContexts()BaseCPU
regProbePoints() overrideAtomicSimpleCPU
regStats() overrideBaseSimpleCPU
resetStats() overrideBaseSimpleCPU
Running enum valueBaseSimpleCPUprotected
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)BaseCPU
schedulePowerGatingEvent()BaseCPU
sendPacket(RequestPort &port, const PacketPtr &pkt)AtomicSimpleCPUprotectedvirtual
serialize(CheckpointOut &cp) const overrideBaseCPU
serializeThread(CheckpointOut &cp, ThreadID tid) const overrideBaseSimpleCPUvirtual
setPid(uint32_t pid)BaseCPUinline
setupFetchRequest(const RequestPtr &req)BaseSimpleCPU
simulate_data_stallsAtomicSimpleCPUprotected
simulate_inst_stallsAtomicSimpleCPUprotected
socketId() constBaseCPUinline
startup() overrideBaseCPU
Status enum nameBaseSimpleCPUprotected
suspendContext(ThreadID thread_num) overrideAtomicSimpleCPUvirtual
swapActiveThread()BaseSimpleCPUprotected
switchedOut() constBaseCPUinline
switchOut() overrideAtomicSimpleCPUvirtual
syscallRetryLatencyBaseCPU
systemBaseCPU
takeOverFrom(BaseCPU *oldCPU) overrideAtomicSimpleCPUvirtual
taskId() constBaseCPUinline
taskId(uint32_t id)BaseCPUinline
threadContextsBaseCPUprotected
threadInfoBaseSimpleCPU
threadSnoop(PacketPtr pkt, ThreadID sender)AtomicSimpleCPUprotected
tick()AtomicSimpleCPUprotected
tickEventAtomicSimpleCPUprotected
totalInsts() const overrideBaseSimpleCPUvirtual
totalOps() const overrideBaseSimpleCPUvirtual
traceDataBaseSimpleCPU
traceFault()BaseSimpleCPUprotected
traceFunctions(Addr pc)BaseCPUinline
traceFunctionsInternal(Addr pc)BaseCPUprivate
tracerBaseCPUprotected
tryCompleteDrain()AtomicSimpleCPUprotected
unserialize(CheckpointIn &cp) overrideBaseCPU
unserializeThread(CheckpointIn &cp, ThreadID tid) overrideBaseSimpleCPUvirtual
updateCycleCounters(CPUState state)BaseCPUinlineprotected
verifyMemoryMode() const overrideAtomicSimpleCPUvirtual
waitForRemoteGDB() constBaseCPU
wakeup(ThreadID tid) overrideBaseSimpleCPUvirtual
widthAtomicSimpleCPUprotected
workItemBegin()BaseCPUinline
workItemEnd()BaseCPUinline
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) overrideAtomicSimpleCPUvirtual
~AtomicSimpleCPU()AtomicSimpleCPUvirtual
~BaseCPU()BaseCPUvirtual
~BaseSimpleCPU()BaseSimpleCPUvirtual

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