#include <atomic.hh>

Inheritance diagram for AtomicSimpleCPU:

Classes
class	AtomicCPUDPort

class	AtomicCPUPort
	An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instead of panicking. More...

Public Member Functions
	AtomicSimpleCPU (AtomicSimpleCPUParams *params)

virtual	~AtomicSimpleCPU ()

void	init () override

DrainState	drain () override

void	drainResume () override

void	switchOut () override
	Prepare for another CPU to take over execution. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU. More...

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active. More...

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended. More...

bool	genMemFragmentRequest (const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
	Helper function used to set up the request for a single fragment of a memory access. More...

Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	initiateHtmCmd (Request::Flags flags) override
	Hardware transactional memory commands (HtmCmds), e.g. More...

void	htmSendAbortSignal (HtmFailureFaultCause cause) override
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

void	regProbePoints () override

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging). More...

Public Member Functions inherited from BaseSimpleCPU
	BaseSimpleCPU (BaseSimpleCPUParams *params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	init () override

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted. More...

void	regStats () override

void	resetStats () override

virtual Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

Public Member Functions inherited from BaseCPU
virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override

void	startup () override

void	regStats () override

void	regProbePoints () override

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Protected Member Functions
void	tick ()

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

bool	tryCompleteDrain ()
	Try to complete a drain request. More...

virtual Tick	sendPacket (RequestPort &port, const PacketPtr &pkt)

Port &	getDataPort () override
	Return a reference to the data port. More...

Port &	getInstPort () override
	Return a reference to the instruction port. More...

void	threadSnoop (PacketPtr pkt, ThreadID sender)
	Perform snoop for other cpu-local thread contexts. More...

Protected Member Functions inherited from BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

void	traceFault ()
	Handler used when encountering a fault; its purpose is to tear down the InstRecord. More...

Protected Member Functions inherited from BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Attributes
EventFunctionWrapper	tickEvent

const int	width

bool	locked

const bool	simulate_data_stalls

const bool	simulate_inst_stalls

AtomicCPUPort	icachePort

AtomicCPUDPort	dcachePort

RequestPtr	ifetch_req

RequestPtr	data_read_req

RequestPtr	data_write_req

RequestPtr	data_amo_req

bool	dcache_access

Tick	dcache_latency

ProbePointArg< std::pair< SimpleThread , const StaticInstPtr > >	ppCommit
	Probe Points. More...

Protected Attributes inherited from BaseSimpleCPU
ThreadID	curThread

BPredUnit *	branchPred

Status	_status

Protected Attributes inherited from BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Additional Inherited Members
Public Types inherited from BaseCPU
typedef BaseCPUParams	Params

Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Public Attributes inherited from BaseSimpleCPU
Trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

TheISA::MachInst	inst
	Current instruction. More...

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Static Public Attributes inherited from BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Types inherited from BaseSimpleCPU
enum	Status { Idle, Running, Faulting, ITBWaitResponse, IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse, DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch }

Protected Types inherited from BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Detailed Description

Definition at line 50 of file atomic.hh.

Constructor & Destructor Documentation

◆ AtomicSimpleCPU()

AtomicSimpleCPU::AtomicSimpleCPU ( AtomicSimpleCPUParams * params )

Definition at line 76 of file atomic.cc.

References tick().

◆ ~AtomicSimpleCPU()

AtomicSimpleCPU::~AtomicSimpleCPU ( )

virtual

Definition at line 96 of file atomic.cc.

References Event::scheduled(), and tickEvent.

Member Function Documentation

◆ activateContext()

void AtomicSimpleCPU::activateContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now active.

Reimplemented from BaseCPU.

Definition at line 223 of file atomic.cc.

References BaseSimpleCPU::_status, BaseCPU::activateContext(), BaseSimpleCPU::activeThreads, DPRINTF, BaseCPU::numCycles, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseSimpleCPU::threadInfo, and tickEvent.

◆ amoMem()

Fault AtomicSimpleCPU::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

overridevirtual

◆ drain()

DrainState AtomicSimpleCPU::drain ( )

override

Definition at line 104 of file atomic.cc.

References BaseSimpleCPU::activeThreads, BaseCPU::deschedulePowerGatingEvent(), DPRINTF, Drained, Draining, isCpuDrained(), Event::scheduled(), BaseCPU::switchedOut(), and tickEvent.

◆ drainResume()

void AtomicSimpleCPU::drainResume ( )

override

Definition at line 144 of file atomic.cc.

References BaseSimpleCPU::_status, ThreadContext::Active, BaseSimpleCPU::activeThreads, DPRINTF, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::schedulePowerGatingEvent(), BaseCPU::switchedOut(), BaseCPU::threadContexts, BaseSimpleCPU::threadInfo, tickEvent, and verifyMemoryMode().

◆ genMemFragmentRequest()

bool AtomicSimpleCPU::genMemFragmentRequest	(	const RequestPtr &	req,
		Addr	frag_addr,
		int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable,
		int &	frag_size,
		int &	size_left
	)		const

Helper function used to set up the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters

	req	Pointer to the Request object to populate.
	frag_addr	Start address of the fragment.
	size	Total size of the memory access in bytes.
	flags	Request flags.
	byte_enable	Byte-enable mask for the entire memory access.
[out]	frag_size	Fragment size.
[in,out]	size_left	Size left to be processed in the memory access.

Returns: True if the byte-enable mask for the fragment is not all-false.

Definition at line 335 of file atomic.cc.

References addrBlockOffset(), BaseCPU::cacheLineSize(), BaseSimpleCPU::curThread, BaseCPU::dataRequestorId(), isAnyActiveElement(), and BaseSimpleCPU::threadInfo.

Referenced by readMem(), and writeMem().

◆ getDataPort()

Port& AtomicSimpleCPU::getDataPort ( )

inlineoverrideprotectedvirtual

Return a reference to the data port.

Implements BaseCPU.

Definition at line 175 of file atomic.hh.

References dcachePort.

◆ getInstPort()

Port& AtomicSimpleCPU::getInstPort ( )

inlineoverrideprotectedvirtual

Return a reference to the instruction port.

Implements BaseCPU.

Definition at line 178 of file atomic.hh.

References icachePort.

◆ htmSendAbortSignal()

void AtomicSimpleCPU::htmSendAbortSignal ( HtmFailureFaultCause cause )

inlineoverridevirtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Implements BaseSimpleCPU.

Definition at line 228 of file atomic.hh.

References panic.

◆ init()

void AtomicSimpleCPU::init ( )

override

Definition at line 65 of file atomic.cc.

References BaseSimpleCPU::init().

◆ initiateHtmCmd()

Fault AtomicSimpleCPU::initiateHtmCmd ( Request::Flags flags )

inlineoverridevirtual

Hardware transactional memory commands (HtmCmds), e.g.

start a transaction and commit a transaction, are memory operations but are neither really (true) loads nor stores. For this reason the interface is extended and initiateHtmCmd() is used to instigate the command.

Implements BaseSimpleCPU.

Definition at line 222 of file atomic.hh.

References panic.

◆ isCpuDrained()

bool AtomicSimpleCPU::isCpuDrained ( ) const

inlineprotected

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
The CPU is in a LLSC region. This shouldn't normally happen as these are executed atomically within a single tick() call. The only way this can happen at the moment is if there is an event in the PC event queue that affects the CPU state while it is in an LLSC region.
Stay at PC is true.

Definition at line 89 of file atomic.hh.

References BaseSimpleCPU::curThread, locked, SimpleThread::microPC(), SimpleExecContext::stayAtPC, SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by drain(), switchOut(), and tryCompleteDrain().

◆ printAddr()

void AtomicSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 776 of file atomic.cc.

References ArmISA::a, dcachePort, and RequestPort::printAddr().

◆ readMem()

Fault AtomicSimpleCPU::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

Reimplemented from BaseSimpleCPU.

Definition at line 369 of file atomic.cc.

References addr, BaseSimpleCPU::curThread, data, data_read_req, Packet::dataStatic(), dcache_access, dcache_latency, dcachePort, SimpleThread::dtb, genMemFragmentRequest(), SimpleThread::getTC(), ArmISA::handleLockedRead(), Packet::isError(), locked, Packet::makeReadCmd(), Request::NO_ACCESS, NoFault, BaseTLB::Read, sendPacket(), Trace::InstRecord::setMem(), BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, and BaseTLB::translateAtomic().

◆ regProbePoints()

void AtomicSimpleCPU::regProbePoints ( )

override

Definition at line 767 of file atomic.cc.

References ppCommit, and BaseCPU::regProbePoints().

◆ sendPacket()

Tick AtomicSimpleCPU::sendPacket	(	RequestPort &	port,
		const PacketPtr &	pkt
	)

protectedvirtual

Reimplemented in NonCachingSimpleCPU.

Definition at line 275 of file atomic.cc.

References RequestPort::sendAtomic().

Referenced by amoMem(), readMem(), tick(), and writeMem().

◆ suspendContext()

void AtomicSimpleCPU::suspendContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented from BaseCPU.

Definition at line 249 of file atomic.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, DPRINTF, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::suspendContext(), BaseSimpleCPU::threadInfo, and tickEvent.

◆ switchOut()

void AtomicSimpleCPU::switchOut ( )

overridevirtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented from BaseCPU.

Definition at line 194 of file atomic.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::Idle, isCpuDrained(), BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::switchOut(), and tickEvent.

◆ takeOverFrom()

void AtomicSimpleCPU::takeOverFrom ( BaseCPU * cpu )

overridevirtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from BaseCPU.

Definition at line 205 of file atomic.cc.

References Event::scheduled(), BaseCPU::takeOverFrom(), and tickEvent.

◆ threadSnoop()

void AtomicSimpleCPU::threadSnoop	(	PacketPtr	pkt,
		ThreadID	sender
	)

protected

Perform snoop for other cpu-local thread contexts.

Definition at line 126 of file atomic.cc.

References AtomicSimpleCPU::AtomicCPUDPort::cacheBlockMask, Packet::cmdString(), dcachePort, DPRINTF, Packet::getAddr(), BaseCPU::getCpuAddrMonitor(), ArmISA::handleLockedSnoop(), BaseCPU::numThreads, BaseSimpleCPU::threadInfo, and BaseSimpleCPU::wakeup().

Referenced by writeMem().

◆ tick()

void AtomicSimpleCPU::tick ( )

protected

Definition at line 630 of file atomic.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::advancePC(), BaseSimpleCPU::checkForInterrupts(), BaseSimpleCPU::checkPcEventQueue(), BaseSimpleCPU::countInst(), BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curMacroStaticInst, BaseSimpleCPU::curStaticInst, BaseSimpleCPU::curThread, curTick(), data_amo_req, data_read_req, data_write_req, Packet::dataStatic(), dcache_access, dcache_latency, divCeil(), DPRINTF, BaseTLB::Execute, StaticInst::execute(), SimpleThread::getTC(), ArmISA::i, icachePort, BaseSimpleCPU::Idle, ifetch_req, BaseSimpleCPU::inst, BaseCPU::instCnt, StaticInst::isDelayedCommit(), Packet::isError(), StaticInst::isFirstMicroop(), StaticInst::isMicroop(), isRomMicroPC(), SimpleThread::itb, locked, NoFault, BaseCPU::numCycles, BaseCPU::numThreads, SimpleThread::pcState(), BaseSimpleCPU::postExecute(), ppCommit, BaseSimpleCPU::preExecute(), MemCmd::ReadReq, sendPacket(), BaseSimpleCPU::setupFetchRequest(), simulate_data_stalls, simulate_inst_stalls, SimpleExecContext::stayAtPC, BaseSimpleCPU::swapActiveThread(), BaseCPU::syscallRetryLatency, BaseCPU::taskId(), SimpleExecContext::thread, BaseCPU::threadContexts, BaseSimpleCPU::threadInfo, tickEvent, BaseSimpleCPU::traceData, BaseSimpleCPU::traceFault(), BaseTLB::translateAtomic(), tryCompleteDrain(), BaseCPU::updateCycleCounters(), and width.

Referenced by AtomicSimpleCPU().

◆ tryCompleteDrain()

bool AtomicSimpleCPU::tryCompleteDrain ( )

protected

Try to complete a drain request.

Returns: true if the CPU is drained, false otherwise.

Definition at line 177 of file atomic.cc.

References DPRINTF, Draining, and isCpuDrained().

Referenced by tick().

◆ verifyMemoryMode()

void AtomicSimpleCPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from BaseCPU.

Reimplemented in NonCachingSimpleCPU.

Definition at line 214 of file atomic.cc.

References fatal, System::isAtomicMode(), and BaseCPU::system.

Referenced by drainResume().

◆ writeMem()

Fault AtomicSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

Member Data Documentation

◆ data_amo_req

RequestPtr AtomicSimpleCPU::data_amo_req

protected

Definition at line 164 of file atomic.hh.

Referenced by amoMem(), and tick().

◆ data_read_req

RequestPtr AtomicSimpleCPU::data_read_req

protected

Definition at line 162 of file atomic.hh.

Referenced by readMem(), and tick().

◆ data_write_req

RequestPtr AtomicSimpleCPU::data_write_req

protected

Definition at line 163 of file atomic.hh.

Referenced by tick(), and writeMem().

◆ dcache_access

bool AtomicSimpleCPU::dcache_access

protected

Definition at line 166 of file atomic.hh.

Referenced by amoMem(), readMem(), tick(), and writeMem().

◆ dcache_latency

Tick AtomicSimpleCPU::dcache_latency

protected

Definition at line 167 of file atomic.hh.

Referenced by amoMem(), readMem(), tick(), and writeMem().

◆ dcachePort

AtomicCPUDPort AtomicSimpleCPU::dcachePort

protected

Definition at line 158 of file atomic.hh.

Referenced by amoMem(), getDataPort(), printAddr(), readMem(), threadSnoop(), and writeMem().

◆ icachePort

AtomicCPUPort AtomicSimpleCPU::icachePort

protected

Definition at line 157 of file atomic.hh.

Referenced by getInstPort(), and tick().

◆ ifetch_req

RequestPtr AtomicSimpleCPU::ifetch_req

protected

Definition at line 161 of file atomic.hh.

Referenced by tick().

◆ locked

bool AtomicSimpleCPU::locked

protected

Definition at line 64 of file atomic.hh.

Referenced by isCpuDrained(), readMem(), tick(), and writeMem().

◆ ppCommit

ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr> >* AtomicSimpleCPU::ppCommit

protected

Probe Points.

Definition at line 170 of file atomic.hh.

Referenced by regProbePoints(), and tick().

◆ simulate_data_stalls

const bool AtomicSimpleCPU::simulate_data_stalls

protected

Definition at line 65 of file atomic.hh.

Referenced by tick().

◆ simulate_inst_stalls

const bool AtomicSimpleCPU::simulate_inst_stalls

protected

Definition at line 66 of file atomic.hh.

Referenced by tick().

◆ tickEvent

EventFunctionWrapper AtomicSimpleCPU::tickEvent

protected

Definition at line 61 of file atomic.hh.

Referenced by activateContext(), drain(), drainResume(), suspendContext(), switchOut(), takeOverFrom(), tick(), and ~AtomicSimpleCPU().

◆ width

const int AtomicSimpleCPU::width

protected

Definition at line 63 of file atomic.hh.

Referenced by tick().

The documentation for this class was generated from the following files:

cpu/simple/atomic.hh
cpu/simple/atomic.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ AtomicSimpleCPU()

◆ ~AtomicSimpleCPU()

Member Function Documentation

◆ activateContext()

◆ amoMem()

◆ drain()

◆ drainResume()

◆ genMemFragmentRequest()

◆ getDataPort()

◆ getInstPort()

◆ htmSendAbortSignal()

◆ init()

◆ initiateHtmCmd()

◆ isCpuDrained()

◆ printAddr()

◆ readMem()

◆ regProbePoints()

◆ sendPacket()

◆ suspendContext()

◆ switchOut()

◆ takeOverFrom()

◆ threadSnoop()

◆ tick()

◆ tryCompleteDrain()

◆ verifyMemoryMode()

◆ writeMem()

Member Data Documentation

◆ data_amo_req

◆ data_read_req

◆ data_write_req

◆ dcache_access

◆ dcache_latency

◆ dcachePort

◆ icachePort

◆ ifetch_req

◆ locked

◆ ppCommit

◆ simulate_data_stalls

◆ simulate_inst_stalls

◆ tickEvent

◆ width