BaseO3DynInst< Impl > Member List

This is the complete list of members for BaseO3DynInst< Impl >, including all inherited members.

_destMiscRegIdx	BaseO3DynInst< Impl >	protected
_destMiscRegVal	BaseO3DynInst< Impl >	protected
_destRegIdx	BaseDynInst< Impl >	protected
_flatDestRegIdx	BaseDynInst< Impl >	protected
_numDestMiscRegs	BaseO3DynInst< Impl >	protected
_prevDestRegIdx	BaseDynInst< Impl >	protected
_readySrcRegIdx	BaseDynInst< Impl >	protected
_srcRegIdx	BaseDynInst< Impl >	protected
amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)	ExecContext	inlinevirtual
armMonitor(Addr address) override	BaseDynInst< Impl >	inlinevirtual
AtCommit enum value	BaseDynInst< Impl >	protected
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu)	BaseDynInst< Impl >
BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop)	BaseDynInst< Impl >
BaseDynInstPtr typedef	BaseDynInst< Impl >
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu)	BaseO3DynInst< Impl >
BaseO3DynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop)	BaseO3DynInst< Impl >
BlockingInst enum value	BaseDynInst< Impl >	protected
branchTarget() const	BaseDynInst< Impl >	inline
CanCommit enum value	BaseDynInst< Impl >	protected
CanIssue enum value	BaseDynInst< Impl >	protected
clearCanCommit()	BaseDynInst< Impl >	inline
clearCanIssue()	BaseDynInst< Impl >	inline
clearHtmTransactionalState()	BaseDynInst< Impl >	inline
clearInIQ()	BaseDynInst< Impl >	inline
clearInROB()	BaseDynInst< Impl >	inline
clearIssued()	BaseDynInst< Impl >	inline
clearSerializeAfter()	BaseDynInst< Impl >	inline
clearSerializeBefore()	BaseDynInst< Impl >	inline
Committed enum value	BaseDynInst< Impl >	protected
completeAcc(PacketPtr pkt)	BaseO3DynInst< Impl >
Completed enum value	BaseDynInst< Impl >	protected
contextId() const	BaseDynInst< Impl >	inline
count	RefCounted	mutableprivate
cpu	BaseDynInst< Impl >
cpuId() const	BaseDynInst< Impl >	inline
decref() const	RefCounted	inline
demapDataPage(Addr vaddr, uint64_t asn)	BaseDynInst< Impl >	inline
demapInstPage(Addr vaddr, uint64_t asn)	BaseDynInst< Impl >	inline
demapPage(Addr vaddr, uint64_t asn) override	BaseDynInst< Impl >	inlinevirtual
destRegIdx(int i) const	BaseDynInst< Impl >	inline
doneTargCalc()	BaseDynInst< Impl >	inline
dump()	BaseDynInst< Impl >
dump(std::string &outstring)	BaseDynInst< Impl >
DynInstPtr typedef	BaseDynInst< Impl >
eaSrcsReady() const	BaseDynInst< Impl >
effAddr	BaseDynInst< Impl >
effAddrValid() const	BaseDynInst< Impl >	inline
effAddrValid(bool b)	BaseDynInst< Impl >	inline
EffAddrValid enum value	BaseDynInst< Impl >	protected
effSize	BaseDynInst< Impl >
execute()	BaseO3DynInst< Impl >
Executed enum value	BaseDynInst< Impl >	protected
fault	BaseDynInst< Impl >
Flags enum name	BaseDynInst< Impl >	protected
flattenDestReg(int idx, const RegId &flattened_dest)	BaseDynInst< Impl >	inline
flattenedDestRegIdx(int idx) const	BaseDynInst< Impl >	inline
forwardOldRegs()	BaseO3DynInst< Impl >	inline
getAddrMonitor() override	BaseDynInst< Impl >	inlinevirtual
getCpuPtr()	BaseDynInst< Impl >	inline
getFault() const	BaseDynInst< Impl >	inline
getFault()	BaseDynInst< Impl >	inline
getHtmTransactionalDepth() const override	BaseDynInst< Impl >	inlinevirtual
getHtmTransactionUid() const override	BaseDynInst< Impl >	inlinevirtual
getInstListIt()	BaseDynInst< Impl >	inline
getWritableVecPredRegOperand(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
getWritableVecRegOperand(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
hasRequest() const	BaseDynInst< Impl >	inline
hitExternalSnoop() const	BaseDynInst< Impl >	inline
hitExternalSnoop(bool f)	BaseDynInst< Impl >	inline
HitExternalSnoop enum value	BaseDynInst< Impl >	protected
htmDepth	BaseDynInst< Impl >	private
HtmFromTransaction enum value	BaseDynInst< Impl >	protected
htmUid	BaseDynInst< Impl >	private
ImplCPU typedef	BaseDynInst< Impl >
ImplState typedef	BaseDynInst< Impl >
incref() const	RefCounted	inline
inHtmTransactionalState() const override	BaseDynInst< Impl >	inlinevirtual
initiateAcc()	BaseO3DynInst< Impl >
initiateHtmCmd(Request::Flags flags) override	BaseDynInst< Impl >	virtual
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override	BaseDynInst< Impl >
ExecContext::initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)	ExecContext	inlinevirtual
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override	BaseDynInst< Impl >
ExecContext::initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())	ExecContext	inlinevirtual
initVars()	BaseO3DynInst< Impl >	private
instAddr() const	BaseDynInst< Impl >	inline
instFlags	BaseDynInst< Impl >	private
instListIt	BaseDynInst< Impl >
instResult	BaseDynInst< Impl >	protected
IqEntry enum value	BaseDynInst< Impl >	protected
isAtCommit()	BaseDynInst< Impl >	inline
isAtomic() const	BaseDynInst< Impl >	inline
isCall() const	BaseDynInst< Impl >	inline
isCommitted() const	BaseDynInst< Impl >	inline
isCompleted() const	BaseDynInst< Impl >	inline
isCondCtrl() const	BaseDynInst< Impl >	inline
isCondDelaySlot() const	BaseDynInst< Impl >	inline
isControl() const	BaseDynInst< Impl >	inline
isDataPrefetch() const	BaseDynInst< Impl >	inline
isDelayedCommit() const	BaseDynInst< Impl >	inline
isDirectCtrl() const	BaseDynInst< Impl >	inline
isExecuted() const	BaseDynInst< Impl >	inline
isFirstMicroop() const	BaseDynInst< Impl >	inline
isFloating() const	BaseDynInst< Impl >	inline
isHtmCancel() const	BaseDynInst< Impl >	inline
isHtmCmd() const	BaseDynInst< Impl >	inline
isHtmStart() const	BaseDynInst< Impl >	inline
isHtmStop() const	BaseDynInst< Impl >	inline
isIndirectCtrl() const	BaseDynInst< Impl >	inline
isInIQ() const	BaseDynInst< Impl >	inline
isInLSQ() const	BaseDynInst< Impl >	inline
isInROB() const	BaseDynInst< Impl >	inline
isInstPrefetch() const	BaseDynInst< Impl >	inline
isInteger() const	BaseDynInst< Impl >	inline
isIprAccess() const	BaseDynInst< Impl >	inline
isIssued() const	BaseDynInst< Impl >	inline
isLastMicroop() const	BaseDynInst< Impl >	inline
isLoad() const	BaseDynInst< Impl >	inline
isMacroop() const	BaseDynInst< Impl >	inline
isMemBarrier() const	BaseDynInst< Impl >	inline
isMemRef() const	BaseDynInst< Impl >	inline
isMicroBranch() const	BaseDynInst< Impl >	inline
isMicroop() const	BaseDynInst< Impl >	inline
isNonSpeculative() const	BaseDynInst< Impl >	inline
isNop() const	BaseDynInst< Impl >	inline
isPinnedRegsRenamed() const	BaseDynInst< Impl >	inline
isPinnedRegsSquashDone() const	BaseDynInst< Impl >	inline
isPinnedRegsWritten() const	BaseDynInst< Impl >	inline
isQuiesce() const	BaseDynInst< Impl >	inline
isReadySrcRegIdx(int idx) const	BaseDynInst< Impl >	inline
isResultReady() const	BaseDynInst< Impl >	inline
isReturn() const	BaseDynInst< Impl >	inline
isSerializeAfter() const	BaseDynInst< Impl >	inline
isSerializeBefore() const	BaseDynInst< Impl >	inline
isSerializeHandled()	BaseDynInst< Impl >	inline
isSerializing() const	BaseDynInst< Impl >	inline
isSquashAfter() const	BaseDynInst< Impl >	inline
isSquashed() const	BaseDynInst< Impl >	inline
isSquashedInIQ() const	BaseDynInst< Impl >	inline
isSquashedInLSQ() const	BaseDynInst< Impl >	inline
isSquashedInROB() const	BaseDynInst< Impl >	inline
isStore() const	BaseDynInst< Impl >	inline
isStoreConditional() const	BaseDynInst< Impl >	inline
IsStrictlyOrdered enum value	BaseDynInst< Impl >	protected
Issued enum value	BaseDynInst< Impl >	protected
isSyscall() const	BaseDynInst< Impl >	inline
isTempSerializeAfter()	BaseDynInst< Impl >	inline
isTempSerializeBefore()	BaseDynInst< Impl >	inline
isThreadSync() const	BaseDynInst< Impl >	inline
isTranslationDelayed() const	BaseDynInst< Impl >	inline
isUncondCtrl() const	BaseDynInst< Impl >	inline
isUnverifiable() const	BaseDynInst< Impl >	inline
isVector() const	BaseDynInst< Impl >	inline
isWriteBarrier() const	BaseDynInst< Impl >	inline
ListIt typedef	BaseDynInst< Impl >
lqIdx	BaseDynInst< Impl >
lqIt	BaseDynInst< Impl >
LQIterator typedef	BaseDynInst< Impl >
LsqEntry enum value	BaseDynInst< Impl >	protected
LSQRequestPtr typedef	BaseDynInst< Impl >
MachInst typedef	BaseO3DynInst< Impl >
macroop	BaseDynInst< Impl >
markSrcRegReady()	BaseDynInst< Impl >
markSrcRegReady(RegIndex src_idx)	BaseDynInst< Impl >
MaxFlags enum value	BaseDynInst< Impl >	protected
MaxInstDestRegs enum value	BaseO3DynInst< Impl >
MaxInstSrcRegs enum value	BaseO3DynInst< Impl >
MemAccPredicate enum value	BaseDynInst< Impl >	protected
memData	BaseDynInst< Impl >
MemOpDone enum value	BaseDynInst< Impl >	protected
memOpDone() const	BaseDynInst< Impl >	inline
memOpDone(bool f)	BaseDynInst< Impl >	inline
memReqFlags	BaseDynInst< Impl >
microPC() const	BaseDynInst< Impl >	inline
mispredicted()	BaseDynInst< Impl >	inline
mwait(PacketPtr pkt) override	BaseDynInst< Impl >	inlinevirtual
mwaitAtomic(ThreadContext *tc) override	BaseDynInst< Impl >	inlinevirtual
newHtmTransactionUid() const override	BaseDynInst< Impl >	inlinevirtual
nextInstAddr() const	BaseDynInst< Impl >	inline
notAnInst() const	BaseDynInst< Impl >	inline
NotAnInst enum value	BaseDynInst< Impl >	protected
numCCDestRegs() const	BaseDynInst< Impl >	inline
numDestRegs() const	BaseDynInst< Impl >	inline
numFPDestRegs() const	BaseDynInst< Impl >	inline
numIntDestRegs() const	BaseDynInst< Impl >	inline
numSrcRegs() const	BaseDynInst< Impl >	inline
NumStatus enum value	BaseDynInst< Impl >	protected
numVecDestRegs() const	BaseDynInst< Impl >	inline
numVecElemDestRegs() const	BaseDynInst< Impl >	inline
NumVecElemPerVecReg	BaseO3DynInst< Impl >	static
numVecPredDestRegs() const	BaseDynInst< Impl >	inline
O3CPU typedef	BaseO3DynInst< Impl >
opClass() const	BaseDynInst< Impl >	inline
operator=(const RefCounted &)	RefCounted	private
pc	BaseDynInst< Impl >	protected
PCState typedef	ExecContext
pcState() const override	BaseDynInst< Impl >	inlinevirtual
pcState(const TheISA::PCState &val) override	BaseDynInst< Impl >	inlinevirtual
physEffAddr	BaseDynInst< Impl >
PinnedRegsRenamed enum value	BaseDynInst< Impl >	protected
PinnedRegsSquashDone enum value	BaseDynInst< Impl >	protected
PinnedRegsWritten enum value	BaseDynInst< Impl >	protected
popResult(InstResult dflt=InstResult())	BaseDynInst< Impl >	inline
PossibleLoadViolation enum value	BaseDynInst< Impl >	protected
possibleLoadViolation() const	BaseDynInst< Impl >	inline
possibleLoadViolation(bool f)	BaseDynInst< Impl >	inline
Predicate enum value	BaseDynInst< Impl >	protected
predInstAddr()	BaseDynInst< Impl >	inline
predMicroPC()	BaseDynInst< Impl >	inline
predNextInstAddr()	BaseDynInst< Impl >	inline
predPC	BaseDynInst< Impl >
PredTaken enum value	BaseDynInst< Impl >	protected
prevDestRegIdx(int idx) const	BaseDynInst< Impl >	inline
readCCRegOperand(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
readFloatRegOperandBits(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
readIntRegOperand(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())	ExecContext	inlinevirtual
readMemAccPredicate() const override	BaseDynInst< Impl >	inlinevirtual
readMiscReg(int misc_reg) override	BaseO3DynInst< Impl >	inlinevirtual
readMiscRegOperand(const StaticInst *si, int idx) override	BaseO3DynInst< Impl >	inlinevirtual
readPredicate() const override	BaseDynInst< Impl >	inlinevirtual
readPredTaken()	BaseDynInst< Impl >	inline
readPredTarg()	BaseDynInst< Impl >	inline
readStCondFailures() const override	BaseDynInst< Impl >	inlinevirtual
readVec16BitLaneOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVec32BitLaneOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVec64BitLaneOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVec8BitLaneOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVecElemOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVecPredRegOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readVecRegOperand(const StaticInst *si, int idx) const override	BaseO3DynInst< Impl >	inlinevirtual
readyRegs	BaseDynInst< Impl >
readyToCommit() const	BaseDynInst< Impl >	inline
readyToIssue() const	BaseDynInst< Impl >	inline
recordResult(bool f)	BaseDynInst< Impl >	inline
RecordResult enum value	BaseDynInst< Impl >	protected
RecoverInst enum value	BaseDynInst< Impl >	protected
RefCounted(const RefCounted &)	RefCounted	private
RefCounted()	RefCounted	inline
removeInLSQ()	BaseDynInst< Impl >	inline
renamedDestRegIdx(int idx) const	BaseDynInst< Impl >	inline
renameDestReg(int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)	BaseDynInst< Impl >	inline
renamedSrcRegIdx(int idx) const	BaseDynInst< Impl >	inline
renameSrcReg(int idx, PhysRegIdPtr renamed_src)	BaseDynInst< Impl >	inline
ReqMade enum value	BaseDynInst< Impl >	protected
reqToVerify	BaseDynInst< Impl >
requestorId() const	BaseDynInst< Impl >	inline
ResultReady enum value	BaseDynInst< Impl >	protected
resultSize()	BaseDynInst< Impl >	inline
RobEntry enum value	BaseDynInst< Impl >	protected
savedReq	BaseDynInst< Impl >
seqNum	BaseDynInst< Impl >
SerializeAfter enum value	BaseDynInst< Impl >	protected
SerializeBefore enum value	BaseDynInst< Impl >	protected
SerializeHandled enum value	BaseDynInst< Impl >	protected
setAtCommit()	BaseDynInst< Impl >	inline
setCanCommit()	BaseDynInst< Impl >	inline
setCanIssue()	BaseDynInst< Impl >	inline
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override	BaseO3DynInst< Impl >	inlinevirtual
setCommitted()	BaseDynInst< Impl >	inline
setCompleted()	BaseDynInst< Impl >	inline
setExecuted()	BaseDynInst< Impl >	inline
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override	BaseO3DynInst< Impl >	inlinevirtual
setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)	BaseDynInst< Impl >	inline
setInIQ()	BaseDynInst< Impl >	inline
setInLSQ()	BaseDynInst< Impl >	inline
setInROB()	BaseDynInst< Impl >	inline
setInstListIt(ListIt _instListIt)	BaseDynInst< Impl >	inline
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override	BaseO3DynInst< Impl >	inlinevirtual
setIssued()	BaseDynInst< Impl >	inline
setMemAccPredicate(bool val) override	BaseDynInst< Impl >	inlinevirtual
setMiscReg(int misc_reg, RegVal val) override	BaseO3DynInst< Impl >	inlinevirtual
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override	BaseO3DynInst< Impl >	inlinevirtual
setNotAnInst()	BaseDynInst< Impl >	inline
setPinnedRegsRenamed()	BaseDynInst< Impl >	inline
setPinnedRegsSquashDone()	BaseDynInst< Impl >	inline
setPinnedRegsWritten()	BaseDynInst< Impl >	inline
setPredicate(bool val) override	BaseDynInst< Impl >	inlinevirtual
setPredTaken(bool predicted_taken)	BaseDynInst< Impl >	inline
setPredTarg(const TheISA::PCState &_predPC)	BaseDynInst< Impl >	inline
setRequest()	BaseDynInst< Impl >	inline
setResultReady()	BaseDynInst< Impl >	inline
setScalarResult(T &&t)	BaseDynInst< Impl >	inline
setSerializeAfter()	BaseDynInst< Impl >	inline
setSerializeBefore()	BaseDynInst< Impl >	inline
setSerializeHandled()	BaseDynInst< Impl >	inline
setSquashed()	BaseDynInst< Impl >
setSquashedInIQ()	BaseDynInst< Impl >	inline
setSquashedInLSQ()	BaseDynInst< Impl >	inline
setSquashedInROB()	BaseDynInst< Impl >	inline
setStCondFailures(unsigned int sc_failures) override	BaseDynInst< Impl >	inlinevirtual
setThreadState(ImplState *state)	BaseDynInst< Impl >	inline
setTid(ThreadID tid)	BaseDynInst< Impl >	inline
setVecElemOperand(const StaticInst *si, int idx, const VecElem val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecElemResult(T &&t)	BaseDynInst< Impl >	inline
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecLaneOperandT(const StaticInst *si, int idx, const LD &val)	BaseO3DynInst< Impl >	inline
setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecPredResult(T &&t)	BaseDynInst< Impl >	inline
setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) override	BaseO3DynInst< Impl >	inlinevirtual
setVecResult(T &&t)	BaseDynInst< Impl >	inline
socketId() const	BaseDynInst< Impl >	inline
sqIdx	BaseDynInst< Impl >
sqIt	BaseDynInst< Impl >
SQIterator typedef	BaseDynInst< Impl >
Squashed enum value	BaseDynInst< Impl >	protected
SquashedInIQ enum value	BaseDynInst< Impl >	protected
SquashedInLSQ enum value	BaseDynInst< Impl >	protected
SquashedInROB enum value	BaseDynInst< Impl >	protected
srcRegIdx(int i) const	BaseDynInst< Impl >	inline
staticInst	BaseDynInst< Impl >
Status enum name	BaseDynInst< Impl >	protected
status	BaseDynInst< Impl >	private
strictlyOrdered() const	BaseDynInst< Impl >	inline
strictlyOrdered(bool so)	BaseDynInst< Impl >	inline
syscall() override	BaseO3DynInst< Impl >	virtual
tcBase() const override	BaseDynInst< Impl >	inlinevirtual
thread	BaseDynInst< Impl >
threadNumber	BaseDynInst< Impl >
ThreadsyncWait enum value	BaseDynInst< Impl >	protected
traceData	BaseDynInst< Impl >
TranslationCompleted enum value	BaseDynInst< Impl >	protected
translationCompleted() const	BaseDynInst< Impl >	inline
translationCompleted(bool f)	BaseDynInst< Impl >	inline
TranslationStarted enum value	BaseDynInst< Impl >	protected
translationStarted() const	BaseDynInst< Impl >	inline
translationStarted(bool f)	BaseDynInst< Impl >	inline
trap(const Fault &fault)	BaseO3DynInst< Impl >
updateMiscRegs()	BaseO3DynInst< Impl >	inline
VecElem typedef	BaseO3DynInst< Impl >
VecPredRegContainer typedef	BaseO3DynInst< Impl >
VecRegContainer typedef	BaseO3DynInst< Impl >
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override	BaseDynInst< Impl >
ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())=0	ExecContext	pure virtual
~BaseDynInst()	BaseDynInst< Impl >
~BaseO3DynInst()	BaseO3DynInst< Impl >
~RefCounted()	RefCounted	inlinevirtual