| _cacheLineSize | BaseCPU | protected |
| _cpuId | BaseCPU | protected |
| _dataRequestorId | BaseCPU | protected |
| _instRequestorId | BaseCPU | protected |
| _pid | BaseCPU | protected |
| _socketId | BaseCPU | protected |
| _status | FullO3CPU< O3CPUImpl > | |
| _switchedOut | BaseCPU | protected |
| _taskId | BaseCPU | protected |
| activateContext(ThreadID tid) override | FullO3CPU< O3CPUImpl > | virtual |
| activateStage(const StageIdx idx) | FullO3CPU< O3CPUImpl > | inline |
| activateThread(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| activeThreads | FullO3CPU< O3CPUImpl > | protected |
| activityRec | FullO3CPU< O3CPUImpl > | private |
| activityThisCycle() | FullO3CPU< O3CPUImpl > | inline |
| addInst(const DynInstPtr &inst) | FullO3CPU< O3CPUImpl > | |
| addressMonitor | BaseCPU | private |
| addThreadToExitingList(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| armMonitor(ThreadID tid, Addr address) | BaseCPU | |
| BaseCPU(Params *params, bool is_checker=false) | BaseCPU | |
| BaseO3CPU(BaseCPUParams *params) | BaseO3CPU | |
| Blocked enum value | FullO3CPU< O3CPUImpl > | |
| cacheLineSize() const | BaseCPU | inline |
| ccRegfileReads | FullO3CPU< O3CPUImpl > | |
| ccRegfileWrites | FullO3CPU< O3CPUImpl > | |
| checker | FullO3CPU< O3CPUImpl > | |
| checkInterrupts(ThreadID tid) const | BaseCPU | inline |
| cleanUpRemovedInsts() | FullO3CPU< O3CPUImpl > | |
| clearInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| clearInterrupts(ThreadID tid) | BaseCPU | inline |
| commit | FullO3CPU< O3CPUImpl > | protected |
| commitDrained(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| CommitIdx enum value | FullO3CPU< O3CPUImpl > | |
| commitRenameMap | FullO3CPU< O3CPUImpl > | protected |
| committedInsts | FullO3CPU< O3CPUImpl > | |
| committedOps | FullO3CPU< O3CPUImpl > | |
| contextToThread(ContextID cid) | BaseCPU | inline |
| cpi | FullO3CPU< O3CPUImpl > | |
| CPU_STATE_ON enum value | BaseCPU | protected |
| CPU_STATE_SLEEP enum value | BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | BaseCPU | protected |
| cpuId() const | BaseCPU | inline |
| cpuList | BaseCPU | privatestatic |
| CPUPolicy typedef | FullO3CPU< O3CPUImpl > | |
| CPUState enum name | BaseCPU | protected |
| cpuWaitList | FullO3CPU< O3CPUImpl > | |
| currentFunctionEnd | BaseCPU | private |
| currentFunctionStart | BaseCPU | private |
| dataRequestorId() const | BaseCPU | inline |
| deactivateStage(const StageIdx idx) | FullO3CPU< O3CPUImpl > | inline |
| deactivateThread(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| decode | FullO3CPU< O3CPUImpl > | protected |
| DecodeIdx enum value | FullO3CPU< O3CPUImpl > | |
| decodeQueue | FullO3CPU< O3CPUImpl > | |
| DecodeStruct typedef | FullO3CPU< O3CPUImpl > | |
| demapDataPage(Addr vaddr, uint64_t asn) | FullO3CPU< O3CPUImpl > | inline |
| demapInstPage(Addr vaddr, uint64_t asn) | FullO3CPU< O3CPUImpl > | inline |
| demapPage(Addr vaddr, uint64_t asn) | FullO3CPU< O3CPUImpl > | inline |
| DerivO3CPU(DerivO3CPUParams *p) | DerivO3CPU | inline |
| deschedulePowerGatingEvent() | BaseCPU | |
| drain() override | FullO3CPU< O3CPUImpl > | |
| drainResume() override | FullO3CPU< O3CPUImpl > | |
| drainSanityCheck() const | FullO3CPU< O3CPUImpl > | private |
| dtb | FullO3CPU< O3CPUImpl > | |
| dumpInsts() | FullO3CPU< O3CPUImpl > | |
| DynInstPtr typedef | FullO3CPU< O3CPUImpl > | |
| enableFunctionTrace() | BaseCPU | private |
| enterPwrGating() | BaseCPU | protected |
| enterPwrGatingEvent | BaseCPU | protected |
| exitingThreads | FullO3CPU< O3CPUImpl > | protected |
| exitThreads() | FullO3CPU< O3CPUImpl > | |
| fetch | FullO3CPU< O3CPUImpl > | protected |
| FetchIdx enum value | FullO3CPU< O3CPUImpl > | |
| fetchQueue | FullO3CPU< O3CPUImpl > | |
| FetchStruct typedef | FullO3CPU< O3CPUImpl > | |
| findContext(ThreadContext *tc) | BaseCPU | |
| flushTLBs() | BaseCPU | |
| fpRegfileReads | FullO3CPU< O3CPUImpl > | |
| fpRegfileWrites | FullO3CPU< O3CPUImpl > | |
| freeList | FullO3CPU< O3CPUImpl > | protected |
| FullO3CPU(DerivO3CPUParams *params) | FullO3CPU< O3CPUImpl > | |
| functionEntryTick | BaseCPU | private |
| functionTraceStream | BaseCPU | private |
| functionTracingEnabled | BaseCPU | private |
| getAndIncrementInstSeq() | FullO3CPU< O3CPUImpl > | inline |
| getContext(int tn) | BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | BaseCPU | |
| getDataPort() override | FullO3CPU< O3CPUImpl > | inlinevirtual |
| getFreeTid() | FullO3CPU< O3CPUImpl > | |
| getInstPort() override | FullO3CPU< O3CPUImpl > | inlinevirtual |
| getInterruptController(ThreadID tid) | BaseCPU | inline |
| getInterrupts() | FullO3CPU< O3CPUImpl > | |
| getPid() const | BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | BaseCPU | |
| getSendFunctional() | BaseCPU | inlinevirtual |
| getTracer() | BaseCPU | inline |
| getWritableArchVecPredReg(int reg_idx, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| getWritableArchVecReg(int reg_idx, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| getWritableVecPredReg(PhysRegIdPtr reg_idx) | FullO3CPU< O3CPUImpl > | |
| getWritableVecReg(PhysRegIdPtr reg_idx) | FullO3CPU< O3CPUImpl > | |
| globalSeqNum | FullO3CPU< O3CPUImpl > | |
| halt() | FullO3CPU< O3CPUImpl > | inline |
| haltContext(ThreadID tid) override | FullO3CPU< O3CPUImpl > | virtual |
| Halted enum value | FullO3CPU< O3CPUImpl > | |
| htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) | FullO3CPU< O3CPUImpl > | |
| Idle enum value | FullO3CPU< O3CPUImpl > | |
| idleCycles | FullO3CPU< O3CPUImpl > | |
| iew | FullO3CPU< O3CPUImpl > | protected |
| IEWIdx enum value | FullO3CPU< O3CPUImpl > | |
| iewQueue | FullO3CPU< O3CPUImpl > | |
| IEWStruct typedef | FullO3CPU< O3CPUImpl > | |
| ImplState typedef | FullO3CPU< O3CPUImpl > | |
| init() override | FullO3CPU< O3CPUImpl > | |
| insertThread(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| instAddr(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| instCnt | BaseCPU | protected |
| instCount() | BaseCPU | inline |
| instcount | FullO3CPU< O3CPUImpl > | |
| instDone(ThreadID tid, const DynInstPtr &inst) | FullO3CPU< O3CPUImpl > | |
| instList | FullO3CPU< O3CPUImpl > | |
| instRequestorId() const | BaseCPU | inline |
| interrupts | BaseCPU | protected |
| intRegfileReads | FullO3CPU< O3CPUImpl > | |
| intRegfileWrites | FullO3CPU< O3CPUImpl > | |
| invldPid | BaseCPU | static |
| ipc | FullO3CPU< O3CPUImpl > | |
| isa | FullO3CPU< O3CPUImpl > | protected |
| isCpuDrained() const | FullO3CPU< O3CPUImpl > | private |
| isDraining() const | FullO3CPU< O3CPUImpl > | inline |
| isThreadExiting(ThreadID tid) const | FullO3CPU< O3CPUImpl > | |
| itb | FullO3CPU< O3CPUImpl > | |
| lastActivatedCycle | FullO3CPU< O3CPUImpl > | |
| lastRunningCycle | FullO3CPU< O3CPUImpl > | |
| ListIt typedef | FullO3CPU< O3CPUImpl > | |
| LSQRequest typedef | FullO3CPU< O3CPUImpl > | |
| microPC(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| miscRegfileReads | FullO3CPU< O3CPUImpl > | |
| miscRegfileWrites | FullO3CPU< O3CPUImpl > | |
| mwait(ThreadID tid, PacketPtr pkt) | BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) | BaseCPU | |
| nextInstAddr(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| numActiveThreads() | FullO3CPU< O3CPUImpl > | inline |
| numContexts() | BaseCPU | inline |
| numCycles | BaseCPU | |
| numSimulatedCPUs() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| NumStages enum value | FullO3CPU< O3CPUImpl > | |
| numThreads | BaseCPU | |
| numWorkItemsCompleted | BaseCPU | |
| numWorkItemsStarted | BaseCPU | |
| O3CPU typedef | FullO3CPU< O3CPUImpl > | |
| Params typedef | BaseCPU | |
| params() const | BaseCPU | inline |
| PCMask | BaseCPU | static |
| pcState(const TheISA::PCState &newPCState, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| pcState(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| pmuProbePoint(const char *name) | BaseCPU | protected |
| postInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | |
| powerGatingOnIdle | BaseCPU | protected |
| ppActiveCycles | BaseCPU | protected |
| ppAllCycles | BaseCPU | protected |
| ppDataAccessComplete | FullO3CPU< O3CPUImpl > | |
| ppInstAccessComplete | FullO3CPU< O3CPUImpl > | |
| ppRetiredBranches | BaseCPU | protected |
| ppRetiredInsts | BaseCPU | protected |
| ppRetiredInstsPC | BaseCPU | protected |
| ppRetiredLoads | BaseCPU | protected |
| ppRetiredStores | BaseCPU | protected |
| ppSleeping | BaseCPU | protected |
| previousCycle | BaseCPU | protected |
| previousState | BaseCPU | protected |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | BaseCPU | virtual |
| processInterrupts(const Fault &interrupt) | FullO3CPU< O3CPUImpl > | |
| pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >()) | FullO3CPU< O3CPUImpl > | inline |
| pwrGatingLatency | BaseCPU | protected |
| quiesceCycles | FullO3CPU< O3CPUImpl > | |
| read(LSQRequest *req, int load_idx) | FullO3CPU< O3CPUImpl > | inline |
| readArchCCReg(int reg_idx, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| readArchFloatReg(int reg_idx, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| readArchIntReg(int reg_idx, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| readArchVecElem(const RegIndex ®_idx, const ElemIndex &ldx, ThreadID tid) const | FullO3CPU< O3CPUImpl > | |
| readArchVecLane(int reg_idx, int lId, ThreadID tid) const | FullO3CPU< O3CPUImpl > | inline |
| readArchVecPredReg(int reg_idx, ThreadID tid) const | FullO3CPU< O3CPUImpl > | |
| readArchVecReg(int reg_idx, ThreadID tid) const | FullO3CPU< O3CPUImpl > | |
| readCCReg(PhysRegIdPtr phys_reg) | FullO3CPU< O3CPUImpl > | |
| readFloatReg(PhysRegIdPtr phys_reg) | FullO3CPU< O3CPUImpl > | |
| readIntReg(PhysRegIdPtr phys_reg) | FullO3CPU< O3CPUImpl > | |
| readMiscReg(int misc_reg, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| readMiscRegNoEffect(int misc_reg, ThreadID tid) const | FullO3CPU< O3CPUImpl > | |
| readVecElem(PhysRegIdPtr reg_idx) const | FullO3CPU< O3CPUImpl > | |
| readVecLane(PhysRegIdPtr phys_reg) const | FullO3CPU< O3CPUImpl > | inline |
| readVecLane(PhysRegIdPtr phys_reg) const | FullO3CPU< O3CPUImpl > | inline |
| readVecPredReg(PhysRegIdPtr reg_idx) const | FullO3CPU< O3CPUImpl > | |
| readVecReg(PhysRegIdPtr reg_idx) const | FullO3CPU< O3CPUImpl > | |
| regFile | FullO3CPU< O3CPUImpl > | protected |
| registerThreadContexts() | BaseCPU | |
| regProbePoints() override | FullO3CPU< O3CPUImpl > | |
| regStats() override | FullO3CPU< O3CPUImpl > | |
| removeFrontInst(const DynInstPtr &inst) | FullO3CPU< O3CPUImpl > | |
| removeInstsNotInROB(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| removeInstsThisCycle | FullO3CPU< O3CPUImpl > | |
| removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| removeList | FullO3CPU< O3CPUImpl > | |
| removeThread(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| rename | FullO3CPU< O3CPUImpl > | protected |
| RenameIdx enum value | FullO3CPU< O3CPUImpl > | |
| renameMap | FullO3CPU< O3CPUImpl > | protected |
| renameQueue | FullO3CPU< O3CPUImpl > | |
| RenameStruct typedef | FullO3CPU< O3CPUImpl > | |
| rob | FullO3CPU< O3CPUImpl > | protected |
| Running enum value | FullO3CPU< O3CPUImpl > | |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | BaseCPU | |
| schedulePowerGatingEvent() | BaseCPU | |
| scheduleThreadExitEvent(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| scheduleTickEvent(Cycles delay) | FullO3CPU< O3CPUImpl > | inlineprivate |
| scoreboard | FullO3CPU< O3CPUImpl > | protected |
| serialize(CheckpointOut &cp) const override | BaseCPU | |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | FullO3CPU< O3CPUImpl > | virtual |
| setArchCCReg(int reg_idx, RegVal val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setArchIntReg(int reg_idx, RegVal val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setArchVecElem(const RegIndex ®_idx, const ElemIndex &ldx, const VecElem &val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD &val) | FullO3CPU< O3CPUImpl > | inline |
| setArchVecPredReg(int reg_idx, const VecPredRegContainer &val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setArchVecReg(int reg_idx, const VecRegContainer &val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setCCReg(PhysRegIdPtr phys_reg, RegVal val) | FullO3CPU< O3CPUImpl > | |
| setFloatReg(PhysRegIdPtr phys_reg, RegVal val) | FullO3CPU< O3CPUImpl > | |
| setIntReg(PhysRegIdPtr phys_reg, RegVal val) | FullO3CPU< O3CPUImpl > | |
| setMiscReg(int misc_reg, RegVal val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| setPid(uint32_t pid) | BaseCPU | inline |
| setVecElem(PhysRegIdPtr reg_idx, const VecElem &val) | FullO3CPU< O3CPUImpl > | |
| setVecLane(PhysRegIdPtr phys_reg, const LD &val) | FullO3CPU< O3CPUImpl > | inline |
| setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer &val) | FullO3CPU< O3CPUImpl > | |
| setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer &val) | FullO3CPU< O3CPUImpl > | |
| setVectorsAsReady(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| socketId() const | BaseCPU | inline |
| squashFromTC(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| squashInstIt(const ListIt &instIt, ThreadID tid) | FullO3CPU< O3CPUImpl > | inline |
| StageIdx enum name | FullO3CPU< O3CPUImpl > | |
| startup() override | FullO3CPU< O3CPUImpl > | |
| Status enum name | FullO3CPU< O3CPUImpl > | |
| suspendContext(ThreadID tid) override | FullO3CPU< O3CPUImpl > | virtual |
| SwitchedOut enum value | FullO3CPU< O3CPUImpl > | |
| switchedOut() const | BaseCPU | inline |
| switchOut() override | FullO3CPU< O3CPUImpl > | virtual |
| switchRenameMode(ThreadID tid, UnifiedFreeList *freelist) | FullO3CPU< O3CPUImpl > | |
| syscall(ThreadID tid) | FullO3CPU< O3CPUImpl > | |
| syscallRetryLatency | BaseCPU | |
| system | FullO3CPU< O3CPUImpl > | |
| takeOverFrom(BaseCPU *oldCPU) override | FullO3CPU< O3CPUImpl > | virtual |
| taskId() const | BaseCPU | inline |
| taskId(uint32_t id) | BaseCPU | inline |
| tcBase(ThreadID tid) | FullO3CPU< O3CPUImpl > | inline |
| Thread typedef | FullO3CPU< O3CPUImpl > | |
| thread | FullO3CPU< O3CPUImpl > | |
| threadContexts | BaseCPU | protected |
| threadExitEvent | FullO3CPU< O3CPUImpl > | private |
| threadMap | FullO3CPU< O3CPUImpl > | |
| tick() | FullO3CPU< O3CPUImpl > | |
| tickEvent | FullO3CPU< O3CPUImpl > | private |
| tids | FullO3CPU< O3CPUImpl > | |
| timeBuffer | FullO3CPU< O3CPUImpl > | |
| timesIdled | FullO3CPU< O3CPUImpl > | |
| TimeStruct typedef | FullO3CPU< O3CPUImpl > | |
| totalCpi | FullO3CPU< O3CPUImpl > | |
| totalInsts() const override | FullO3CPU< O3CPUImpl > | |
| BaseO3CPU::totalInsts() const =0 | BaseCPU | pure virtual |
| totalIpc | FullO3CPU< O3CPUImpl > | |
| totalOps() const override | FullO3CPU< O3CPUImpl > | |
| BaseO3CPU::totalOps() const =0 | BaseCPU | pure virtual |
| traceFunctions(Addr pc) | BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | BaseCPU | private |
| tracer | BaseCPU | protected |
| trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst) | FullO3CPU< O3CPUImpl > | |
| tryDrain() | FullO3CPU< O3CPUImpl > | private |
| unscheduleTickEvent() | FullO3CPU< O3CPUImpl > | inlineprivate |
| unserialize(CheckpointIn &cp) override | BaseCPU | |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | FullO3CPU< O3CPUImpl > | virtual |
| updateCycleCounters(CPUState state) | BaseCPU | inlineprotected |
| updateThreadPriority() | FullO3CPU< O3CPUImpl > | |
| VecElem typedef | FullO3CPU< O3CPUImpl > | |
| vecMode | FullO3CPU< O3CPUImpl > | protected |
| VecPredRegContainer typedef | FullO3CPU< O3CPUImpl > | |
| vecPredRegfileReads | FullO3CPU< O3CPUImpl > | mutable |
| vecPredRegfileWrites | FullO3CPU< O3CPUImpl > | |
| VecRegContainer typedef | FullO3CPU< O3CPUImpl > | |
| vecRegfileReads | FullO3CPU< O3CPUImpl > | mutable |
| vecRegfileWrites | FullO3CPU< O3CPUImpl > | |
| vecRenameMode() const | FullO3CPU< O3CPUImpl > | inline |
| vecRenameMode(Enums::VecRegRenameMode vec_mode) | FullO3CPU< O3CPUImpl > | inline |
| verifyMemoryMode() const override | FullO3CPU< O3CPUImpl > | |
| BaseO3CPU::verifyMemoryMode() const | BaseCPU | inlinevirtual |
| waitForRemoteGDB() const | BaseCPU | |
| wakeCPU() | FullO3CPU< O3CPUImpl > | |
| wakeup(ThreadID tid) override | FullO3CPU< O3CPUImpl > | virtual |
| workItemBegin() | BaseCPU | inline |
| workItemEnd() | BaseCPU | inline |
| write(LSQRequest *req, uint8_t *data, int store_idx) | FullO3CPU< O3CPUImpl > | inline |
| ~BaseCPU() | BaseCPU | virtual |
| ~FullO3CPU() | FullO3CPU< O3CPUImpl > | |