| _cacheLineSize | BaseCPU | protected |
| _cpuId | BaseCPU | protected |
| _dataRequestorId | BaseCPU | protected |
| _instRequestorId | BaseCPU | protected |
| _pid | BaseCPU | protected |
| _socketId | BaseCPU | protected |
| _status | BaseSimpleCPU | protected |
| _switchedOut | BaseCPU | protected |
| _taskId | BaseCPU | protected |
| activateContext(ThreadID thread_num) override | TimingSimpleCPU | virtual |
| activeThreads | BaseSimpleCPU | |
| addressMonitor | BaseCPU | private |
| advanceInst(const Fault &fault) | TimingSimpleCPU | |
| advancePC(const Fault &fault) | BaseSimpleCPU | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | BaseSimpleCPU | inlinevirtual |
| armMonitor(ThreadID tid, Addr address) | BaseCPU | |
| BaseCPU(Params *params, bool is_checker=false) | BaseCPU | |
| BaseSimpleCPU(BaseSimpleCPUParams *params) | BaseSimpleCPU | |
| branchPred | BaseSimpleCPU | protected |
| buildPacket(const RequestPtr &req, bool read) | TimingSimpleCPU | private |
| buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| cacheLineSize() const | BaseCPU | inline |
| checker | BaseSimpleCPU | |
| checkForInterrupts() | BaseSimpleCPU | |
| checkInterrupts(ThreadID tid) const | BaseCPU | inline |
| checkPcEventQueue() | BaseSimpleCPU | protected |
| clearInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| clearInterrupts(ThreadID tid) | BaseCPU | inline |
| completeDataAccess(PacketPtr pkt) | TimingSimpleCPU | |
| completeIfetch(PacketPtr) | TimingSimpleCPU | |
| contextToThread(ContextID cid) | BaseCPU | inline |
| countInst() | BaseSimpleCPU | |
| CPU_STATE_ON enum value | BaseCPU | protected |
| CPU_STATE_SLEEP enum value | BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | BaseCPU | protected |
| cpuId() const | BaseCPU | inline |
| cpuList | BaseCPU | privatestatic |
| CPUState enum name | BaseCPU | protected |
| curMacroStaticInst | BaseSimpleCPU | |
| currentFunctionEnd | BaseCPU | private |
| currentFunctionStart | BaseCPU | private |
| curStaticInst | BaseSimpleCPU | |
| curThread | BaseSimpleCPU | protected |
| dataRequestorId() const | BaseCPU | inline |
| dcache_pkt | TimingSimpleCPU | private |
| dcachePort | TimingSimpleCPU | private |
| DcacheRetry enum value | BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| deschedulePowerGatingEvent() | BaseCPU | |
| drain() override | TimingSimpleCPU | |
| drainResume() override | TimingSimpleCPU | |
| DTBWaitResponse enum value | BaseSimpleCPU | protected |
| enableFunctionTrace() | BaseCPU | private |
| enterPwrGating() | BaseCPU | protected |
| enterPwrGatingEvent | BaseCPU | protected |
| Faulting enum value | BaseSimpleCPU | protected |
| fetch() | TimingSimpleCPU | |
| fetchEvent | TimingSimpleCPU | private |
| fetchTranslation | TimingSimpleCPU | private |
| findContext(ThreadContext *tc) | BaseCPU | |
| finishTranslation(WholeTranslationState *state) | TimingSimpleCPU | |
| flushTLBs() | BaseCPU | |
| functionEntryTick | BaseCPU | private |
| functionTraceStream | BaseCPU | private |
| functionTracingEnabled | BaseCPU | private |
| getContext(int tn) | BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | BaseCPU | |
| getDataPort() override | TimingSimpleCPU | inlineprotectedvirtual |
| getInstPort() override | TimingSimpleCPU | inlineprotectedvirtual |
| getInterruptController(ThreadID tid) | BaseCPU | inline |
| getPid() const | BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | BaseCPU | |
| getSendFunctional() | BaseCPU | inlinevirtual |
| getTracer() | BaseCPU | inline |
| haltContext(ThreadID thread_num) override | BaseSimpleCPU | virtual |
| handleReadPacket(PacketPtr pkt) | TimingSimpleCPU | private |
| handleWritePacket() | TimingSimpleCPU | private |
| htmSendAbortSignal(HtmFailureFaultCause) override | TimingSimpleCPU | virtual |
| icachePort | TimingSimpleCPU | private |
| IcacheRetry enum value | BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| Idle enum value | BaseSimpleCPU | protected |
| ifetch_pkt | TimingSimpleCPU | private |
| init() override | TimingSimpleCPU | |
| initiateHtmCmd(Request::Flags flags) override | TimingSimpleCPU | virtual |
| initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | TimingSimpleCPU | virtual |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override | TimingSimpleCPU | virtual |
| inst | BaseSimpleCPU | |
| instCnt | BaseCPU | protected |
| instCount() | BaseCPU | inline |
| instRequestorId() const | BaseCPU | inline |
| interrupts | BaseCPU | protected |
| invldPid | BaseCPU | static |
| isCpuDrained() const | TimingSimpleCPU | inlineprivate |
| isSquashed() const | TimingSimpleCPU | inline |
| ITBWaitResponse enum value | BaseSimpleCPU | protected |
| mwait(ThreadID tid, PacketPtr pkt) | BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) | BaseCPU | |
| numContexts() | BaseCPU | inline |
| numCycles | BaseCPU | |
| numSimulatedCPUs() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numThreads | BaseCPU | |
| numWorkItemsCompleted | BaseCPU | |
| numWorkItemsStarted | BaseCPU | |
| Params typedef | BaseCPU | |
| params() const | BaseCPU | inline |
| PCMask | BaseCPU | static |
| pmuProbePoint(const char *name) | BaseCPU | protected |
| postExecute() | BaseSimpleCPU | |
| postInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | |
| powerGatingOnIdle | BaseCPU | protected |
| ppActiveCycles | BaseCPU | protected |
| ppAllCycles | BaseCPU | protected |
| ppRetiredBranches | BaseCPU | protected |
| ppRetiredInsts | BaseCPU | protected |
| ppRetiredInstsPC | BaseCPU | protected |
| ppRetiredLoads | BaseCPU | protected |
| ppRetiredStores | BaseCPU | protected |
| ppSleeping | BaseCPU | protected |
| preExecute() | BaseSimpleCPU | |
| previousCycle | TimingSimpleCPU | private |
| previousState | BaseCPU | protected |
| printAddr(Addr a) | TimingSimpleCPU | |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | BaseCPU | virtual |
| pwrGatingLatency | BaseCPU | protected |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | BaseSimpleCPU | inlinevirtual |
| registerThreadContexts() | BaseCPU | |
| regProbePoints() override | BaseCPU | |
| regStats() override | BaseSimpleCPU | |
| resetStats() override | BaseSimpleCPU | |
| Running enum value | BaseSimpleCPU | protected |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | BaseCPU | |
| schedulePowerGatingEvent() | BaseCPU | |
| sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read) | TimingSimpleCPU | private |
| sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc) | TimingSimpleCPU | |
| sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| serialize(CheckpointOut &cp) const override | BaseCPU | |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | BaseSimpleCPU | virtual |
| setPid(uint32_t pid) | BaseCPU | inline |
| setupFetchRequest(const RequestPtr &req) | BaseSimpleCPU | |
| socketId() const | BaseCPU | inline |
| startup() override | BaseCPU | |
| Status enum name | BaseSimpleCPU | protected |
| suspendContext(ThreadID thread_num) override | TimingSimpleCPU | virtual |
| swapActiveThread() | BaseSimpleCPU | protected |
| switchedOut() const | BaseCPU | inline |
| switchOut() override | TimingSimpleCPU | virtual |
| syscallRetryLatency | BaseCPU | |
| system | BaseCPU | |
| takeOverFrom(BaseCPU *oldCPU) override | TimingSimpleCPU | virtual |
| taskId() const | BaseCPU | inline |
| taskId(uint32_t id) | BaseCPU | inline |
| threadContexts | BaseCPU | protected |
| threadInfo | BaseSimpleCPU | |
| threadSnoop(PacketPtr pkt, ThreadID sender) | TimingSimpleCPU | private |
| TimingSimpleCPU(TimingSimpleCPUParams *params) | TimingSimpleCPU | |
| totalInsts() const override | BaseSimpleCPU | virtual |
| totalOps() const override | BaseSimpleCPU | virtual |
| traceData | BaseSimpleCPU | |
| traceFault() | BaseSimpleCPU | protected |
| traceFunctions(Addr pc) | BaseCPU | inline |
| traceFunctionsInternal(Addr pc) | BaseCPU | private |
| tracer | BaseCPU | protected |
| translationFault(const Fault &fault) | TimingSimpleCPU | private |
| tryCompleteDrain() | TimingSimpleCPU | private |
| unserialize(CheckpointIn &cp) override | BaseCPU | |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | BaseSimpleCPU | virtual |
| updateCycleCounters(CPUState state) | BaseCPU | inlineprotected |
| updateCycleCounts() | TimingSimpleCPU | private |
| verifyMemoryMode() const override | TimingSimpleCPU | virtual |
| waitForRemoteGDB() const | BaseCPU | |
| wakeup(ThreadID tid) override | BaseSimpleCPU | virtual |
| workItemBegin() | BaseCPU | inline |
| workItemEnd() | BaseCPU | inline |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override | TimingSimpleCPU | virtual |
| ~BaseCPU() | BaseCPU | virtual |
| ~BaseSimpleCPU() | BaseSimpleCPU | virtual |
| ~TimingSimpleCPU() | TimingSimpleCPU | virtual |