#include <timing.hh>

Inheritance diagram for TimingSimpleCPU:

Classes
class	DcachePort

class	FetchTranslation

class	IcachePort

struct	IprEvent

class	SplitFragmentSenderState

class	SplitMainSenderState

class	TimingCPUPort
	A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle. More...

Public Member Functions
	TimingSimpleCPU (TimingSimpleCPUParams *params)

virtual	~TimingSimpleCPU ()

void	init () override

DrainState	drain () override

void	drainResume () override

void	switchOut () override
	Prepare for another CPU to take over execution. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU. More...

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active. More...

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended. More...

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

void	fetch ()

void	sendFetch (const Fault &fault, const RequestPtr &req, ThreadContext *tc)

void	completeIfetch (PacketPtr)

void	completeDataAccess (PacketPtr pkt)

void	advanceInst (const Fault &fault)

bool	isSquashed () const
	This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed. More...

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging). More...

void	finishTranslation (WholeTranslationState *state)
	Finish a DTB translation. More...

Fault	initiateHtmCmd (Request::Flags flags) override
	hardware transactional memory More...

void	htmSendAbortSignal (HtmFailureFaultCause) override
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...

Public Member Functions inherited from BaseSimpleCPU
	BaseSimpleCPU (BaseSimpleCPUParams *params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	init () override

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted. More...

void	regStats () override

void	resetStats () override

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

Public Member Functions inherited from BaseCPU
virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override

void	startup () override

void	regStats () override

void	regProbePoints () override

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Protected Member Functions
Port &	getDataPort () override
	Return a reference to the data port. More...

Port &	getInstPort () override
	Return a reference to the instruction port. More...

Protected Member Functions inherited from BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

void	traceFault ()
	Handler used when encountering a fault; its purpose is to tear down the InstRecord. More...

Protected Member Functions inherited from BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Private Member Functions
void	threadSnoop (PacketPtr pkt, ThreadID sender)

void	sendData (const RequestPtr &req, uint8_t data, uint64_t res, bool read)

void	sendSplitData (const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

void	translationFault (const Fault &fault)

PacketPtr	buildPacket (const RequestPtr &req, bool read)

void	buildSplitPacket (PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

bool	handleReadPacket (PacketPtr pkt)

bool	handleWritePacket ()

void	updateCycleCounts ()

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

bool	tryCompleteDrain ()
	Try to complete a drain request. More...

Private Attributes
FetchTranslation	fetchTranslation

IcachePort	icachePort

DcachePort	dcachePort

PacketPtr	ifetch_pkt

PacketPtr	dcache_pkt

Cycles	previousCycle

EventFunctionWrapper	fetchEvent

Additional Inherited Members
Public Types inherited from BaseCPU
typedef BaseCPUParams	Params

Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Public Attributes inherited from BaseSimpleCPU
Trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

TheISA::MachInst	inst
	Current instruction. More...

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Static Public Attributes inherited from BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Types inherited from BaseSimpleCPU
enum	Status { Idle, Running, Faulting, ITBWaitResponse, IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse, DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch }

Protected Types inherited from BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Attributes inherited from BaseSimpleCPU
ThreadID	curThread

BPredUnit *	branchPred

Status	_status

Protected Attributes inherited from BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Detailed Description

Definition at line 49 of file timing.hh.

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

TimingSimpleCPU::TimingSimpleCPU ( TimingSimpleCPUParams * params )

Definition at line 77 of file timing.cc.

References fetch().

◆ ~TimingSimpleCPU()

TimingSimpleCPU::~TimingSimpleCPU ( )

virtual

Definition at line 87 of file timing.cc.

Member Function Documentation

◆ activateContext()

void TimingSimpleCPU::activateContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now active.

Reimplemented from BaseCPU.

Definition at line 211 of file timing.cc.

References BaseSimpleCPU::_status, BaseCPU::activateContext(), BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), and BaseSimpleCPU::threadInfo.

◆ advanceInst()

void TimingSimpleCPU::advanceInst ( const Fault & fault )

◆ buildPacket()

PacketPtr TimingSimpleCPU::buildPacket	(	const RequestPtr &	req,
		bool	read
	)

private

Definition at line 415 of file timing.cc.

References Packet::createRead(), and Packet::createWrite().

Referenced by buildSplitPacket(), and sendData().

◆ buildSplitPacket()

void TimingSimpleCPU::buildSplitPacket	(	PacketPtr &	pkt1,
		PacketPtr &	pkt2,
		const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read
	)

private

Definition at line 421 of file timing.cc.

References buildPacket(), Packet::cmd, data, Packet::dataDynamic(), Packet::dataStatic(), Request::NO_ACCESS, MemCmd::responseCommand(), and Packet::senderState.

Referenced by sendSplitData().

◆ completeDataAccess()

void TimingSimpleCPU::completeDataAccess ( PacketPtr pkt )

Definition at line 945 of file timing.cc.

References BaseSimpleCPU::_status, advanceInst(), TimingSimpleCPU::SplitFragmentSenderState::bigPkt, StaticInst::completeAcc(), BaseSimpleCPU::countInst(), BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curStaticInst, BaseSimpleCPU::curThread, BaseSimpleCPU::DcacheWaitResponse, DPRINTF, BaseSimpleCPU::DTBWaitResponse, FAIL_REMOTE, FAIL_SELF, Packet::getHtmTransactionFailedInCacheRC(), SimpleExecContext::getHtmTransactionUid(), Packet::getHtmTransactionUid(), htmFailureToStr(), Packet::htmTransactionFailedInCache(), SimpleThread::htmTransactionStops, SimpleExecContext::inHtmTransactionalState(), Packet::isError(), StaticInst::isHtmStop(), Packet::isHtmTransactional(), Packet::isWrite(), MEMORY, Request::NO_ACCESS, NoFault, TimingSimpleCPU::SplitMainSenderState::outstanding, panic, BaseSimpleCPU::postExecute(), Packet::req, BaseSimpleCPU::Running, Packet::senderState, Packet::setHtmTransactional(), Packet::setHtmTransactionFailedInCache(), SIZE, SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, BaseSimpleCPU::traceFault(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by TimingSimpleCPU::DcachePort::DTickEvent::process(), sendData(), and sendSplitData().

◆ completeIfetch()

void TimingSimpleCPU::completeIfetch ( PacketPtr pkt )

Definition at line 822 of file timing.cc.

References BaseSimpleCPU::_status, advanceInst(), BaseSimpleCPU::countInst(), BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curStaticInst, BaseSimpleCPU::curThread, DPRINTF, StaticInst::execute(), Packet::getAddr(), SimpleThread::htmTransactionStarts, BaseSimpleCPU::IcacheWaitResponse, SimpleExecContext::inHtmTransactionalState(), StaticInst::initiateAcc(), BaseCPU::instCnt, Packet::isError(), StaticInst::isFirstMicroop(), StaticInst::isHtmStart(), StaticInst::isMemRef(), StaticInst::isMicroop(), SimpleExecContext::newHtmTransactionUid(), NoFault, BaseSimpleCPU::postExecute(), BaseSimpleCPU::preExecute(), Packet::req, BaseSimpleCPU::Running, SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, BaseSimpleCPU::traceFault(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by fetch(), and TimingSimpleCPU::IcachePort::ITickEvent::process().

◆ drain()

DrainState TimingSimpleCPU::drain ( )

override

Definition at line 92 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, BaseCPU::deschedulePowerGatingEvent(), DPRINTF, Drained, Draining, fetchEvent, BaseSimpleCPU::Idle, isCpuDrained(), BaseSimpleCPU::Running, Event::scheduled(), and BaseCPU::switchedOut().

◆ drainResume()

void TimingSimpleCPU::drainResume ( )

override

Definition at line 119 of file timing.cc.

References BaseSimpleCPU::_status, ThreadContext::Active, BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::schedulePowerGatingEvent(), BaseCPU::switchedOut(), BaseCPU::system, BaseCPU::threadContexts, BaseSimpleCPU::threadInfo, System::totalNumInsts, and verifyMemoryMode().

◆ fetch()

void TimingSimpleCPU::fetch ( )

◆ finishTranslation()

void TimingSimpleCPU::finishTranslation ( WholeTranslationState * state )

Finish a DTB translation.

Parameters

state The DTB translation state.

Definition at line 657 of file timing.cc.

References BaseSimpleCPU::_status, WholeTranslationState::data, WholeTranslationState::deleteReqs(), WholeTranslationState::getFault(), WholeTranslationState::isPrefetch(), WholeTranslationState::isSplit, WholeTranslationState::mainReq, WholeTranslationState::mode, NoFault, BaseTLB::Read, WholeTranslationState::res, BaseSimpleCPU::Running, sendData(), sendSplitData(), WholeTranslationState::setNoFault(), WholeTranslationState::sreqHigh, WholeTranslationState::sreqLow, and translationFault().

◆ getDataPort()

Port& TimingSimpleCPU::getDataPort ( )

inlineoverrideprotectedvirtual

Return a reference to the data port.

Implements BaseCPU.

Definition at line 265 of file timing.hh.

References dcachePort.

◆ getInstPort()

Port& TimingSimpleCPU::getInstPort ( )

inlineoverrideprotectedvirtual

Return a reference to the instruction port.

Implements BaseCPU.

Definition at line 268 of file timing.hh.

References icachePort.

◆ handleReadPacket()

bool TimingSimpleCPU::handleReadPacket ( PacketPtr pkt )

private

Definition at line 265 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::curThread, dcache_pkt, dcachePort, BaseSimpleCPU::DcacheRetry, BaseSimpleCPU::DcacheWaitResponse, SimpleThread::getTC(), ArmISA::handleLockedRead(), Packet::isRead(), Packet::req, RequestPort::sendTimingReq(), SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

◆ handleWritePacket()

bool TimingSimpleCPU::handleWritePacket ( )

private

Definition at line 507 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::curThread, dcache_pkt, dcachePort, BaseSimpleCPU::DcacheRetry, BaseSimpleCPU::DcacheWaitResponse, SimpleThread::getTC(), Packet::req, RequestPort::sendTimingReq(), SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

◆ htmSendAbortSignal()

void TimingSimpleCPU::htmSendAbortSignal ( HtmFailureFaultCause cause )

overridevirtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Implements BaseSimpleCPU.

Definition at line 1263 of file timing.cc.

References addr, SimpleThread::contextId(), BaseSimpleCPU::curThread, data, BaseCPU::dataRequestorId(), Request::HTM_ABORT, SimpleThread::instAddr(), SimpleExecContext::numInst, MipsISA::pc, Request::PHYSICAL, sendData(), Trace::InstRecord::setMem(), Request::STRICT_ORDER, BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, and BaseSimpleCPU::traceData.

◆ init()

void TimingSimpleCPU::init ( )

override

Definition at line 65 of file timing.cc.

References BaseSimpleCPU::init().

◆ initiateHtmCmd()

Fault TimingSimpleCPU::initiateHtmCmd ( Request::Flags flags )

overridevirtual

hardware transactional memory

Implements BaseSimpleCPU.

Definition at line 1218 of file timing.cc.

References addr, SimpleThread::contextId(), BaseSimpleCPU::curThread, data, BaseCPU::dataRequestorId(), DPRINTF, SimpleExecContext::getHtmTransactionUid(), SimpleThread::instAddr(), NoFault, SimpleExecContext::numInst, panic, MipsISA::pc, sendData(), Trace::InstRecord::setMem(), BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, and BaseSimpleCPU::traceData.

◆ initiateMemAMO()

Fault TimingSimpleCPU::initiateMemAMO	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

overridevirtual

◆ initiateMemRead()

Fault TimingSimpleCPU::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

◆ isCpuDrained()

bool TimingSimpleCPU::isCpuDrained ( ) const

inlineprivate

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
Stay at PC is true.
A fetch event is scheduled. Normally this would never be the case with microPC() == 0, but right after a context is activated it can happen.

Definition at line 356 of file timing.hh.

References BaseSimpleCPU::curThread, fetchEvent, SimpleThread::microPC(), Event::scheduled(), SimpleExecContext::stayAtPC, SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by drain(), and tryCompleteDrain().

◆ isSquashed()

bool TimingSimpleCPU::isSquashed ( ) const

inline

This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

This always returns false for the simple timing CPU as it never executes any instructions speculatively. @ return Is the current instruction squashed?

Definition at line 309 of file timing.hh.

◆ printAddr()

void TimingSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 1212 of file timing.cc.

References ArmISA::a, dcachePort, and RequestPort::printAddr().

◆ sendData()

void TimingSimpleCPU::sendData	(	const RequestPtr &	req,
		uint8_t *	data,
		uint64_t *	res,
		bool	read
	)

private

◆ sendFetch()

void TimingSimpleCPU::sendFetch	(	const Fault &	fault,
		const RequestPtr &	req,
		ThreadContext *	tc
	)

Definition at line 726 of file timing.cc.

References BaseSimpleCPU::_status, advanceInst(), BaseCPU::CPU_STATE_ON, Packet::dataStatic(), DPRINTF, Packet::getAddr(), icachePort, BaseSimpleCPU::IcacheRetry, BaseSimpleCPU::IcacheWaitResponse, ifetch_pkt, BaseSimpleCPU::inst, NoFault, MemCmd::ReadReq, BaseSimpleCPU::Running, RequestPort::sendTimingReq(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by TimingSimpleCPU::FetchTranslation::finish().

◆ sendSplitData()

void TimingSimpleCPU::sendSplitData	(	const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read
	)

private

Definition at line 348 of file timing.cc.

References buildSplitPacket(), TimingSimpleCPU::SplitFragmentSenderState::clearFromParent(), completeDataAccess(), BaseSimpleCPU::curThread, data, dcache_pkt, SimpleExecContext::getHtmTransactionUid(), handleReadPacket(), handleWritePacket(), SimpleExecContext::inHtmTransactionalState(), Packet::makeResponse(), Request::NO_ACCESS, Packet::senderState, Packet::setHtmTransactional(), and BaseSimpleCPU::threadInfo.

Referenced by finishTranslation().

◆ suspendContext()

void TimingSimpleCPU::suspendContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented from BaseCPU.

Definition at line 235 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, BaseSimpleCPU::curThread, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::suspendContext(), and BaseSimpleCPU::threadInfo.

◆ switchOut()

void TimingSimpleCPU::switchOut ( )

overridevirtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented from BaseCPU.

Definition at line 172 of file timing.cc.

References BaseSimpleCPU::_status, BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curThread, fetchEvent, BaseSimpleCPU::Idle, SimpleExecContext::inHtmTransactionalState(), BaseSimpleCPU::Running, Event::scheduled(), SimpleExecContext::stayAtPC, BaseCPU::switchOut(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseCPU::updateCycleCounters(), and updateCycleCounts().

◆ takeOverFrom()

void TimingSimpleCPU::takeOverFrom ( BaseCPU * cpu )

overridevirtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from BaseCPU.

Definition at line 194 of file timing.cc.

References previousCycle, and BaseCPU::takeOverFrom().

◆ threadSnoop()

void TimingSimpleCPU::threadSnoop	(	PacketPtr	pkt,
		ThreadID	sender
	)

private

Definition at line 643 of file timing.cc.

References TimingSimpleCPU::DcachePort::cacheBlockMask, dcachePort, BaseCPU::getCpuAddrMonitor(), ArmISA::handleLockedSnoop(), BaseCPU::numThreads, BaseSimpleCPU::threadInfo, and BaseSimpleCPU::wakeup().

Referenced by sendData().

◆ translationFault()

void TimingSimpleCPU::translationFault ( const Fault & fault )

private

Definition at line 398 of file timing.cc.

References advanceInst(), BaseCPU::CPU_STATE_ON, NoFault, BaseSimpleCPU::postExecute(), BaseSimpleCPU::traceData, BaseSimpleCPU::traceFault(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by finishTranslation().

◆ tryCompleteDrain()

bool TimingSimpleCPU::tryCompleteDrain ( )

private

Try to complete a drain request.

Returns: true if the CPU is drained, false otherwise.

Definition at line 156 of file timing.cc.

References DPRINTF, Draining, and isCpuDrained().

Referenced by advanceInst().

◆ updateCycleCounts()

void TimingSimpleCPU::updateCycleCounts ( )

private

Definition at line 1081 of file timing.cc.

References BaseCPU::numCycles, and previousCycle.

Referenced by completeDataAccess(), completeIfetch(), fetch(), sendFetch(), switchOut(), and translationFault().

◆ verifyMemoryMode()

void TimingSimpleCPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from BaseCPU.

Definition at line 202 of file timing.cc.

References fatal, System::isTimingMode(), and BaseCPU::system.

Referenced by drainResume().

◆ writeMem()

Fault TimingSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

Member Data Documentation

◆ dcache_pkt

PacketPtr TimingSimpleCPU::dcache_pkt

private

Definition at line 258 of file timing.hh.

Referenced by handleReadPacket(), handleWritePacket(), TimingSimpleCPU::DcachePort::recvReqRetry(), sendData(), and sendSplitData().

◆ dcachePort

DcachePort TimingSimpleCPU::dcachePort

private

Definition at line 255 of file timing.hh.

Referenced by getDataPort(), handleReadPacket(), handleWritePacket(), printAddr(), sendData(), and threadSnoop().

◆ fetchEvent

EventFunctionWrapper TimingSimpleCPU::fetchEvent

private

Definition at line 330 of file timing.hh.

Referenced by activateContext(), advanceInst(), drain(), drainResume(), isCpuDrained(), suspendContext(), and switchOut().

◆ fetchTranslation

FetchTranslation TimingSimpleCPU::fetchTranslation

private

Definition at line 131 of file timing.hh.

Referenced by fetch().

◆ icachePort

IcachePort TimingSimpleCPU::icachePort

private

Definition at line 254 of file timing.hh.

Referenced by getInstPort(), and sendFetch().

◆ ifetch_pkt

PacketPtr TimingSimpleCPU::ifetch_pkt

private

Definition at line 257 of file timing.hh.

Referenced by TimingSimpleCPU::IcachePort::recvReqRetry(), and sendFetch().

◆ previousCycle

Cycles TimingSimpleCPU::previousCycle

private

Definition at line 260 of file timing.hh.

Referenced by takeOverFrom(), and updateCycleCounts().

The documentation for this class was generated from the following files:

cpu/simple/timing.hh
cpu/simple/timing.cc

Classes

Public Member Functions

Protected Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

◆ ~TimingSimpleCPU()

Member Function Documentation

◆ activateContext()

◆ advanceInst()

◆ buildPacket()

◆ buildSplitPacket()

◆ completeDataAccess()

◆ completeIfetch()

◆ drain()

◆ drainResume()

◆ fetch()

◆ finishTranslation()

◆ getDataPort()

◆ getInstPort()

◆ handleReadPacket()

◆ handleWritePacket()

◆ htmSendAbortSignal()

◆ init()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ isCpuDrained()

◆ isSquashed()

◆ printAddr()

◆ sendData()

◆ sendFetch()

◆ sendSplitData()

◆ suspendContext()

◆ switchOut()

◆ takeOverFrom()

◆ threadSnoop()

◆ translationFault()

◆ tryCompleteDrain()

◆ updateCycleCounts()

◆ verifyMemoryMode()

◆ writeMem()

Member Data Documentation

◆ dcache_pkt

◆ dcachePort

◆ fetchEvent

◆ fetchTranslation

◆ icachePort

◆ ifetch_pkt

◆ previousCycle