gem5  v20.1.0.0
compressed.hh
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
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29 
30 #ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
31 #define __ARCH_RISCV_INSTS_COMPRESSED_HH__
32 
33 #include <string>
34 
36 #include "cpu/static_inst.hh"
37 
38 namespace RiscvISA
39 {
40 
44 class CompRegOp : public RiscvStaticInst
45 {
46  protected:
47  using RiscvStaticInst::RiscvStaticInst;
48 
49  std::string generateDisassembly(
50  Addr pc, const Loader::SymbolTable *symtab) const override;
51 };
52 
53 }
54 
55 #endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
RiscvISA::CompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: compressed.cc:42
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
Loader::SymbolTable
Definition: symtab.hh:59
RiscvISA::CompRegOp
Base class for compressed operations that work only on registers.
Definition: compressed.hh:44
RiscvISA
Definition: fs_workload.cc:36
static_inst.hh
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:46

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