gem5
v20.1.0.0
arch
riscv
insts
compressed.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 RISC-V Foundation
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* Copyright (c) 2017 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/riscv/insts/compressed.hh
"
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#include <sstream>
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#include <string>
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#include "
arch/riscv/utility.hh
"
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#include "
cpu/static_inst.hh
"
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namespace
RiscvISA
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{
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std::string
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CompRegOp::generateDisassembly
(
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Addr
pc
,
const
Loader::SymbolTable
*symtab)
const
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{
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std::stringstream
ss
;
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ss
<<
mnemonic
<<
' '
<<
registerName
(
_destRegIdx
[0]) <<
", "
<<
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registerName
(
_srcRegIdx
[0]);
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return
ss
.str();
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}
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}
RiscvISA::CompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
compressed.cc:42
RiscvISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:240
Loader::SymbolTable
Definition:
symtab.hh:59
RiscvISA
Definition:
fs_workload.cc:36
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition:
static_inst.hh:250
StaticInst::_destRegIdx
RegId _destRegIdx[MaxInstDestRegs]
See destRegIdx().
Definition:
static_inst.hh:248
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition:
static_inst.hh:258
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
compressed.hh
RiscvISA::registerName
std::string registerName(RegId reg)
Definition:
utility.hh:139
utility.hh
RiscvISA::ss
Bitfield< 11, 8 > ss
Definition:
pra_constants.hh:254
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