gem5  v20.1.0.0
compressed.cc
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2017 The University of Virginia
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5  *
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28  */
29 
31 
32 #include <sstream>
33 #include <string>
34 
35 #include "arch/riscv/utility.hh"
36 #include "cpu/static_inst.hh"
37 
38 namespace RiscvISA
39 {
40 
41 std::string
43  Addr pc, const Loader::SymbolTable *symtab) const
44 {
45  std::stringstream ss;
46  ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
48  return ss.str();
49 }
50 
51 }
RiscvISA::CompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: compressed.cc:42
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
Loader::SymbolTable
Definition: symtab.hh:59
RiscvISA
Definition: fs_workload.cc:36
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition: static_inst.hh:250
StaticInst::_destRegIdx
RegId _destRegIdx[MaxInstDestRegs]
See destRegIdx().
Definition: static_inst.hh:248
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
compressed.hh
RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:139
utility.hh
RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:254

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