compute_unit.hh File Reference

#include <deque>
#include <map>
#include <unordered_set>
#include <vector>
#include "base/callback.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "config/the_gpu_isa.hh"
#include "enums/PrefetchType.hh"
#include "gpu-compute/comm.hh"
#include "gpu-compute/exec_stage.hh"
#include "gpu-compute/fetch_stage.hh"
#include "gpu-compute/global_memory_pipeline.hh"
#include "gpu-compute/hsa_queue_entry.hh"
#include "gpu-compute/local_memory_pipeline.hh"
#include "gpu-compute/register_manager.hh"
#include "gpu-compute/scalar_memory_pipeline.hh"
#include "gpu-compute/schedule_stage.hh"
#include "gpu-compute/scoreboard_check_stage.hh"
#include "mem/port.hh"
#include "mem/token_port.hh"
#include "sim/clocked_object.hh"

Go to the source code of this file.

Classes
class	WFBarrier
	WF barrier slots. More...
class	ComputeUnit
class	ComputeUnit::GMTokenPort
class	ComputeUnit::DataPort
	Data access Port. More...
struct	ComputeUnit::DataPort::SenderState
class	ComputeUnit::ScalarDataPort
struct	ComputeUnit::ScalarDataPort::SenderState
class	ComputeUnit::ScalarDataPort::MemReqEvent
class	ComputeUnit::SQCPort
struct	ComputeUnit::SQCPort::SenderState
class	ComputeUnit::DTLBPort
	Data TLB port. More...
struct	ComputeUnit::DTLBPort::SenderState
	SenderState is information carried along with the packet throughout the TLB hierarchy. More...
class	ComputeUnit::ScalarDTLBPort
struct	ComputeUnit::ScalarDTLBPort::SenderState
class	ComputeUnit::ITLBPort
struct	ComputeUnit::ITLBPort::SenderState
	SenderState is information carried along with the packet throughout the TLB hierarchy. More...
class	ComputeUnit::LDSPort
	the port intended to communicate between the CU and its LDS More...
class	ComputeUnit::LDSPort::SenderState
	SenderState is information carried along with the packet, esp. More...

Enumerations
enum	EXEC_POLICY { OLDEST = 0, RR }
enum	TLB_CACHE { TLB_MISS_CACHE_MISS = 0, TLB_MISS_CACHE_HIT, TLB_HIT_CACHE_MISS, TLB_HIT_CACHE_HIT }

Enumeration Type Documentation

EXEC_POLICY

enum EXEC_POLICY

Enumerator
OLDEST
RR

Definition at line 69 of file compute_unit.hh.

TLB_CACHE

enum TLB_CACHE

Enumerator
TLB_MISS_CACHE_MISS
TLB_MISS_CACHE_HIT
TLB_HIT_CACHE_MISS
TLB_HIT_CACHE_HIT

Definition at line 75 of file compute_unit.hh.