gem5
v20.1.0.0
systemc
tests
systemc
misc
synth
add_chain
data_gen.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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data_gen.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "
define.h
"
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/******************************************************************************/
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/*************************** data_gen Function **********************/
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/******************************************************************************/
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SC_MODULE
( DATA_GEN )
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{
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SC_HAS_PROCESS
( DATA_GEN );
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sc_in_clk
clk;
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/*** Input and Output Ports ***/
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const
sc_signal<bool>& ready;
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signal_bool_vector8
&
data
;
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sc_signal<int>&
addr
;
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/*** Constructor ***/
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DATA_GEN ( sc_module_name NAME,
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sc_clock& TICK_N,
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const
sc_signal<bool>& READY,
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signal_bool_vector8
& DATA,
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sc_signal<int>& ADDR )
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:
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ready (READY),
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data
(DATA),
// 8 bits
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addr
(ADDR)
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{
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clk (TICK_N);
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SC_CTHREAD
( entry, clk.neg() );
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}
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/*** Call to Process Functionality ***/
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void
entry();
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};
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void
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DATA_GEN::entry()
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{
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while
(
true
) {
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// WAIT FOR POSEDGE OF ready
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at_posedge
(ready);
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// CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED
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if
(
addr
.read() >
LIMIT
) {
// if(addr > LIMIT)
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break
;
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}
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// WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data
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// INCREMENT addr BY 1
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data
.write(
mem
[
addr
.read()]);
// data = mem[addr]
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addr
.write(
addr
.read() + 1);
// addr = addr + 1
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}
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}
data
const char data[]
Definition:
circlebuf.test.cc:42
LIMIT
#define LIMIT
Definition:
define.h:40
SC_MODULE
SC_MODULE(DATA_GEN)
Definition:
data_gen.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
define.h
sc_core::at_posedge
void at_posedge(const sc_signal_in_if< bool > &s)
Definition:
sc_module.cc:784
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
addr
ip6_addr_t addr
Definition:
inet.hh:423
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
mem
bool_vector8 mem[]
Definition:
reset_stim.h:43
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition:
common.h:43
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