gem5  v20.1.0.0
data_gen.h
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20 /*****************************************************************************
21 
22  data_gen.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "define.h"
39 
40 /******************************************************************************/
41 /*************************** data_gen Function **********************/
42 /******************************************************************************/
43 
44 SC_MODULE( DATA_GEN )
45 {
46  SC_HAS_PROCESS( DATA_GEN );
47 
48  sc_in_clk clk;
49 
50  /*** Input and Output Ports ***/
51  const sc_signal<bool>& ready;
53  sc_signal<int>& addr;
54 
55  /*** Constructor ***/
56  DATA_GEN ( sc_module_name NAME,
57  sc_clock& TICK_N,
58  const sc_signal<bool>& READY,
59  signal_bool_vector8& DATA,
60  sc_signal<int>& ADDR )
61 
62  :
63  ready (READY),
64  data (DATA), // 8 bits
65  addr (ADDR)
66 
67  {
68  clk (TICK_N);
69  SC_CTHREAD( entry, clk.neg() );
70  }
71 
72  /*** Call to Process Functionality ***/
73  void entry();
74 
75 };
76 
77 void
78 DATA_GEN::entry()
79 {
80 
81  while(true) {
82 
83 // WAIT FOR POSEDGE OF ready
84 
85  at_posedge(ready);
86 
87 // CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED
88 
89  if(addr.read() > LIMIT) { // if(addr > LIMIT)
90  break;
91  }
92 
93 // WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data
94 // INCREMENT addr BY 1
95 
96  data.write(mem[addr.read()]); // data = mem[addr]
97  addr.write(addr.read() + 1); // addr = addr + 1
98  }
99 
100 }
data
const char data[]
Definition: circlebuf.test.cc:42
LIMIT
#define LIMIT
Definition: define.h:40
SC_MODULE
SC_MODULE(DATA_GEN)
Definition: data_gen.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
define.h
sc_core::at_posedge
void at_posedge(const sc_signal_in_if< bool > &s)
Definition: sc_module.cc:784
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
addr
ip6_addr_t addr
Definition: inet.hh:423
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43

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