gem5  v20.1.0.0
dramsim2.hh
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37 
42 #ifndef __MEM_DRAMSIM2_HH__
43 #define __MEM_DRAMSIM2_HH__
44 
45 #include <queue>
46 #include <unordered_map>
47 
48 #include "mem/abstract_mem.hh"
49 #include "mem/dramsim2_wrapper.hh"
50 #include "mem/qport.hh"
51 #include "params/DRAMSim2.hh"
52 
53 class DRAMSim2 : public AbstractMemory
54 {
55  private:
56 
62  class MemoryPort : public ResponsePort
63  {
64 
65  private:
66 
68 
69  public:
70 
71  MemoryPort(const std::string& _name, DRAMSim2& _memory);
72 
73  protected:
74 
76 
77  void recvFunctional(PacketPtr pkt);
78 
79  bool recvTimingReq(PacketPtr pkt);
80 
81  void recvRespRetry();
82 
84 
85  };
86 
88 
93 
97  bool retryReq;
98 
102  bool retryResp;
103 
108 
115  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
116  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
117 
123  unsigned int nbrOutstandingReads;
124  unsigned int nbrOutstandingWrites;
125 
132 
133  unsigned int nbrOutstanding() const;
134 
142  void accessAndRespond(PacketPtr pkt);
143 
144  void sendResponse();
145 
150 
154  void tick();
155 
160 
165  std::unique_ptr<Packet> pendingDelete;
166 
167  public:
168 
169  typedef DRAMSim2Params Params;
170  DRAMSim2(const Params *p);
171 
179  void readComplete(unsigned id, uint64_t addr, uint64_t cycle);
180 
188  void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
189 
190  DrainState drain() override;
191 
192  Port &getPort(const std::string &if_name,
193  PortID idx=InvalidPortID) override;
194 
195  void init() override;
196  void startup() override;
197 
198  protected:
199 
201  void recvFunctional(PacketPtr pkt);
202  bool recvTimingReq(PacketPtr pkt);
203  void recvRespRetry();
204 
205 };
206 
207 #endif // __MEM_DRAMSIM2_HH__
dramsim2_wrapper.hh
DRAMSim2::responseQueue
std::deque< PacketPtr > responseQueue
Queue to hold response packets until we can send them back.
Definition: dramsim2.hh:131
ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:265
DRAMSim2::startTick
Tick startTick
Keep track of when the wrapper is started.
Definition: dramsim2.hh:107
DRAMSim2::accessAndRespond
void accessAndRespond(PacketPtr pkt)
When a packet is ready, use the "access()" method in AbstractMemory to actually create the response p...
Definition: dramsim2.cc:247
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:238
abstract_mem.hh
DRAMSim2::nbrOutstanding
unsigned int nbrOutstanding() const
Definition: dramsim2.cc:130
DRAMSim2::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: dramsim2.cc:75
DRAMSim2::nbrOutstandingWrites
unsigned int nbrOutstandingWrites
Definition: dramsim2.hh:124
DRAMSim2::sendResponse
void sendResponse()
Definition: dramsim2.cc:100
DRAMSim2::retryResp
bool retryResp
Are we waiting for a retry for sending a response.
Definition: dramsim2.hh:102
DRAMSim2::readComplete
void readComplete(unsigned id, uint64_t addr, uint64_t cycle)
Read completion callback.
Definition: dramsim2.cc:283
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
DRAMSim2::recvRespRetry
void recvRespRetry()
Definition: dramsim2.cc:237
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
DRAMSim2::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, DRAMSim2 &_memory)
Definition: dramsim2.cc:353
DRAMSim2::Params
DRAMSim2Params Params
Definition: dramsim2.hh:169
DRAMSim2::outstandingReads
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingReads
Keep track of what packets are outstanding per address, and do so separately for reads and writes.
Definition: dramsim2.hh:115
DRAMSim2::DRAMSim2
DRAMSim2(const Params *p)
Definition: dramsim2.cc:47
EventFunctionWrapper
Definition: eventq.hh:1101
DRAMSim2::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: dramsim2.cc:160
DRAMSim2::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: dramsim2.cc:367
DRAMSim2::tick
void tick()
Progress the controller one clock cycle.
Definition: dramsim2.cc:136
DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:71
AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:104
DRAMSim2::retryReq
bool retryReq
Is the connected port waiting for a retry from us.
Definition: dramsim2.hh:97
DRAMSim2::MemoryPort
The memory port has to deal with its own flow control to avoid having unbounded storage that is impli...
Definition: dramsim2.hh:62
DRAMSim2::port
MemoryPort port
Definition: dramsim2.hh:87
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
Clocked::cycle
Cycles cycle
Definition: clocked_object.hh:69
DRAMSim2
Definition: dramsim2.hh:53
DRAMSim2::sendResponseEvent
EventFunctionWrapper sendResponseEvent
Event to schedule sending of responses.
Definition: dramsim2.hh:149
DRAMSim2::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: dramsim2.cc:379
DRAMSim2::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: dramsim2.cc:151
DRAMSim2::MemoryPort::recvRespRetry
void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: dramsim2.cc:386
DRAMSim2::MemoryPort::memory
DRAMSim2 & memory
Definition: dramsim2.hh:67
DRAMSim2::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: dramsim2.cc:336
DRAMSim2::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: dramsim2.cc:91
qport.hh
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
std::deque
STL deque class.
Definition: stl.hh:44
DRAMSim2::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dramsim2.cc:346
addr
ip6_addr_t addr
Definition: inet.hh:423
DRAMSim2::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: dramsim2.cc:373
DRAMSim2::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: dramsim2.cc:174
AbstractMemory::Params
AbstractMemoryParams Params
Definition: abstract_mem.hh:207
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list< AddrRange >
DRAMSim2::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: dramsim2.hh:165
DRAMSim2::outstandingWrites
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingWrites
Definition: dramsim2.hh:116
DRAMSim2::writeComplete
void writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
Write completion callback.
Definition: dramsim2.cc:311
DRAMSim2::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: dramsim2.cc:359
DRAMSim2::nbrOutstandingReads
unsigned int nbrOutstandingReads
Count the number of outstanding transactions so that we can block any further requests until there is...
Definition: dramsim2.hh:123
DRAMSim2::tickEvent
EventFunctionWrapper tickEvent
Event to schedule clock ticks.
Definition: dramsim2.hh:159
DRAMSim2::wrapper
DRAMSim2Wrapper wrapper
The actual DRAMSim2 wrapper.
Definition: dramsim2.hh:92
DRAMSim2Wrapper
Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world...
Definition: dramsim2_wrapper.hh:67

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