gem5
v20.1.0.0
cpu
testers
traffic_gen
exit_gen.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
base/logging.hh
"
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#include "
base/trace.hh
"
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#include "debug/TrafficGen.hh"
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#include "
exit_gen.hh
"
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#include "
sim/sim_exit.hh
"
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void
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ExitGen::enter
()
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{
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DPRINTF
(
TrafficGen
,
"%s has encountered the exit state and will "
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"terminate the simulation.\n"
,
name
());
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exitSimLoop
(
name
() +
" has encountered the exit state and will "
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"terminate the simulation.\n"
);
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}
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PacketPtr
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ExitGen::getNextPacket
()
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{
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panic
(
"Simulation should have exited"
);
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return
NULL;
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}
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Tick
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ExitGen::nextPacketTick
(
bool
elastic,
Tick
delay)
const
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{
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return
MaxTick
;
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}
Tick
uint64_t Tick
Tick count type.
Definition:
types.hh:63
BaseGen::name
std::string name() const
Get the name, useful for DPRINTFs.
Definition:
base_gen.hh:100
sim_exit.hh
exit_gen.hh
DPRINTF
#define DPRINTF(x,...)
Definition:
trace.hh:234
exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition:
sim_events.cc:88
ExitGen::enter
void enter()
Enter this generator state.
Definition:
exit_gen.cc:45
ExitGen::nextPacketTick
Tick nextPacketTick(bool elastic, Tick delay) const
Determine the tick when the next packet is available.
Definition:
exit_gen.cc:61
ExitGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition:
exit_gen.cc:54
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition:
packet.hh:257
logging.hh
trace.hh
MaxTick
const Tick MaxTick
Definition:
types.hh:65
TrafficGen
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
Definition:
traffic_gen.hh:67
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition:
logging.hh:171
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