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v20.1.0.0
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arch
generic
tlb.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2011 ARM Limited
3
* All rights reserved.
4
*
5
* The license below extends only to copyright in the software and shall
6
* not be construed as granting a license to any other intellectual
7
* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
9
* licensed hereunder. You may use the software subject to the license
10
* terms below provided that you ensure that this notice is replicated
11
* unmodified and in its entirety in all distributions of the software,
12
* modified or unmodified, in source code or in binary form.
13
*
14
* Copyright (c) 2006 The Regents of The University of Michigan
15
* All rights reserved.
16
*
17
* Redistribution and use in source and binary forms, with or without
18
* modification, are permitted provided that the following conditions are
19
* met: redistributions of source code must retain the above copyright
20
* notice, this list of conditions and the following disclaimer;
21
* redistributions in binary form must reproduce the above copyright
22
* notice, this list of conditions and the following disclaimer in the
23
* documentation and/or other materials provided with the distribution;
24
* neither the name of the copyright holders nor the names of its
25
* contributors may be used to endorse or promote products derived from
26
* this software without specific prior written permission.
27
*
28
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
*/
40
41
#ifndef __ARCH_GENERIC_TLB_HH__
42
#define __ARCH_GENERIC_TLB_HH__
43
44
#include "
base/logging.hh
"
45
#include "
mem/request.hh
"
46
#include "
sim/sim_object.hh
"
47
48
class
ThreadContext
;
49
50
class
BaseTLB
:
public
SimObject
51
{
52
protected
:
53
BaseTLB
(
const
Params
*
p
) :
SimObject
(
p
) {}
54
55
public
:
56
57
enum
Mode
{
Read
,
Write
,
Execute
};
58
59
class
Translation
60
{
61
public
:
62
virtual
~Translation
()
63
{}
64
69
virtual
void
markDelayed
() = 0;
70
71
/*
72
* The memory for this object may be dynamically allocated, and it may
73
* be responsible for cleaning itself up which will happen in this
74
* function. Once it's called, the object is no longer valid.
75
*/
76
virtual
void
finish
(
const
Fault
&fault,
const
RequestPtr
&req,
77
ThreadContext
*tc,
Mode
mode
) = 0;
78
84
virtual
bool
squashed
()
const
{
return
false
; }
85
};
86
87
public
:
88
virtual
void
demapPage
(
Addr
vaddr
, uint64_t asn) = 0;
89
90
virtual
Fault
translateAtomic
(
91
const
RequestPtr
&req,
ThreadContext
*tc,
Mode
mode
) = 0;
92
virtual
void
translateTiming
(
93
const
RequestPtr
&req,
ThreadContext
*tc,
94
Translation *translation,
Mode
mode
) = 0;
95
virtual
Fault
96
translateFunctional
(
const
RequestPtr
&req,
ThreadContext
*tc,
Mode
mode
)
97
{
98
panic
(
"Not implemented.\n"
);
99
}
100
115
virtual
Fault
finalizePhysical
(
116
const
RequestPtr
&req,
ThreadContext
*tc,
Mode
mode
)
const
= 0;
117
121
virtual
void
flushAll
() = 0;
122
126
virtual
void
takeOverFrom
(
BaseTLB
*otlb) = 0;
127
137
virtual
Port
*
getTableWalkerPort
() {
return
NULL; }
138
139
void
memInvalidate
() {
flushAll
(); }
140
};
141
142
#endif // __ARCH_GENERIC_TLB_HH__
BaseTLB::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
BaseTLB::Translation::squashed
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition:
tlb.hh:84
SimObject::Params
SimObjectParams Params
Definition:
sim_object.hh:113
BaseTLB::Read
@ Read
Definition:
tlb.hh:57
BaseTLB::takeOverFrom
virtual void takeOverFrom(BaseTLB *otlb)=0
Take over from an old tlb context.
BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)=0
BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)=0
BaseTLB::Mode
Mode
Definition:
tlb.hh:57
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition:
request.hh:82
request.hh
BaseTLB
Definition:
tlb.hh:50
BaseTLB::memInvalidate
void memInvalidate()
Invalidate the contents of memory buffers.
Definition:
tlb.hh:139
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
sim_object.hh
Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:240
MipsISA::vaddr
vaddr
Definition:
pra_constants.hh:275
BaseTLB::BaseTLB
BaseTLB(const Params *p)
Definition:
tlb.hh:53
Port
Ports are used to interface objects to each other.
Definition:
port.hh:56
BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition:
tlb.hh:96
ArmISA::mode
Bitfield< 4, 0 > mode
Definition:
miscregs_types.hh:70
BaseTLB::Translation
Definition:
tlb.hh:59
BaseTLB::Translation::~Translation
virtual ~Translation()
Definition:
tlb.hh:62
BaseTLB::getTableWalkerPort
virtual Port * getTableWalkerPort()
Get the table walker port if present.
Definition:
tlb.hh:137
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
BaseTLB::Write
@ Write
Definition:
tlb.hh:57
BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
BaseTLB::Translation::markDelayed
virtual void markDelayed()=0
Signal that the translation has been delayed due to a hw page table walk.
logging.hh
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
BaseTLB::Execute
@ Execute
Definition:
tlb.hh:57
BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const =0
Do post-translation physical address finalization.
BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition:
logging.hh:171
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:92
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