gem5  v20.1.0.0
SimpleLTTarget_ext.h
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19 
20 #ifndef __SIMPLE_LT_TARGET2_H__
21 #define __SIMPLE_LT_TARGET2_H__
22 
23 #include "tlm.h"
24 #include "tlm_utils/simple_target_socket.h"
25 #include "my_extension.h"
26 
27 //#include <systemc>
28 #include <cassert>
29 #include <vector>
30 //#include <iostream>
31 
33 {
34 public:
36  typedef tlm::tlm_phase phase_type;
40 
41 public:
43 
44 public:
47  sc_core::sc_time invalidate_dmi_time = sc_core::sc_time(25, sc_core::SC_NS)) :
49  socket("socket")
50  {
51  // register nb_transport method
54 
56 
60  m_invalidate_dmi_time = invalidate_dmi_time;
61  }
62 
64  {
65  sc_assert(phase == tlm::BEGIN_REQ);
66 
67  my_extension* tmp_ext;
68  trans.get_extension(tmp_ext);
69  if (!tmp_ext)
70  {
71  std::cout << name() << ": ERROR, extension not present" << std::endl;
72  }
73  else
74  {
75  std::cout << name() << ": OK, extension data = "
76  << tmp_ext->m_data << std::endl;
77  }
78  sc_dt::uint64 address = trans.get_address();
79  sc_assert(address < 400);
80 
81  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
82  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
83  std::cout << name() << ": Received write request: A = 0x"
84  << std::hex << (unsigned int)address
85  << ", D = 0x" << data << std::dec
86  << " @ " << sc_core::sc_time_stamp() << std::endl;
87 
88  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
90 
91  } else {
92  std::cout << name() << ": Received read request: A = 0x"
93  << std::hex << (unsigned int)address << std::dec
94  << " @ " << sc_core::sc_time_stamp() << std::endl;
95 
96  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
98  }
99 
101 
102  trans.set_dmi_allowed(true);
103 
104  // LT target
105  // - always return true
106  // - not necessary to update phase (if true is returned)
107  return tlm::TLM_COMPLETED;
108  }
109 
110  unsigned int transport_dbg(transaction_type& r)
111  {
112  if (r.get_address() >= 400) return 0;
113 
114  unsigned int tmp = (int)r.get_address();
115  unsigned int num_bytes;
116  if (tmp + r.get_data_length() >= 400) {
117  num_bytes = 400 - tmp;
118 
119  } else {
120  num_bytes = r.get_data_length();
121  }
122  if (r.is_read()) {
123  for (unsigned int i = 0; i < num_bytes; ++i) {
124  r.get_data_ptr()[i] = mMem[i + tmp];
125  }
126 
127  } else {
128  for (unsigned int i = 0; i < num_bytes; ++i) {
129  mMem[i + tmp] = r.get_data_ptr()[i];
130  }
131  }
132  return num_bytes;
133  }
134 
135  bool myGetDMIPtr(transaction_type& trans,
136  tlm::tlm_dmi& dmi_data)
137  {
138  // notify DMI invalidation, just to check if this reaches the
139  // initiators properly
141 
142  // Check for DMI extension:
143  my_extension * tmp_ext;
144  trans.get_extension(tmp_ext);
145  if (tmp_ext)
146  {
147  std::cout << name() << ": get_direct_mem_ptr OK, extension data = "
148  <<tmp_ext->m_data << std::endl;
149  }
150  else
151  {
152  std::cout << name() << ", get_direct_mem_ptr ERROR: "
153  << "didn't get pointer to extension"
154  << std::endl;
155  }
156  if (trans.get_address() < 400) {
157  dmi_data.allow_read_write();
158  dmi_data.set_start_address(0x0);
159  dmi_data.set_end_address(399);
160  dmi_data.set_dmi_ptr(mMem);
163  return true;
164 
165  } else {
166  // should not happen
167  dmi_data.set_start_address(trans.get_address());
168  dmi_data.set_end_address(trans.get_address());
169  return false;
170 
171  }
172  }
173 
174  void invalidate_dmi_method()
175  {
176  sc_dt::uint64 start_address = 0x0;
177  sc_dt::uint64 end_address = 399;
178  socket->invalidate_direct_mem_ptr(start_address, end_address);
179  }
180 private:
181  unsigned char mMem[400];
184 };
185 
186 #endif
SimpleLTTarget_ext::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: SimpleLTTarget_ext.h:54
SimpleLTTarget_ext::socket
target_socket_type socket
Definition: SimpleLTTarget_ext.h:59
data
const char data[]
Definition: circlebuf.test.cc:42
sc_core::sc_module
Definition: sc_module.hh:97
SimpleLTTarget_ext::myGetDMIPtr
bool myGetDMIPtr(transaction_type &trans, tlm::tlm_dmi &dmi_data)
Definition: SimpleLTTarget_ext.h:152
tlm::tlm_phase
Definition: phase.hh:47
tlm::tlm_dmi::allow_read_write
void allow_read_write()
Definition: dmi.hh:124
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
SimpleLTTarget_ext::mMem
unsigned char mMem[400]
Definition: SimpleLTTarget_ext.h:198
sc_core
Definition: messages.cc:31
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
sc_core::sc_module::sc_module
sc_module()
Definition: sc_module.cc:256
SimpleLTTarget_ext::m_invalidate_dmi_time
sc_core::sc_time m_invalidate_dmi_time
Definition: SimpleLTTarget_ext.h:200
tlm_utils::simple_target_socket_b::register_transport_dbg
void register_transport_dbg(MODULE *mod, unsigned int(MODULE::*cb)(transaction_type &))
Definition: simple_target_socket.h:125
sc_assert
#define sc_assert(expr)
Definition: sc_report_handler.hh:135
tlm::tlm_generic_payload::set_dmi_allowed
void set_dmi_allowed(bool dmi_allowed)
Definition: gp.hh:256
SimpleLTTarget_ext::m_invalidate_dmi_event
sc_core::sc_event m_invalidate_dmi_event
Definition: SimpleLTTarget_ext.h:199
sc_core::SC_NS
@ SC_NS
Definition: sc_time.hh:43
tlm::tlm_dmi::set_end_address
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:117
tlm::tlm_generic_payload::get_command
tlm_command get_command() const
Definition: gp.hh:197
SimpleLTTarget_ext::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: SimpleLTTarget_ext.h:52
my_extension::m_data
int m_data
Definition: my_extension.h:64
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
sc_core::sc_module::dont_initialize
void dont_initialize()
Definition: sc_module.cc:336
tlm::tlm_dmi::set_read_latency
void set_read_latency(sc_core::sc_time t)
Definition: dmi.hh:118
SC_METHOD
#define SC_METHOD(name)
Definition: sc_module.hh:299
SimpleLTTarget_ext::SimpleLTTarget_ext
SimpleLTTarget_ext(sc_core::sc_module_name name, sc_core::sc_time invalidate_dmi_time=sc_core::sc_time(25, sc_core::SC_NS))
Definition: SimpleLTTarget_ext.h:63
sc_core::sc_event
Definition: sc_event.hh:169
MipsISA::r
r
Definition: pra_constants.hh:95
sc_core::sc_time
Definition: sc_time.hh:49
SimpleLTTarget_ext::myNBTransport
sync_enum_type myNBTransport(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
Definition: SimpleLTTarget_ext.h:80
sc_core::sc_module_name
Definition: sc_module_name.hh:41
tlm_utils::simple_target_socket_b::register_get_direct_mem_ptr
void register_get_direct_mem_ptr(MODULE *mod, bool(MODULE::*cb)(transaction_type &, tlm::tlm_dmi &))
Definition: simple_target_socket.h:133
tlm::tlm_generic_payload::get_extension
void get_extension(T *&ext) const
Definition: gp.hh:381
tlm_utils::simple_target_socket
Definition: simple_target_socket.h:605
sc_core::sc_event::notify
void notify()
Definition: sc_event.cc:337
SimpleLTTarget_ext::target_socket_type
tlm_utils::simple_target_socket< SimpleLTTarget_ext, 32, my_extended_payload_types > target_socket_type
Definition: SimpleLTTarget_ext.h:56
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
SimpleLTTarget_ext::invalidate_dmi_method
void invalidate_dmi_method()
Definition: SimpleLTTarget_ext.h:191
tlm::tlm_dmi::set_write_latency
void set_write_latency(sc_core::sc_time t)
Definition: dmi.hh:119
tlm::tlm_generic_payload
Definition: gp.hh:133
my_extended_payload_types
Definition: my_extension.h:50
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
SimpleLTTarget_ext::phase_type
tlm::tlm_phase phase_type
Definition: SimpleLTTarget_ext.h:53
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
tlm::tlm_dmi::set_dmi_ptr
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:115
tlm::tlm_dmi::set_start_address
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:116
my_extension
Definition: my_extension.h:26
SimpleLTTarget_ext::transport_dbg
unsigned int transport_dbg(transaction_type &r)
Definition: SimpleLTTarget_ext.h:127
sc_core::sc_module::sensitive
sc_sensitive sensitive
Definition: sc_module.hh:206
SimpleLTTarget_ext::SC_HAS_PROCESS
SC_HAS_PROCESS(SimpleLTTarget_ext)
SimpleLTTarget_ext
Definition: SimpleLTTarget_ext.h:32
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:128
tlm::tlm_generic_payload::get_data_ptr
unsigned char * get_data_ptr() const
Definition: gp.hh:205
my_extension.h
tlm_utils::simple_target_socket_b::register_nb_transport_fw
void register_nb_transport_fw(MODULE *mod, sync_enum_type(MODULE::*cb)(transaction_type &, phase_type &, sc_core::sc_time &))
Definition: simple_target_socket.h:108
tlm::tlm_generic_payload::set_response_status
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:221

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