gpu_tlb.hh File Reference

#include <fstream>
#include <list>
#include <queue>
#include <string>
#include <vector>
#include "arch/generic/tlb.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/regs/segment.hh"
#include "base/callback.hh"
#include "base/logging.hh"
#include "base/statistics.hh"
#include "gpu-compute/compute_unit.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/X86GPUTLB.hh"
#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"

Go to the source code of this file.

Classes
class	X86ISA::GpuTLB
class	X86ISA::GpuTLB::Translation
class	X86ISA::GpuTLB::CpuSidePort
class	X86ISA::GpuTLB::MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...
struct	X86ISA::GpuTLB::TranslationState
	TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...
class	X86ISA::GpuTLB::TLBEvent
struct	X86ISA::GpuTLB::AccessInfo
	This hash map will use the virtual page address as a key and will keep track of total number of accesses per page. More...

Namespaces
	X86ISA
	This is exposed globally, independent of the ISA.